Commit Graph

41174 Commits

Author SHA1 Message Date
Eric Lai 6f06883856 mb/google/mancomb: Enable CONFIG_CHROMEOS
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I45dcaa8b430721f864d4e5d78ae60883175085c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11 15:07:41 +00:00
Eric Lai 6bb5b9a058 mb/google/mancomb: Add stubs to configure GPIOs
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I7de5e4a4d2273d0ea5a84210ea0ce28d312eaa95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11 15:07:06 +00:00
Subrata Banik 0603902525 soc/intel/common/block/cpu: Use tab instead of space
Convert the lines starts with whitespace with tab as applicable.

TEST=Built google/brya0 and ADLRVP with BUILD_TIMELESS=1: no changes.

Change-Id: Ibd11ad12caa1be866a851a8cd4bd23349e8ffbbe
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51375
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11 05:06:43 +00:00
Jonathan Zhang 492a792d38 soc/intel/common/block: Add PCI IDs for EmmitsBurg PCH
According to Intel EmmitsBurg EDS, doc# 606161:
* Add PCI devid for SPI.
* Add PCI devid for ESPI (LPC).

EmmitsBurg (EBG) PCH is used in the chipset with Sapphire Rapids
Scalable Processor (SPR-SP).

Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ie8925cb739c95c34febf9002149de437d19c8234
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-11 04:26:21 +00:00
Mathew King 238242bda4 mb/google/guybrush: Enable USB ports in devicetree
BUG=b:180529005
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I94d97a38d992f46b32c2c6aca4c8da688d3b76fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51257
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11 01:17:40 +00:00
Mathew King 72cdbfa2f3 mb/amd/majolica: Enable USB ACPI in devicetree
BUG=b:180529005
TEST=boot majolica, all USB ports work

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I6d3506bb4d54c7f8ea1e53576ef68d2aface6c89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-11 01:17:09 +00:00
Mathew King 641690b7ae mb/google/guybrush: Enable Chrome EC SKUID and BOARDID
BUG=b:181910592
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I7851d3b11ea3b026b999019d02df1144f8393753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-11 01:16:20 +00:00
Mathew King 454426d9d0 mb/google/guybrush: Log mainboard events to elog
BUG=b:180653357
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ifd43d9cc1832d8ed8d90c68ba88b5667e3c04f89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-11 01:14:32 +00:00
Mathew King 78f0301ba4 mb/google/guybrush: Add chomeec device to lpc bridge
BUG=b:180507937
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I7b8b2ab73d66e0aaa0e9b7570661c885f7f777ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51296
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 23:49:11 +00:00
Mathew King c519bff9c1 soc/amd/cezanne: Add USB ports to chipset.cb
BUG=b:180529005
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I16de0869abd1eff4e89cf1b8128775858702acb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-10 23:47:03 +00:00
Kane Chen 807ce6258a mb/google/zork/var/shuboz: support regular/numpad touchpad
Define the 26th bit of the fw_config for the regular touchpad
and numpad touchpad selection.

REGULAR_TOUCHPAD: 1
NUMPAD_TOUCHPAD: 0

BUG=b:174964012
BRANCH=zork
TEST=build pass

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ie2055d6bb45a64bc0e59209cecc0f8a31c0f3718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-10 23:44:49 +00:00
Angel Pons 06b20ceb2f mb/{amd/padmelon,google/zork}: Do not select `VGA_BIOS`
The VGA BIOS for AMD Padmelon and Google Zork are stored in `amd_blobs`.
Do not force inclusion of VGA BIOS when `USE_AMD_BLOBS` is not enabled.

Change-Id: I206e8fadc14ec0d9b162dc4d72813fdd3d43958b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-10 23:42:53 +00:00
Angel Pons 83f9f8983b mainboard: Drop unnecessary `VGA_BIOS` default
This option defaults to n already.

Change-Id: I9f6407152f7cf2e2ac6fd1fff874e400f89a27ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-10 23:35:00 +00:00
Raul E Rangel 42c5b010b6 soc/amd/picasso: Fix PSP_SHAREDMEM_BASE
PSP_SHAREDMEM_BASE made the assumption that _psp_sharedmem_dram would
only match once. With CB:49332 there are now two symbols, and it was
grabbing the wrong one.

This change makes it so we match the exact symbol. It also switches to
using awk to simplify the code.

The bootblock.elf target that is added to the list of prerequisites also
creates the bootblock.map file that gets used to extract the base
address of the _psp_sharedmem_dram symbol.

BUG=b:181354692
TEST=Boot zork past bootblock

Fixes: 82d16b150c ("memlayout: Store region sizes as separate symbols")
Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I79675bd73f964282b54bca858830e26de64037c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-10 23:32:46 +00:00
Matt Papageorge a37ec522e1 mb/amd/majolica: Update to use proper APCBs built for Majolica
Some of the previous binaries were incorrect and should not be used
for Majolica because they are templates instead of APCBs specifically
built for the board. This APCB update also places the UMA region under
4G and size 32 MB which is essential for video output.

TEST=Boot with UEFI BIOS and verify we can get to OS. Also verify memory
region size, base and alignment.

Change-Id: Id797e2ad5bd67815c09752aedc19dad7dcf8ad12
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-10 23:28:19 +00:00
Kane Chen d3a767f47e mb/google/zork/var/shuboz: adjust I2C2 data hold time for TP
Add ".data_hold_time_ns" to follow I2C specification.
The adjusted result aobut 0.315us(more than 0.3us)

BUG=b:181091107
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Id92fadcb54b9722709e32ced1f0be001b8c97975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-10 23:10:30 +00:00
Nikolai Vyssotski ad68e69612 soc/amd/common/block/graphics/graphics: GOP: implement vbt_get()
Even though AMD does not need VBT we still need to implement the
vbt_get() function to not break the build with GOP driver enabled
(see fsps_return_value_handler() in fsp2_0/silicon_init.c

BUG=b:171234996
BRANCH=Zork

Change-Id: I80a5131a9852a05998b55b847243748d24cf535f
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-10 23:07:08 +00:00
Mathew King 612e403d53 mb/google/zork: Use SOC defines instead of magic numbers
BUG=b:182269526
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I351fb4fc493bb92b31e2c8bc946dfb048045335c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-10 23:05:41 +00:00
Mathew King 729c61961c soc/amd/picasso: Allow GPIO defines to be used in ASL
BUG=b:182269526
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ib33a46a6eead84eaff2c4ac320800b7993f5c3f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-10 23:05:27 +00:00
John Su 2f67b34e12 mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
To define Mainboard Type config, use the fw_config bit[26].
Check MB Type to modify SDLE settings for different VCORE IC.

BUG=b:177193131
BRANCH=zork

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-10 23:04:32 +00:00
Chris Wang 216d69d459 mb/google/zork: add UPDM updating function before runing FSP-M
Add the UPD updating hook in early stage for customization.

BUG=b:117719313
BRANCH=zork
TEST=build,check the hook function been executed.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4954a438a51b29b086015624127e651fd06f971b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51181
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 23:03:59 +00:00
Felix Held 9a6bc07cc2 soc/amd/cezanne: select common APOB NV cache code
BUG=b:181766974

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I660f19d18810c35dafcd75bcd1993216b7b09644
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51268
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 20:44:45 +00:00
Ronak Kanabar e1a27f2e49 vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2081_02
The headers added are generated as per FSP v2081_02.
Previous FSP version was v2037.
Changes Include:
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
- Add DevIntConfigPtr and NumOfDevIntConfig UPDs in Fsps.h

BUG=b:180758116
BRANCH=None
TEST=Build and boot ADLRVP

Cq-Depend: chrome-internal:3669105
Change-Id: Ib99748a428709ffad27d47f600e00bd91b70d8f3
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51248
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 20:30:20 +00:00
Jakub Czapiga 1add483819 tests/Makefile.inc: Enable support for multiple test groups
Until now output of all test groups run in single unit test were
saved in the same file which caused Jenkins to fail because
of existence of multiple root XML elements.
Now each test group is saved to its own file containing its name
at the end of the filename.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I21ba512073bc8d8693daad8a9b86d5b076bea03f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-03-10 20:23:19 +00:00
Gwendal Grignou 689c25b9d6 drivers/i2c: sx9310: Replace register map with descriptive names
The current driver is using chip registers map to configure the SAR
sensor, which is opaque, especially when the datasheet is not published
widely.

Use more descriptive names, as defined in Linux kernel documentation at
https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/proximity/semtech%2Csx9310.yaml

BUG=b:173341604
BRANCH=volteer
TEST=Dump all tables, check semtech property:
for i in $(find  /sys/firmware/acpi/tables/ -type f) ; do
 f=$(basename $i);  cat $i > /tmp/$f.dat ; iasl -d /tmp/$f.dat
done
In SSDT.dsl, we have:
Package (0x06)
 {
     Package (0x02)
     {
         "semtech,cs0-ground",
         Zero
     },
     Package (0x02)
     {
         "semtech,startup-sensor",
         Zero
     },
     Package (0x02)
     {
         "semtech,proxraw-strength",
         Zero
     },
     Package (0x02)
     {
         "semtech,avg-pos-strength",
         0x0200
     },
     Package (0x02)
     {
         "semtech,combined-sensors",
         Package (0x03)
         {
             Zero,
             One,
             0x02
         }
     },
     Package (0x02)
     {
         "semtech,resolution",
         "finest"
     }
 }

Change-Id: I8d1c81b56eaeef1dbb0f73c1d74c3a20e8b2fd7b
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-10 19:33:01 +00:00
Felix Held e4a7e46a9c soc/amd/stoneyridge/smihandler: sort includes alphabetically
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib317493fe938fe961aed06557e655ed8498e2694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-10 19:18:03 +00:00
Felix Held 2966e0d863 soc/amd/stoneyridge/smihandler: remove unused device/pci_def.h include
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I388cdb1fb9b3decaa6eb6e0e4e538c620d3048a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-10 19:17:56 +00:00
Angel Pons 34be1be240 nb/intel/haswell: Finalize northbridge in ramstage
There's no need to finalize the northbridge in SMM. This also makes
unification with Broadwell easier.

Tested on Asrock B85M Pro4, still boots and registers get locked.

Change-Id: I8b2c0d14a79e4fcd2e8985ce58542791cef9b1fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-10 10:59:36 +00:00
Angel Pons ae999503f6 nb/intel/haswell/pcie.c: Add missing pre-ASPM init
Add devicetree configuration parameters for mainboard-specific settings,
and provide reasonable defaults, which should usually be good enough.
This is based on Haswell SA Reference Code version 1.9.0 (Nov 2014).

Tested on Asrock B85M Pro4, registers now have the expected values.

Change-Id: I0dcdd4ca431c2ae1e62f2719c376d8bdef3054bd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47223
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 10:08:45 +00:00
Angel Pons 517750745f soc/intel/common/block/smm: Ignore PM1 and GPE0 events in SCI mode
When the SCI_EN bit is set, PM1 and GPE0 events will trigger a SCI
instead of a SMI#. However, SMI_STS bits PM1_STS and GPE0_STS can
still be set. Therefore, when SCI_EN is set, ignore PM1 and GPE0
events in the SMI# handler, as these events have triggered a SCI.
Do not ignore any other SMI# types, since they cannot cause a SCI.

Note that these bits are reserved on APL and GLK. However, SoC-specific
code already accounts for it. Thus, no special handling is needed here.

Change-Id: I5998b6bd61d796101786b57f9094cdaf0c3dfbaa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-10 09:52:22 +00:00
Hsin-Hsiung Wang 8d735d2aa3 soc/mediatek/mt8192: mt6315: revise initial setting
Remove unused boot status settings.
Reset the power-off sequence to zero to meet hardware requirement.

BUG=b:179000151
BRANCH=none
TEST=boot asurada correctly

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: Ie9d39be532ec378bd6df6bf1b93307dae4068fc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51246
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 01:29:14 +00:00
Hsin-Hsiung Wang 8579f23353 soc/mediatek/mt8192: mt6315: update initial flow
We saw EXT_PMIC_EN1 and PPVAR_DVDD_PROC_BC power off sequence
failure, and after checking MT6315 MT6315 PMIC protection key
summary.xlsx and MT6315 Top and CLK programming guide.docx,
we found there are something wrong about the sequence of magic
key protection flow and clk setting. Update correct initial
flow.

BUG=b:179000151
BRANCH=none
TEST=boot asurada correctly

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I1b7f970a44904fda09a97f4064eef7c95feefad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51245
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 01:29:07 +00:00
Hsin-Hsiung Wang 670cd9719e soc/mediatek/mt8192: mt6315: update correct slave id
The initial settings for MT6315 were not applied correctly
because the setup process didn't specify correct slave id
(incorrectly always sending 0), and may cause failure in
power off sequence.

BUG=b:179000151
BRANCH=none
TEST=boot asurada correctly

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: Ifd04da8ac55bcc9f9fdbc088d430522c2725ad47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-10 01:28:58 +00:00
Mathew King bac0f26e08 drivers/usb/pci_xhci: Add cezanne xhci pci devce id
BUG=b:180529005
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I836bb838cc97593451f869490ff3c9dd156245b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51349
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 00:47:18 +00:00
Mathew King ee10ce6268 mb/google/guybrush: Add smihandler
BUG=b:180507707
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I25ce0ca869ca854ff33242d2c416319e9688cc6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51264
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 00:38:23 +00:00
Mathew King ad83023425 mb/google/guybrush: Enable Chrome EC
BUG=b:180507937
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I3cdd6422b1bc53ea934346327359cbc6d86baeeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51043
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 00:35:06 +00:00
Felix Held 15c4345cfd soc/amd/picasso/smihandler: sort includes alphabetically
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I674cff3352cd9f5d20b3d8f7e77339d045cadbb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51357
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 00:31:38 +00:00
Felix Held 3680e02e9e soc/amd/cezanne/smihandler: add ELOG and SMMSTORE support
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6bad684bc6a36bb4a2b83d10ff9da1c136f8bbd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51356
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 00:30:15 +00:00
Felix Held 6890d935d8 soc/amd/picasso/smihandler: remove unused device/pci_def.h include
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If4f75eadca101593cf37faf2722f4ea8f509a1f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51355
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 00:30:01 +00:00
Felix Held 90bcdb436a soc/amd/*/smihandler: factor out ELOG and SMMSTORE handler
This also replaces the southbridge_ prefix of the handler functions with
a handle_ prefix.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib6ea1f4e2700c508a8bf72c488043e276ba4a062
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51354
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 00:29:48 +00:00
Felix Held 4324bc60d5 soc/amd/cezanne/Makefile: pass APOB NV parameters to amdfwtool
BUG=b:181766974

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I99d5984da82cfc98a106fc5c27e32fdc3cc13b3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-09 20:43:18 +00:00
Felix Held 8ea26aebb9 soc/amd/picasso/Makefile: simplify APOB NV parameter extraction
TEST=Timeless build of amd/mandolin results in identical binary.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Raul Rangel <rrangel@chromium.org>
Change-Id: Ie0e69532b7d13df87e2d9333ed34dbb008d2cc84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-09 20:43:06 +00:00
Tim Wawrzynczak 885e84eb4d mb/google/brya: Define ChromeOS GPIO support in ACPI tbales
Define the ChromeOS GPIOs (physical write-protect and virtual recovery
mode) in ACPI tables so the OS knows which physical pad is used for them.

BUG=b:181887865
TEST=flashrom_tester is able to "see" the WP GPIO

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I3feed366afd6507894a1d31304891cc785a4d314
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51347
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-09 18:45:13 +00:00
Tim Wawrzynczak 659a591aa7 mb/google/brya: Reorganize flashmap
Intel ADL-P supports an additional memory-mapped 16MiB window into the
platform SPI flash. Support for this window already exists at the SoC
level, so all that is needed is to properly organize the flash map to
take advantage of this. FW_SECTION_A moves down to the bottom of the
available space in the lower 16MiB half, and FW_SECTION_B moves to the
bottom of the top 16MiB half. RW_LEGACY is squashed down to 2M.

BUG=b:182088676
TEST=build and boot to OS from FW_MAIN_A

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I60483b7e638c0a7e41f1f7e2b5503ae02e9906bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-09 18:45:00 +00:00
Marc Jones 6545145f0d soc/intel/xeon_sp: Set SMI lock
Prevent writes to Global SMI enable as recommended by the BWG.

Change-Id: I7824464e53a2ca1e860c1aa40d8a7d26e948c418
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-03-09 16:51:13 +00:00
Marc Jones 81ef9c21da soc/intel/xeon_sp: Add PCH lockdown
Add SOC_INTEL_COMMON_PCH_LOCKDOWN and PMC_GLOBAL_RESET_ENABLE_LOCK
to meet device security requirements.

LOCKDOWN has dependencies on SOC_INTEL_COMMON_PCH_BASE and
several other common block devices. Add COMMON_PCH_BASE and
COMMON_PCH_SERVER to pick up LOCKDOWN and the dependencies.

COMMON_PCH_SERVER adds the following common devices that were not
previously included by XEON_SP:
SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
SOC_INTEL_COMMON_BLOCK_CSE
SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
SOC_INTEL_COMMON_BLOCK_ITSS
SOC_INTEL_COMMON_PCH_LOCKDOWN
SOC_INTEL_COMMON_BLOCK_SATA
SOC_INTEL_COMMON_BLOCK_SMBUS
SOC_INTEL_COMMON_BLOCK_XHCI

Change-Id: Iab97123e487f4f13f874f364a9c51723d234d4f0
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-03-09 16:50:25 +00:00
Marc Jones bab0544200 soc/intel/common/pch: Add server PCH option
Add a server Kconfig option to select a subset of common PCH devices.
Client devices are included if server isn't selected. This maintains
the current Kconfig behavior.

Change-Id: If11d1a51192dd87ad770b8aa53ce02b6a28b8da8
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-03-09 16:50:10 +00:00
Yu-Ping Wu 3322d33e08 mb/google/asurada: Enlarge CONSOLE_CBMEM_BUFFER_SIZE
Enlarge CONSOLE_CBMEM_BUFFER_SIZE from 128K (default) to 512K, so that
more DRAM calibration logs can be stored in CBMEM console.

BUG=b:181933863
TEST=emerge-asurada coreboot
TEST="cbmem -c" shows the whole full calibration log
BRANCH=none

Change-Id: If82cbee5d2d5e97d98cbdaecda739d91a7cca0f8
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51275
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-09 08:14:26 +00:00
Eric Lai c03ab47dc4 mb/google/octopus/var/fleex: Only check LTE sku on fleex
Fleex has other project share the same FW. Only fleex has LTE sku.
So we need to make sure it is fleex then check if LTE sku.

BUG=b:181946744
BRANCH=octopus
TEST=Check no SAR table can be loaded with sku id 4 and 5.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9f3d5fed4315fc716acad1a07735221d154c377e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
2021-03-09 03:38:47 +00:00
Raul E Rangel 8e6059db28 soc/amd,mb/google/,mb/amd: Move sleepstates.asl
This file is common for all the AMD platforms.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I10ee600b4bcd7aaff39bfab075eb4dbc9096b435
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51299
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08 23:30:38 +00:00