1. Exportable options ('export used') used to be exported if referred to in
a 'uses' statement. These options will now only be exported if the
option is set, or the default value is changed.
2. Options marked as 'export always' with no default value ('default none')
used to generate defines with no values 'export k8:='. This behavior
has changed so that the option will ONLY be exported if it has a value
assigned using 'set' or 'default'. Otherwise it is an error.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
than for loop. Please forgive me, I was too young 4 years ago.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
use standard product ID exit method for w49f002u
move udelay stuff into its own file
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Reworked pnp superio device support. Now complete superio support is less than 100 lines.
- Added support for hard coding resource assignments in Config.lb
- Minor bug fixes to romcc
- Initial support for catching the x86 processor BIST error codes. I've only seen
this trigger once in production during a very suspcious reset but...
- added raminit_test to test the code paths in raminit.c for the Opteron
- Removed the IORESOURCE_SET bit and added IORESOURCE_ASSIGNED and IORESOURCE_STORED
so we can tell what we have really done.
- Added generic AGP/IOMMU setting code to x86
- Added an implementation of memmove and removed reserved identifiers from memcpy
- Added minimal support for booting on pre b3 stepping K8 cores
- Moved the checksum on amd8111 boards because our default location was on top of
extended RTC registers
- On the Hdama added support for enabling i2c hub so we can get at the temperature
sensors. Not that i2c bus was implemented well enough to make that useful.
- Redid the Opteron port so we should only need one reset and most of memory initialization
is done in cpu_fixup. This is much, much faster.
- Attempted to make the VGA IO region assigment work. The code seems to work now...
- Redid the error handling in amdk8/raminit.c to distinguish between a bad value
and a smbus error, and moved memory clearing out to cpufixup.
- Removed CONFIG_KEYBOARD as it was useless. See pc87360/superio.c for how to
setup a legacy keyboard properly.
- Reworked the register values for standard hardware, moving the defintions from
chip.h into the headers of the initialization routines. This is much saner
and is actually implemented.
- Made the hdama port an under clockers BIOS. I debuged so many interesting problems.
- On amd8111_lpc added setup of architectural/legacy hardware
- Enabled PCI error reporting as much as possible.
- Enhanded build_opt_tbl to generate a header of the cmos option locations so
that romcc compiled code can query the cmos options.
- In romcc gracefully handle function names that degenerate into function pointers
- Bumped the version to 1.1.6 as we are getting closer to 2.0
TODO finish optimizing the HT links of non dual boards
TODO make all Opteron board work again
TODO convert all superio devices to use the new helpers
TODO convert the via/epia to freebios2 conventions
TODO cpu fixup/setup by cpu type
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
1. Options can only be set with 'option' statement in the target
configuration file. Options can be set as many times as needed.
2 Option DEFAULT values can be changed (or set) in any configuration file.
Changing a default value will display a warning message.
3. A default value is changed with the statement 'default <op> = <val>'.
4. Setting an option overrides the default value.
5. The 'mainboard' and 'arch' statements now set options implicitly. No
'uses' statement is required.
The idea is that parts will define default values for options that
they need/use. Option overrides are only done in the target file.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Support for compiling romcc on non x86 platforms
- new romc options -msse and -mmmx for specifying extra registers to use
- Bug fixes to device the device disable/enable framework and an amd8111 implementation
- Move the link specification to the chip specification instead of the path
- Allow specifying devices with internal bridges.
- Initial via epia support
- Opteron errata fixes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
for paths
- Renamed some configuration variables
SMP -> CONFIG_SMP
MAX_CPUS -> CONFIG_MAX_CPUS
MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
- Removed some dead configuration variables
MAX_CPUS -> CONFIG_MAX_CPUS
MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
SMP -> CONFIG_SMP
FINAL_MAINBOARD_FIXUP
SIO_BASE
SIO_SYSTEM_CLK_INPUT
NO_KEYBOARD
USE_NORMAL_IMAGE
SERIAL_CONSOLE
USE_ELF_BOOT
ENABLE_FIXED_AND_VARIABLE_MTRRS
START_CPU_SEG
DISABLE_WATCHDOG
ENABLE_IOMMU
AMD8111_DEV
- Removed some assembly files that are no longer needed
killed src/southbridge/amd/amd8111/smbus.inc
killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc
killed src/ram/ramtest.inc
- Updates to config.g so that it works more reliably and has initial support
for paths
- Renamed some configuration variables
SMP -> CONFIG_SMP
MAX_CPUS -> CONFIG_MAX_CPUS
MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
- Removed some dead configuration variables
MAX_CPUS -> CONFIG_MAX_CPUS
MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
SMP -> CONFIG_SMP
FINAL_MAINBOARD_FIXUP
SIO_BASE
SIO_SYSTEM_CLK_INPUT
NO_KEYBOARD
USE_NORMAL_IMAGE
SERIAL_CONSOLE
USE_ELF_BOOT
ENABLE_FIXED_AND_VARIABLE_MTRRS
START_CPU_SEG
DISABLE_WATCHDOG
ENABLE_IOMMU
AMD8111_DEV
- Removed some assembly files that are no longer needed
killed src/southbridge/amd/amd8111/smbus.inc
killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc
killed src/ram/ramtest.inc
killed src/sdram/generic_dump_spd.inc
killed src/sdram/generic_dump_spd.inc
- Updated the arima/hdama to build with the new configuration system
- Updated config.g to list all of the variables with make echo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
cpu of a certain type and to eliminate the
cpu p5
cpu p6
cpu k7
nonsense in the old config files.
Next step is to hook into Eric's pci device stuff.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
device arrangement that can be statically configured during boot.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Li-Ta Lo