ACPI device ID of IOM device has been changed for Alder Lake.
Updating it to make it compatible with kernel
TEST=ACPI ID is updated and kernel driver works as expected
Cq-Depend: chromium:2936144
Change-Id: Ifdfcd0c1534e8204719e59e718688cd42e846e84
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We were not adding power management handling of GPIO_COM3 in gpio.asl
This can affect s0ix flow where platform won't go into s0ix since
GPIO_COM3 is not power gated.
BUG=b:188392183
BRANCH=None
TEST=Platform should enter to s0ix and GPIO COMM3 should not block an
entry to s0ix.
Change-Id: I3f269c66bdd6337adb0d2bd29d0b7d72ced19ec4
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Check TBT NVM FW Ready (INFR) bit to skip D3Cold for TBT when device
is in disconnected state.
Not adhering this recommendation is blocking the S0ix state transition.
BUG=b:183670327
TEST=S0ix state transition occurs with TBT disconnected.
Change-Id: Ib9b9ceee4393aeba37fdcb4e05d1b279a6ff72d2
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Each TCSS DMA is grouped together with two PCIe RPs in terms of PM flow.
This change ensures that SD3C is updated for the TCSS DMA devices
corresponding to the TBT RP ports. If TBT port is 0 or 1, SD3C for DMA0
is updated, else for DMA1.
BUG=None
TEST=Built Alderlake image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia3462dfbb287a374960a57bb4c3541db2a435611
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51965
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Lists of changes:
1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS
2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to
soc/gpio.h. Refer to detailed description below to understand the
motivation behind this change.
An advanced GPIO PM capabilities has been introduced since CNP PCH,
refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions.
Now with TGP PCH, additional bits are defined in the MISCCFG register
for GPIO PM control. This results in different SoCs supporting
different number of bits. The bits defined in earlier platforms
(CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the
common GPIO code to keep the bit definitions in intelblock/gpio.h, but
the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so
that each SoC can provide this as per hardware support.
TEST=On ADL, TGL and JSL platform.
Without this CL :
GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable)
With this CL :
GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable)
Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Drop the 100ms delay in the _PS0 method because kernel already adds this
100ms. This change also drops polling TBT PCIe root ports Link Active
State because this scheme is not applicable for SW CM.
BUG=None
TEST=Built Alderlake coreboot image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51191
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The _DSD is generated at runtime using the Intel common pcie
driver, therefore remove it from the ASL files.
BUG=b:182522802, b:182478306
TEST=boot into latest kernel, no thunderbolt driver errors
seen
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iee25a77bf5cc6636f46a5c32f3eeabe8524e0a04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51454
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The _DSD is generated at runtime using the Intel common USB4
driver, therefore remove it from the ASL files.
BUG=b:182522802, b:182478306
TEST=boot into latest kernel, no thunderbolt driver errors
seen
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I77dc283aeb5f52191255137e941487cf68cb7970
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51453
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The iGPU is on the northbridge or system agent, not the southbridge.
Change-Id: Ic63a7ad532fd1faa8e90d44bf7269040fa901757
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Both the IO-APIC and PIC mode PCI IRQ tables are incorrect for ADL; the
2nd field in each package is supposed to be pin, not function number,
and some of the IRQ #s differ from what the FSP programs, therefore
align the ACPI table to match what the FSP is currently programming.
BUG=b:180105941
TEST=boot brya, no more `GSI INT` or `failed to derive IRQ routing`
errors seen in dmesg
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I182be69e8d9ebd854ed74dbb69f4d1f1a539cf2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Replace the two obsolete LPID implementations with the new PEPD device.
The PEPD device gets included in the plaforms' `southbridge.asl`, since
it is required to load the `intel_pmc_core` module in Linux, which
checks for the _HID. (See CB:46469 for more info on that.)
There is no harm for mainboards not supporting S0ix, because the _DSM
function won't be called with the LPS0 UUID on such boards. Such boards
can use the debugging functionality of `intel_pmc_core`, too.
Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46471
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake up from sleep states.
3. Add SoC ASL code in ASL 2.0 syntax for SoC IPs like IPU, ISH,
LAN, HDA etc.
Change-Id: I7509e8c46038b1edfc501db74e763f198efb56ab
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
