This includes the Cedar Island FSP which is used by xeon_sp/cpx.
Also updates EHL FSP to latest MR1 version.
Change-Id: I1c2d440ce0f20a0922e5d91f615771843281fca6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57488
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 4423276b:
2021-08-31 17:41:34 +0000 - (crossystem: add a hwid override mechanism from chromeos-config)
to commit id c5a482ed:
2021-09-08 17:16:59 +0000 - (sign_official_build: disable gsetup for reven)
This brings in 10 new commits.
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: I67d4bfa182eae98bb23ae487f117c991502b66ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Update submodule pointer to include microcode for TGL and others.
Tested the following still boot:
- galp3-c (WHL-U): sig=0x806eb pf=0x80 revision=0xe9
- oryp5 (CFL-H): sig=0x906ea pf=0x20 revision=0xe9
- gaze15 (CML-H): sig=0xa0652 pf=0x20 revision=0xe9
coreboot reports the revision as -1 from what it actually is. i.e.,
these should report revision=0xea (and that is what Linux reports).
However, this behavior is not new.
Change-Id: I084ba67e8eaf7383f1c05fa5589b63c92ff900b1
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56861
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that gsi_fw blob has landed, need to uprev the qc_blobs.
Change-Id: I0bf67a560ee2e5d771bdb71b60e3d3d372dad567
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56776
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 1e800ac83:
2021-03-01 22:59:54 +0000 - (docs: point md files in master to main/HEAD)
to commit id 4c21b57eb:
2021-07-19 11:36:07 +0000 - (pd: Fix missing polarity_rm_dts in some conditions)
This brings in 3145 new commits.
Change-Id: Iff2e9f766e750070d71644c2f9895ad10e8b1c9a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56431
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 96404aa27:
2021-05-13 18:27:27 +0200 - (Merge "build(hooks): update Commitizen to ^4.2.4" into integration)
to commit id 586aafa3a:
2021-07-19 05:36:18 +0200 - (Merge "errata: workaround for Neoverse V1 errata 1791573" into integration)
This brings in 207 new commits.
Change-Id: Iaf8af5ffaf377070ee1430ed7cfdc51001a1ba6b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56416
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that cpucp blobs have landed, need to uprev the qc_blobs.
Change-Id: I62dc410cee7baf5efa5c0406f35ee05a535f49b1
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Updating from commit id b38e3a63:
cros_ec: Use boot mode to check if EC can be trusted
to commit id ccc56f4:
vboot: add x86 SHA256 ext support
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I4e170e84a12646386d3fd84ae97add6c19f23809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This updates the intel-sec-tools submodule pointer to include a fake
acm binary to be included for buildtesting.
Change-Id: Id4a9e177f71306b8c5538a578da229a53d19487a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This brings in three new commits that are mostly concerned about
fixing the build with gcc 11.
Change-Id: I35f9100e2bfb2a261b3a0a128697550caf5840d9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55498
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This update adds a commit to fix building libgfxinit with gcc 11
Change-Id: I5c0e3823ab7219667f9430bce74e4f2fba0c0c3a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The commit currently being pointed to is unreachable. Use the same
commit that exists in a reachable branch.
Fixes: Commit 1128817ed6
(3rdparty/intel-sec-tools: Update to support Boot Guard)
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: I1cfc08d48fe5471592fea1013e8b43bea5d7b565
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55414
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update intel-sec-tools to commit of BootGuard support.
Remove --coreboot argument in src/security/intel/cbnt/Makefile.inc:
was removed as argument for cbnt
Change-Id: Iaf34bdb65a5f067d1d632e35d340b8fc49aaf318
Signed-off-by: Christopher Meis <christopher.meis@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55013
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Newest master includes these changes:
1. Introduce the FSP package for Elkhart Lake SKUs
2. Introduce the FSP package for Tiger Lake IoT SKUs
3. Update the FSP package to latest version for Apollo Lake,
Comet Lake and Tiger Lake (client SKUs)
You can get further 3rdparty/FSP commit history here:
https://github.com/intel/FSP/commits/master
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I96d147fec82d0fcd5c7748c277deb0672a975ceb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55228
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id e681c37:
change node locked version expectations
to commit id b38e3a63:
cros_ec: Use boot mode to check if EC can be trusted
Change-Id: Id6de185af85a61a3843b302fef6fa0d4d3c17aef
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55026
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the vboot submodule from commit 57c0c5b:
cgpt: Move all GPT on SPI-NOR infra behind a flag
to e681c37:
change node locked version expectations
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: Ifd130e3f66f1819f59f00703f0ad0c2278b544bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Updating from commit id 7ad39818b:
2020-10-12 09:16:21 +0000 - (Merge "mediatek: mt8192: add GIC600 support" into integration)
to commit id 96404aa27:
2021-05-13 18:27:27 +0200 - (Merge "build(hooks): update Commitizen to ^4.2.4" into integration)
This brings in 861 new commits.
Change-Id: I912545022e4320b86ab8a382144c02e315d0c835
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Now that Boot blobs have landed, need to uprev the qc_blobs.
Change-Id: I510de2d1e4334612c81f35a082dea92d445da0bb
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Some changes:
- bg-prov got renamed to cbnt-prov
- cbfs support was added which means that providing IBB.Base/Size
separatly is not required anymore. Also fspt.bin gets added as an
IBB to secure the root of trust.
Change-Id: I20379e9723fa18e0ebfb0622c050524d4e6d2717
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52971
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 9d4053df:
2020-11-20 01:51:08 +0000 - (Revert "Reland: Clean up implicit fall through.")
to commit id 57c0c5be:
2021-04-09 11:45:39 +0800 - (cgpt: Move all GPT on SPI-NOR infra behind a flag)
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Id50a892f12ff3c4147c422c98b640ac047143128
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52453
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
mb/google/guybrush: Update APCB - disable debug
mb/google/guybrush: Add APCB to get through memory training
soc/mediatek/mt8192: Add EMI Settings of 8GB Normal Mode
soc/mediatek/mt8192: Update MCUPM firmware
soc/mediatek/mt8192: Add version info for SSPM
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I445d753c712670fe80efcdf29459736df2b76666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Updating from commit id 3a9d7cd:
2021-03-03 15:37:08 -0700 - (picasso: Update Dali SMU firmware)
to commit id dded82f:
2021-03-23 15:36:36 -0600 - (picasso: Update Dali SMU firmware)
This brings in 2 new commits.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If71e52a2a3e50aeb8599798de7b49bc71ed26a04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This includes the bg-prov tool.
Change-Id: Iba8efe3bcb67694da76ef78abaa0562d47f7850b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Updating from commit id a2390f3c5:
2020-12-01 08:35:44 +0000 - (servo_v4/usb_pd_policy: Reject SNK->SRC power swap if CC_ALLOW_SRC not set)
to commit id 1e800ac83:
2021-03-01 22:59:54 +0000 - (docs: point md files in master to main/HEAD)
This brings in 188 new commits.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5c276d7839e0bdbf14ac56f16c231d75a6ea4c3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Updating from commit id 3b1a734:
2021-03-02 11:51:18 -0700 - (picasso: Update FSP to build 0x26)
to commit id 3a9d7cd:
2021-03-03 15:37:08 -0700 - (picasso: Update Dali SMU firmware)
This brings in 1 new commits.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iff3b4ff667f97d3804bc66477f8a95a60e23b1a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51459
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 4fdfa1c:
2021-03-05 13:10:22 -0600 - (mb/amd/majolica: Update to use proper APCBs built for Majolica)
to commit id fc2d4e2:
2021-03-12 10:31:48 -0700 - (mb/google/guybrush: Add initial APCB)
This brings in 1 new commit.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I3003fdb8ba0bcfbc33452999c35a9a21775ecc10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Some of the previous binaries were incorrect and should not be used
for Majolica because they are templates instead of APCBs specifically
built for the board. This APCB update also places the UMA region under
4G and size 32 MB which is essential for video output.
TEST=Boot with UEFI BIOS and verify we can get to OS. Also verify memory
region size, base and alignment.
Change-Id: Id797e2ad5bd67815c09752aedc19dad7dcf8ad12
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Avoid a Secure OS Abort. This prevents coreboot timing out on C2P
mailbox commands and allows HDT unlocking.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I358530a1ba959ee1896e26a47853c9918ee124b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This adds the apcb binary for Bilby.
Change-Id: I1487369bc72734e875c5a701f27ed2d6af41cd01
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Updating from commit id a1afae4:
2019-10-02 11:47:45 +0000 - (juniper: initial setup)
to commit id a2390f3:
2020-12-01 08:35:44 +0000 - (servo_v4/usb_pd_policy: Reject SNK->SRC power swap if CC_ALLOW_SRC not set)
This brings in 4022 new commits.
Change-Id: Ib13921aa78a60f88455223eff602296abc424ca8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48212
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update submodule pointer to include microcode for CML-H and others.
Change-Id: Ide211b0b163f824a3cfa6500a73aea1e2176c652
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47914
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This pulls in the following changes:
* Drop geode_lx
* cpu/amd/model_fxx: Drop unused microcode
* cpu/amd/model_10xx: Drop unused microcode
* soc/mediatek/mt8192: Add dram.elf for DRAM full calibration
* soc/mediatek/mt8192: Add dpm binary
* soc/mediatek/mt8192: Add 4266Mbps flag for dpm & dram blob
* soc/mediatek/mt8192: add SPM firmware
* soc/mediatek/mt8192: Support 26M clock off in SPM
* soc/mediatek/mt8192: Add SSPM firmware
* soc/mediatek/mt8192: Add MCUPM firmware
* soc/mediatek/mt8192: Update MCUPM firmware
* soc/mediatek/mt8192: Support discrete DRAM modules
* mb/amd/majolica: Add APCB configuration files
Change-Id: I5c18349307421707fac71f392b785f3e2bef3acb
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
We missed that Cannon Point, the PCH usually paired with Coffee, Whiskey
and Comet Lake, differs a bit from its predecessors. Hence, libgfxinit
now has a new Kconfig setting for the PCH.
Change-Id: I1c02c0d9abb7340aabe94185ee5e17ef4c2b0d36
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add blobs from the 1.0.0.1 release of CezannePI-FP6.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Iebfbe819ed429a7aed1882964061e1bc98f3bc39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add the newest SMU firmware and FSP blobs for the picasso project.
This supports Picasso, Dali, and Pollock devices.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I75e6f3d2a59ed8b2e42afba3a6978574373ec4e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Updating from commit id 9d4053d:
2020-11-20 01:51:08 +0000 - (Revert "Reland: Clean up implicit fall through.")
to commit id 48195e5:
2020-11-24 10:23:45 +0000 - (Makefile: Test for warning flags before using them)
This brings in 3 new commits.
Change-Id: I64f27f346df264cb6eeeb4e3203fcca7d35f7e83
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Updating from commit id 4c523ed1:
vboot2: Add support for modexp acceleration
to commit id 9d4053df:
Revert "Reland: Clean up implicit fall through."
This brings in 32 new commmits. Among the changes are restored support
for older GCC/clang versions that do not support
__attribute__((fallthrough)).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1110664bf71b4376bcdd9ba934a95031ba872c1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This now tracks a recently created upstream repository located at
https://github.com/amd/firmware_binaries
BUG=b:166107781
Change-Id: Ib193d646bb51cbf7b86f46828033e619c3f70e16
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46594
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The 3 commits commits from the blob repository this patch pulls in
remove executable flags from files in the repo that shouldn't have those
flags set:
* pi/amd/00660F01/FP4/AGESA.bin: Remove execute file mode bit
* Remove execute permission from all binaries
* Remove execute permission from plaintext files
Change-Id: I9c2b7c69f07e46bac466bfbfb277595c9fbc5a5a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Updating from commit id 4bb06cc1:
COIL: Change denylist to blocklist
to commit id 4c523ed1:
vboot2: Add support for modexp acceleration
This brings in 10 new commmits.
Change-Id: Iff6eb99c8ed3046b6fdb6c1e2892aab956f3b562
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The patch incorporates the STM build as a part of the coreboot
build. A separate patch lists and documents the options that
the developer can use. In most cases the default options will
suffice.
Change-Id: I8c6e0c85edd4e2b0658791553bd9947656e8c796
Signed-off-by: Eugene D Myers <cedarhouse@comcast.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Updating from commit id fefcaa65:
vboot: adjust VB2_SECDATA_KERNEL_FLAGS in non-recovery path
to commit id 4bb06cc1:
COIL: Change denylist to blocklist
This brings in 20 new commmits.
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I0efef2f0ab6ecb89c8132cca2bd4ab7f71e85ced
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45299
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id ace23683b:
2019-09-27 Merge changes from topic "ld/stm32-authentication" into
integration
to commit id a4c979ade:
2020-08-26 Merge changes I6bf1db15,I8631c34a,Id76ada14 into integration
This brings in 1825 new commits.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Id26301dae421eec61c10a2d18842053f3228c557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44885
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 3932b1c:
2020-08-19 02:09:04 +0000 - inclusive: change usage of
blacklist/whitelist
to commit id fefcaa6:
2020-08-24 04:32:03 +0000 - vboot: adjust VB2_SECDATA_KERNEL_FLAGS in
non-recovery path
This brings in 2 new commits.
Change-Id: Ia3ff764537b91f76ba6fa3ba2646638964800510
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This also includes https://chromium-review.googlesource.com/2318026
which fixes an issue with duplicate symbols.
Change-Id: Icf450616b3bcd8b7c01261c913cd172625dbd6ba
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Building depthcharge master currently fails as depthcharge commit 74ca8ae5
(depthcharge: Hide dev mode timeout description) changed the function signature
according to vboot commit 59fd331b (vboot/ui: pass timer_disabled to
vb2ex_display_ui()), which is not yet present in the vboot checkout:
$ make
[…]
CC drivers/ec/vboot_auxfw.depthcharge.o
src/drivers/ec/vboot_auxfw.c: In function 'display_firmware_sync_screen':
src/drivers/ec/vboot_auxfw.c:117:5: error: too many arguments to function 'vb2ex_display_ui'
vb2ex_display_ui(VB2_SCREEN_FIRMWARE_SYNC,
^~~~~~~~~~~~~~~~
In file included from /dev/shm/coreboot-1/3rdparty/vboot/firmware/include/vb2_api.h:18,
from src/drivers/ec/vboot_auxfw.c:17:
/dev/shm/coreboot-1/3rdparty/vboot/firmware/include/../2lib/include/2api.h:1262:13: note: declared here
vb2_error_t vb2ex_display_ui(enum vb2_screen screen,
^~~~~~~~~~~~~~~~
So update the submodule pointer from commit 68de90c7 (Allow building for
non-CrOS environments) to commit ed23c084 (Reset EC when transitioning to dev
mode).
This brings in 7 new commits.
Change-Id: Icd5408fb824fc5da470774b7f493b916dff17832
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Joel Kitching <kitching@google.com>
This brings in 4 new commits:
* c0db994 common/Makefile.inc: Factor out generation TLAs
* 3f86b0b Move `PSR_Off` out of `Power_And_Clocks_Haswell`
* 450c24c haswell: Make VGA on FDI work
* 3318bf2 Drop generation suffix from `Power_And_Clocks`
Change-Id: I023b0c2bb403b3a9c9fe575a78cd2cf2f20b112a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Updating from commit id c531000f:
2020-05-18 20:55:55 +0000 - (vboot: Add recovery reason code for CSE Lite SKU errors)
to commit id 68de90c7:
2020-07-02 11:31:05 +0000 - (Allow building for non-CrOS environments)
This brings in 59 new commits.
Change-Id: I7f3c30511ff4acc60e3581bdab89d685dc7beaa5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43008
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a separate blobs repository for Qualcomm blobs,
analogous to the existing AMD blobs. Qualcomm's binary licenses allow
files to be redistributed and used by anyone, but they explicitly
require the user to agree to the license terms when just *downloading*
the binary (even if they're not using them to build any firmware). Some
community members do not like to have to agree to licenses for files
they're not actually using, so we are keeping these files separate from
the main blobs repository and adding an extra Kconfig to make sure the
user is aware of and must explicitly agree to this before downloading
these files.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I247746c1b633343064c9f32ef1556000475d6c4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This pulls in a newer version of the PSP-related blobs.
Change-Id: I6ff39260e9697512f78eb68435bd17ea83af35d5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Cmocka unit testing framework is used for writing and building coreboot
unit tests. This repo will be checked-in only when building some test
targets.
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I3cdfd32f5bba795d5834ebeae1afff0f7006a0d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The code is based on autoport and that for X230. Major differences are:
- Only one DDR3 slot
- HM77 PCH
- M.2 socket instead of mini pci-e
- no docking
- no tpm
Tested:
- CPU i5-3337U
- Slotted DIMM 8GiB
- Camera
- pci-e and usb2 on M.2 slot with A key for wlan
- sata and usb2 (no superspeed components) on M.2 slot with B key for wwan
- On board SDHCI connected to pci-e
- USB3 ports
- libgfxinit-based graphic init
- NVRAM options for North and South bridges
- Sound
- Thinkpad EC
- S3
- Linux 4.9 within Debian GNU/Linux stable, loaded from
Seabios.
Untested:
- Touch screen, which is said to work under ubuntu but not debian.
Change-Id: Ie537645d5ffaee799e79af2f821f80c3ebd2dfec
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Updating from commit id 55154620:
vboot: Add screens for recovery using disk
to commit id 3aab3014:
vboot: Convert reboot-related errors to vboot2-style
This brings in 3 new commits.
Change-Id: I75be535e0b0f8080366b98e5ae2007452ad51738
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40845
Reviewed-by: Joel Kitching <kitching@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update submodule pointer to 20191115 release to include the microcode
update for CML-U62, and others.
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I4765a70be0b1182acd340a3c31a5d71fd0ab500f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Updating from commit id 46ff62c3:
vboot: stop reading from ACPI for wpsw_boot
to commit id 55154620:
vboot: Add screens for recovery using disk
This brings in 37 new commits.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: Ie184cbe6cc18cea540966d5801472ae821ea3e86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40503
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the pointer for vboot_reference so it can be used to compile
depthcharge payload on the master branch.
Change-Id: I5fc6e05896d7221a1e48ca86c6b15081488302b5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Changes allow to use the integrated panel logic (power sequen-
cing and backlight control) for more connectors. The Kconfigs
GFX_GMA_PANEL_1_PORT and GFX_GMA_PANEL_2_PORT can now be set
to any port, e.g.
config GFX_GMA_PANEL_1_PORT
default "DP3"
Now that the panel logic is not tied to the `Internal` port
choice anymore, we can properly split it into `LVDS` and `eDP`.
This also adds Comet Lake PCI IDs which should still work the
same as Kaby and Coffee Lake.
Change-Id: I78b1b458ca00714dcbe7753a7beb4fb05d69986b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38921
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 8b9732f5:
2020-01-28 02:32:08 +0000 - (2lib: Fix struct vb2_hash the way it was
meant to be)
to commit id 5059062d:
2020-03-05 02:40:39 (EFS: Implement EFS2 and NO_BOOT mode)
This brings in 19 new commits.
Change-Id: Ic33500921e2c1a6109c24ad36713b41ab6e43de9
Signed-off-by: dnojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39324
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 0e97e25e:
2020-01-28 02:32:08 +0000 - (2lib: Fix struct vb2_hash the way it was meant to be)
to commit id 8b9732f5:
2020-02-18 05:55:01 +0000 - (vboot: do not call vb2_commit_data at end of VBSLK)
This brings in 36 new commits.
Change-Id: Icb0ab2c82c3264185171a32357944949afd2edce
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I5f053c1270bab71aeab3bb785c60417419736b44
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Updating from commit id 6ef33b99:
2019-11-22 Hung-Te Lin futility: updater: refactor: unify
getting temp files for firmware images
to commit id 0e97e25e:
2020-01-23 Julius Werner 2lib: Fix struct vb2_hash the way it was
meant to be
Change-Id: I539aba2f283804f67ff3ff4f98324b3d10b2bb54
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Updating from commit id 2843aa62:
2019-12-12 Julius Werner 2lib: Move firmware body size reporting to
separate function
to commit id f5367d59:
2020-01-20 Joel Kitching vboot: translate recovery reason info from
vboot 2->1
This brings in 27 new commits.
Change-Id: I7d33337881fa2d36d6e562b0a390b56227cfad55
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
We had to role the `fsp` submodule back for a minute due to a regression
with the Coffee Lake binary. Intel silently mixed FSP 2.1 features into
the Coffee Lake FSP which is supposed to be FSP 2.0. With the stack and
heap usage partitioned for FSP using coreboot's stack (config FSP_USES_
CB_STACK), it works again.
To make this even messier: We already selected this Kconfig option for
Whiskey Lake, which is supposed to use the very same FSP binary. So with
either submodule pointer, something was always broken :-/
Change-Id: Id2aa17aaa2c843dcc7e0fb28779d1e5948da83c9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mimoja <coreboot@mimoja.de>
CB:36845 simplified how coreboot finds the RW CBFS after vboot has and
eliminated a layer of caching. Unfortunately, we missed the fact that
the former cached value didn't exactly match the FMAP section... it was
in fact truncated to the data actually used by vboot. That patch
unintentionally broke this truncation which leads to performance
regressions on certain CBFS accesses.
This patch makes use of a new API function added to vboot (CL:1965920)
which we can use to retrieve the real firmware body length as before.
(Also stop making all the vb2_context pointers const. vboot generally
never marks context pointers as const in its API functions, even when
the function doesn't modify the context. Therefore constifying it inside
coreboot just makes things weird because it prevents you from calling
random API functions for no reason. If we really want const context
pointers, that's a refactoring that would have to start inside vboot
first.)
This patch brings in upstream vboot commit 4b0408d2:
2019-12-12 Julius Werner 2lib: Move firmware body size reporting to
separate function
Change-Id: I167cd40cb435dbae7f09d6069c9f1ffc1d99fe13
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Updating from commit id 695c56dc:
2019-12-04 Julius Werner Makefile: Make loop unrolling fully
controllable by the caller
to commit id b10e5e32:
2019-12-09 Yu-Ping Wu vboot: Make 2nvstorage.h private to
vboot_reference
This brings in 19 new commits.
Change-Id: I9cdccd25422aee26620d48d31f83bcf32a7b4809
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37717
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With CB:37564 (3rdparts/fsp: Update fsp submodule) a regression
has been introduced to CFL platforms, such that the FSP-M fails/is
broken. This commit sets the commit to checkout in the submodule
FSP back to a working version.
Change-Id: I8eac551211559962fc60e7edd46ff118d7bde830
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37669
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The name for the CoffeeLake FSP.fd was changed to Fsp.fd.
Therefore the CoffeLake / WhiskeyLake default path was
changed.
Change-Id: I0f51e378fcaacb25392d8940a342fc968c730157
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37564
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Going forwards, vb2ex_commit_data will be used to flush both
nvdata and secdata.
The patch that is circularly dependent on this lies between a patch that
makes vboot no longer build and the patch that fixes that, so we have to
pull the whole thing in at once to sort out the mess.
Updating from commit id 1c4dbaa0:
2019-11-18 Julius Werner Makefile: Fix typo for MOCK_TPM
to commit id 695c56dc:
2019-12-04 Julius Werner Makefile: Make loop unrolling fully
controllable by the caller
BUG=b:124141368, chromium:1006689
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Ia2612da0df101cd3c46151dbce728633a39fada1
Signed-off-by: Joel Kitching <kitching@google.com>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Updating from commit id e561c63:
2019-10-02 17:03:58 +0530 - (lib: Fix coldboot race condition observed on emulators/simulators)
to commit id 215421c:
2019-11-11 16:40:34 -0800 - (lib: Remove date and time from init message)
This brings in 13 new commits and allows reproducible builds with
opensbi.
Change-Id: I0fb9e0921b017822defa8b56df5a0f3e014d7f33
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Arthur Heymans