Commit Graph

37586 Commits

Author SHA1 Message Date
Daisuke Nojiri ab2ad3f2f9 Fleex: Resume from suspend on critical battery
This patch makes Fleex EC wake up AP from s0ix when the state of
charge drops to 5%.

Demonstrated as follows:

1. Boot Fleex.
2. Run powerd_dbus_suspend.
3. On EC, run battfake 5.
4. System resumes.

BUG=b:163721887
BRANCH=Octopus
TEST=Verified on Fleex:

Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I4a998ad0aef5a7cfc6fd18995bde5571e6127e77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-10-05 20:44:28 +00:00
Nick Vaccaro dfcd739fc7 lib/spd_bin: add LPDDR4X case to spd_get_name()
Add case for LPDDR4x to spd_get_name().

BUG=b:169800932, b:168724473
TEST=none

Change-Id: I6bae373468b8ad5ae0a6b8dd6bbe14143afb85af
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45886
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 18:03:46 +00:00
Nick Vaccaro be34b500a6 mb/google/hatch,dedede,volteer: enable CHROMEOS_DRAM_PART_NUMBER_IN_CBI
Enable CHROMEOS_DRAM_PART_NUMBER_IN_CBI on hatch, dedede, and volteer
to use the common version of mainboard_get_dram_part_num().

Remove duplicate instances of mainboard_get_dram_part_num().

BUG=b:169789558, b:168724473
TEST="emerge-volteer coreboot && emerge-hatch coreboot &&
emerge-dedede coreboot" and verify it builds.

Change-Id: I4e29d3e7ef0f3370eab9a6996a5c4a21a636b40e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45883
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 18:03:38 +00:00
Nick Vaccaro 53b99a84a5 soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num()
Consolidate all weak declarations of mainboard_get_dram_part_num() to
instead use the common definition in lib/spd_bin.c.

BUG=b:168724473
TEST="emerge-volteer coreboot && emerge-nocturne coreboot &&
emerge-dedede coreboot" and verify build succeeds without error.

Change-Id: I322899c080ab7ebcf1cdcad3ce3dfa1d022864d1
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-05 18:03:22 +00:00
Nick Vaccaro edecf46187 vendorcode/google: add CHROMEOS_DRAM_PART_NUMBER_IN_CBI Kconfig option
Add CHROMEOS_DRAM_PART_NUMBER_IN_CBI Kconfig option to declare whether
the SPD Module Part Number (memory part name) is stored in the CBI.

Move mainboard_get_dram_part_num() into src/vendor/google/chromeos
to allow mainboards to use it without having to duplicate that code
by enabling the CHROMEOS_DRAM_PART_NUMBER_IN_CBI config option.

BUG=b:169789558, b:168724473
TEST="emerge-volteer coreboot && emerge-hatch coreboot &&
emerge-dedede coreboot && emerge-nocturne coreboot" and verify it
builds.

Change-Id: I0d393efd0fc731daa70d3990e5b69865be99b78b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-05 18:02:51 +00:00
Nick Vaccaro 3b24bb6fc8 soc: move mainboard_get_dram_part_num prototype to memory_info.h
BUG=b:169774661, b:168724473
TEST="emerge-volteer coreboot && emerge-nocturne coreboot &&
emerge-dedede coreboot" and verify they build successfully.

Change-Id: I8b228475621ca1035fe13f8311355fc3b926e897
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-05 18:02:37 +00:00
Nick Vaccaro 0ed02d00cb mb, soc: change mainboard_get_dram_part_num() prototype
Change mainboard_get_dram_part_num() to return a constant character
pointer to a null-terminated C string and to take no input
parameters.  This also addresses the issue that different SOCs and
motherboards were using different definitions for
mainboard_get_dram_part_num by consolidating to a single definition.

BUG=b:169774661, b:168724473
TEST="emerge-volteer coreboot && emerge-dedede coreboot && emerge-hatch
coreboot" and verify build completes successfully.

Change-Id: Ie7664eab65a2b9e25b7853bf68baf2525b040487
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45873
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 18:02:22 +00:00
Nick Vaccaro aef9ac97c7 soc/intel/elkhartlake: add __weak to mainboard_get_dram_part_num()
Add missing __weak declaration to Elkhart Lake's definition of
mainboard_get_dram_part_num().

BUG=b:169774482, b:168724473
TEST=none

Change-Id: I883d662315a9ab91eb6183ebcdfd7e7cc8064c64
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45871
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 18:02:05 +00:00
Angel Pons 8975e7b025 lib/ubsan.c: Remove GCC 5.x workaround
The coreboot toolchain has been using a newer GCC version for a while
already. This code is build-tested from commit 13cd145e02 onwards.

Change-Id: Ic324b503878c73e4560d4d8f2e0d38ecb595b8fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45822
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 16:18:24 +00:00
Subrata Banik cf0ac156c4 soc/intel/tigerlake/acpi: Convert 'pch_hda.asl' into ASL 2.0 syntax
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I8deaeb29abed097d536f1c3c44606a549c6af4e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05 15:18:05 +00:00
Subrata Banik 37a42da465 soc/intel/common/block/acpi: Factor out common ish.asl
This patch moves ish.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.

TEST=Able to build and boot TGL, CML platform.
1) Dump and disassemble DSDT, verify ISHB device present inside
common ish.asl is still there with correct _ADR value.
2) Verify no ACPI error seen while running 'dmesg` from console.

CML platform:

Device (ISHB)
{
  Name (_ADR, 0x00130000)  // _ADR: Address
  Name (_DDN, "Integrated Sensor Hub Controller")  //_DDN: DOS Device Name
}

TGL/JSL platform:

Device (ISHB)
{
  Name (_ADR, 0x00120000)  // _ADR: Address
  Name (_DDN, "Integrated Sensor Hub Controller")  //_DDN: DOS Device Name
}

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I33c1649d7a632c7b147e1bf307cfb5c1dfd84c0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05 15:17:53 +00:00
Angel Pons b70c66b00d nb/intel/ironlake: Drop unnecessary `smm_region_start` function
Change-Id: I4c4b40b2b4f54b7756b8485dad80a1b4786270f7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-05 09:19:28 +00:00
Angel Pons 11ca2ae167 nb/intel/ironlake/memmap.c: Clean up includes
Drop unused includes and add missing <types.h>.

Change-Id: Ifefe81d4727d67ea702c5e24527f80a0614aa396
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-05 09:19:08 +00:00
Zheng Bao 9c8ce3e423 amdfwtool: Remove the assumption of ROM_SIZE
Every platform passes (and need to) the --flashsize to the command
parameter, so we remove the macro definition about a built-time
romsize defined in Makefile.

Change-Id: I894e833ed23a7da38b36986b624e7dcdf1f4090c
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-05 08:37:46 +00:00
Zheng Bao 473969163d amdfwtool: Use a variable to get the return value of write
New Jenkins complaint about the original code that return
value gets to nowhere. Fix that with a new variable.

Change-Id: I8099b856ccb751dc380d0e95f5fe319cc3e2c6cc
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45812
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 08:37:37 +00:00
Zheng Bao 7698a55202 amdfwtool: Clean up the Makefile of amdfwtool
Add Makefile.inc to compliant with other tools.
Makefile is kept for building amdfwtool by typing make
in the folder.

Change-Id: I3688d93de4459f5f838955892086b4b9bf30a9b8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-05 08:37:28 +00:00
Mario Scheithauer 8725c0af09 mb/siemens/mc_apl6: Enable eMMC
Enable eMMC with HS200 mode for mc_apl6 mainboard.

TEST: Linux booted and checked with 'lspci'.

Change-Id: Ib760a1a26a92047e8916979ffb5001bcff0a6e45
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45898
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 05:11:03 +00:00
Subrata Banik 6577ec4de4 soc/intel/common/block/acpi: Factor out common platform.asl
This patch moves platform.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.

TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify _PIC method present inside
common platform.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05 04:01:40 +00:00
Subrata Banik ae63c1e013 soc/intel/{cnl,icl,skl}: Convert 'platform.asl' to ASL 2.0 syntax
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I3fcd971402e540d91a7392ca58175eb3ecc24cec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45981
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 04:00:46 +00:00
Subrata Banik 319a91f894 soc/intel/skylake: Align platform.asl with CNL
Refer _WAK and _PTS ASL functions from common platform.asl

TEST=Dump and disassemble DSDT, verify all methods present inside
common platform.asl like _WAK, _PTS etc. are still there.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I625e42b3c49abbb3595a4307da5fc24850a98fbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45980
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 04:00:34 +00:00
Subrata Banik 3b3bbd4fba soc/intel/common/block/acpi: Factor out common smbus.asl
This patch moves smbus.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.

TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify SBUS device present inside
common smbus.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ib1ae48f7ece3e521501d92c40cd551287ea2f1ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05 04:00:19 +00:00
Subrata Banik 73968fd14b mb/{google,intel}/{volteer,tglrvp}: Refer to common IPU ASL
Delete SoC local copy of ipu.asl and refer from common block ipu.asl

TEST=Dump and disassemble DSDT on tglrvp, verify IPU0 device
present there.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I6a0f8a919092f7bbcd64d4791746d30fdee33894
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05 04:00:05 +00:00
Subrata Banik 500c245f3c soc/intel/jasperlake: Delete unused ipu.asl
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I8c7363d442ed40c36fc01dc3608bab864865f29d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45977
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 03:59:43 +00:00
Subrata Banik 415b598742 soc/intel/common/block: Rename IPU ACPI device
IMGU->IPU0 to align with other SoC IPU entires.

TEST=Dump and disassemble DSDT on poppy, verify IPU0 device
present there.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I803c01f9156a56dbd903b6ba7897cc0f96b0a26a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05 03:59:34 +00:00
Subrata Banik d2becae223 soc/intel/common/block/acpi: Factor out common pch_glan.asl
This patch moves pch_glan.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.

TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify GLAN device present inside
common pch_glan.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I479678c864eba39e5ab04f658600e8cba48198ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05 03:59:08 +00:00
Rob Barnes 34cf7ccebc Revert "util/spd_tools: output binaries instead of hexdumps"
This reverts commit f23794cf04.

Reason for revert: This change breaks compatibility if the changes
in CB:44775 are not also included. CB:44775 is still under discussion,
so revert this change to make spd_tools usable again.

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I5840a1b895dcbc8b91c76d8b60df2f95b93a4370
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44999
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03 16:29:00 +00:00
Subrata Banik 2871e0e78c soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage
List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Add CPU, PCH and SA EDS document number and chapter number
4. Fill required FSP-S UPD to call FSP-S API

Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03 12:15:22 +00:00
Marc Jones 95bab4077e soc/intel/xeon_sp/acpi: Rename pci_irq.asl
Rename pci_irq.asl to pci_irqs.asl to match other intel soc file
names. This makes comparing differences much easier.

Change-Id: I622dfef675c3df2dff7a3024ccbe14c356a5cd86
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45834
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03 09:30:13 +00:00
Marc Jones 9f0c000227 soc/intel/xeon_sp: Clean up pci_devs.h
Prepare for merging cpx and skx pci_devs.h.

Remove duplicate defines. Move defines so they match each other.

Checked TiogaPass and DeltaLake BUILD_TIMELESS.

Change-Id: I146dd9e3f7eba053977d48dcf34d927dea310059
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45833
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03 09:29:53 +00:00
Subrata Banik 0359d9dde3 soc/intel: Make use of PMC low power program from common block
List of changes:
1. Select PMC_LOW_POWER_MODE_PROGRAM from applicable SoC directory
2. Remove redundant PMC programming from SoC and refer to common
code block
3. Remove unused 'reg8' and 'reg32' variable as applicable from SoC
function.

Change-Id: I18894c49cfc6e88675b5fb71bca0412e5639fb4b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45796
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03 06:58:07 +00:00
Subrata Banik 3e959d8e2a soc/intel/common/block/pmc: Add PMC API for low power programming
List of changes:
1. Create Kconfig to select pmc low power program by SoC
2. Add API to make ACPI timer disable
3. Add API to ignore XTAL shutdown for SLP_S0# assertion

Change-Id: I017ddc772f02ccba889d316319ab3d5626b80ba5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45794
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03 06:57:51 +00:00
Subrata Banik 8971ccd576 soc/intel: Move pch_misc_init() to common code
List of changes:
1. Move pch_misc_init() into common block code.
2. Remove redundant LPC functions from SoC directory and
refer from block/lpc directory.
3. Create macros for IO port 0x61 and 0x70 as applicable.

TEST=Able to build and boot hatch and tglrvp platform without seeing
any functional impact.

Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03 04:19:00 +00:00
Subrata Banik 78463a7d26 soc/intel: Move soc_pch_pirq_init() to common code
List of changes:
1. Rename soc_pch_pirq_init() as pch_pirq_init() and
move into common block code.
2. Remove redundant LPC functions from SoC directory and
refer from block/lpc directory.

TEST=Able to build and boot hatch and tglrvp platform without seeing
any functional impact.

Change-Id: I856b5ca024e58fd14b4d1721f23d9516a283ebf8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03 04:18:46 +00:00
Subrata Banik 1366e4438d soc/intel: Move pch_enable_ioapic() to common code
List of changes:
1. Move pch_enable_ioapic() into common block code.
2. Remove redundant LPC functions from SoC directory and
refer from block/lpc directory.

TEST=Able to build and boot hatch and tglrvp platform without seeing
any functional impact.

Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03 04:18:32 +00:00
Marc Jones 18b1984f86 soc/intel/xeon_sp/include: De-duplicate .h files
Move duplicate .h files to top level xeon_sp/include/soc from
silicon specific cpx/include/soc and skx/include/soc.

Change-Id: I11d8a95a4b2f9451615b236798b3bd030c724858
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45221
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03 03:36:24 +00:00
Marc Jones e2f6c7fb99 soc/intel/xeon_sp/skx: Prepare acpi.* for merging
Clean up acpi.h in preparation for merging with cpx/ acpi.* files

Change-Id: I2a0dc964eeb7f8da53676eb94c4385ff8668f6af
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45218
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03 03:35:59 +00:00
Marc Jones b0e8c7c437 soc/intel/xeon_sp: Use common ASL code for xeon_sp
Move and use the common xeon_sp/cpx/acpi asl for skx/.
There were only minor whitespace differences between the directories.

Update the mainboards to build the moved files.

TiogaPass coreboot.rom checked with BUILD_TIMELESS.

Change-Id: I5058a3fe8d96075a266fb92f10707bb94308c85b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45217
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03 03:34:52 +00:00
Marc Jones 07e8cd5348 soc/intel/xeon_sp/skx: Fix uncore.asl \_SB namespace issue
The skx uncore ACPI scope was missing the \ on \_SB causing
the uncore IRQs to not be in the namespace. This addresses
ACPI uncore IRQ routing issues. This was found preparing
skx acpi to match cpx acpi for merging in the future.

Check scope in dsdt.asl in tiogapass build.

Change-Id: I799042babbe60287e5e4ec60b21c08d57ccda04b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45269
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03 03:34:06 +00:00
Marc Jones c3d92f0c73 soc/intel/xeon_sp/skx: Update ITSS OperationRegion to ACPI2.0 notation
Prepare for merge with cpx.
Use the C style operators instead of the ACPI1.x polish notation.
This is much easier to read and matches the cpx code.

This generates the same ASL code.
Checked with BUILD_TIMELESS on TiogaPass.

Change-Id: Id44138894d2ffed4c93afe5d4bbb4d59b538b577
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45270
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03 03:33:25 +00:00
Marc Jones b20c1023d6 soc/intel/xeon_sp/skx: Update uncore IRQ routing ACPI tables
Update the skx uncore ACPI routing tables to match cpx. This
adds the IRQ routing for B-D for legacy and IOAPIC modes.

Change-Id: Iac0ffdb467a78b9befe7402c074835ea602d43c8
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03 03:32:39 +00:00
Shelley Chen b4a4f59dd2 mrc_cache: Update mrc_cache data in romstage
Previously, we were writing to cbmem after memory training and then
writing the training data from cbmem to mrc_cache in ramstage.  We
were doing this because we were unable to read/write to SPI
simultaneously on older x86 chips.  Now that newer chips allow for
simultaneously reads and writes, we can move the mrc_cache update into
romstage.  This is beneficial if there is a reboot for some reason
after memory training but before the previous mrc_cache_stash_data
call originally in ramstage.  If this happens, we would lose all the
mrc_cache training data in the next boot even though we've already
performed the memory training.

Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate
older x86 platforms that don't do mmapping but still want to use the
cbmem to store the mrc_cache data in order to write the mrc_cache data
back at a later time.  We are maintaining the use of cbmem for these
older platforms because we have no way of validating the earlier write
back to mrc_cache at this time.

BUG=b:150502246
BRANCH=None
TEST=reboot from ec console.  Make sure memory training happens.
     reboot from ec console.  Make sure that we don't do training again.

Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I3430bda45484cb8c2b01ab9614508039dfaac9a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44196
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-02 23:11:39 +00:00
Shelley Chen 156bc6f47a soc/intel/braswell: Increase dcache size
Increase the DRAM cache size for Braswell to address the
compilation error

    Cache as RAM area too full

when moving the mrc_cache writeback to romstage.  We need to increase
this first before landing the CL moving mrc_cache writeback to
romstage.

BUG=b:150502246
BRANCH=None
TEST=Able to successfully compile braswell boards

Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45827
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-02 23:11:16 +00:00
Shelley Chen 6c2568f4f5 drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate
older x86 platforms that don't allow writing to SPI flash when early
stages are running XIP from flash.  If
BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected,
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y.  This allows for current platforms
that write to flash in the earlier stages, assuming that they have
that capability.

BUG=b:150502246
BRANCH=None

TEST=diff the coreboot.rom files resulting from running
     ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless
     with and without this change to make sure that there was no
     difference.  Also did this for GOOGLE_CANDY board, which is
     baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
     enabled).

Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-02 23:11:04 +00:00
Felix Singer ba9f82ed73 mb/clevo/l140cu: Add variant specific romstage.c to build
While restructuring the mainboard directory, it was forgotten to add the
variant specific romstage.c to the build. Therefore, add romstage.c to
the Makefile fixing the raminit.

Change-Id: I7afbf1574803128f7d62592eed2398c945334757
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45928
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-02 19:22:28 +00:00
Zheng Bao 6d402acbc0 amdfwtool: Fix the gcc warning about sign comparison
New (maybe) compile tool complains the warning below.
warning: comparison between signed and unsigned
integer expressions [-Wsign-compare]
Fix all of them.

Change-Id: I59624326233284e6c3595df49625563254949c45
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-02 16:01:45 +00:00
Jonathan Zhang ce0e2a0140 drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region
APEI (ACPI Platform Error Interface) defines BERT (Boot Error Record
Table) memory region:
* Bootloader (firmware) generates UEFI CPER (Common Platform Error
Record) records, and populates BERT region.
* OS parses ACPI BERT table, finds the BERT region address, inteprets
the data and processes it accordingly.

When CONFIG_ACPI_BERT is defined, update FSP UPD BootLoaderTolumSize,
so FSP allocates memory region for it. The APEI BERT region is placed
on top of CBMEM, for the size of CONFIG_ACPI_BERT_SIZE.

Apart from APEI BERT region, we also have plan to add APEI HEST region
which holds OS runtime hardware error record, based on firmware
first hardware error handling model. HEST region will be reserved
same way as BERT region.

Note that CBMEM region can not be used for such purpose, the OS
(bert/hest) drivers are not able to access data held in CBMEM region,
as CBMEM is set as type 16 (configuration table).

An option considered was to reserve the BERT region under CBMEM.
However, we do not know the size of CBMEM till acpi tables are set up.
On the other hand, BERT region needs to be filled up before ACPI BERT
table is finalized.

Change-Id: Ie72240e4c5fa01fcf937d33678c40f9ca826487a
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-02 11:43:23 +00:00
Subrata Banik a5f4781d81 util/ifdtool: Include ADL dynamic check as per Gen12 SPI flash guide
BUG=b:153888802
TEST=Able to list correct PCH revision, SPI/eSPI frequency as per
ADL SPI flash guide.

Without this CL :
PCH Revision: 500 series Tiger Point

With this CL :
PCH Revision: 500 series Tiger Point/ 600 series Alder Point

Change-Id: I0faf0f0fdb625ff82eb0033b5b77e6470971bc23
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-02 04:01:08 +00:00
Jason Le 2b3416134f mb/intel/tglrvp/variants/tglrvp_up4 - Enable onboard HDMI and type-C displays for TGL-Y RVP
- Enable DDC pins for DDI-B
- Enable HPD pins for DDI-1/DDI-2
- Update MPHY/USB2 Mapping to match with the TGL-Y RVP schematic

BUG: System not able to detect displays attached to onboard micro-HDMI or Type-C connectors
TEST: hot-plug/unplug HDMI displays with onboard micro-HDMI connector and USB Type-C connectors to make sure the displays get detected and enabled

Change-Id: I08a1b16a8fa45cf0f366661395b9f2aa25c44935
Signed-off-by: Jason Le <jason.v.le@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-01 22:27:48 +00:00
Julius Werner 411e7607d6 drivers: sn65dsi86: Retry link training up to 10 times
The kernel guys have found that automatic link training from this bridge
can occasionally fail and needs to be retried. They have added up to 10
retries just to be sure, so let's do the same in coreboot.

BUG=b:169535092

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I713b6851bd51d3527ed4c6e6407dee6b42d09955
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45882
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 21:48:55 +00:00
Kevin Chiu 768f59a32f mb/google/zork: Configure EMMC_RESET_L to drive high
Configure EMMC_RESET_L (GPIO68) to drive high by default. As per JEDEC
specification for eMMC, RST_n_FUNCTION defaults to temporarily disable
reset using RST_n signal (which is connected to EMMC_RESET_L on
zork). Chrome OS platforms do not configure RST_n_FUNCTION thus making
the reset signal unused. The spec also says that there are no internal
pulls on the card and hence the RST_n signal should be driven
appropriately to prevent the input circuits from flowing unnecessary
leakage current.

Thus, even though the line remains unused, since it is connected in
hardware, this change drives EMMC_RESET_L to high.

BUG=b:169222156
BRANCH=zork
TEST=emerge-zork coreboot
     eMMC DUT reboot/suspend x100 iterations pass

Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-10-01 20:15:35 +00:00