Commit Graph

39263 Commits

Author SHA1 Message Date
Seunghwan Kim 9c5a3cbc0d mb/google/dedede/var/sasuke: Enable ELAN touchpad
This change adds ELAN touchpad into devicetree for sasuke.

BUG=None
TEST=Built and verified touchpad function

Change-Id: If9c25f23ee1c0e88382fff036f77a6753775b81e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-08 08:29:44 +00:00
Seunghwan Kim c6466aa893 mb/google/dedede/var/sasuke: Enable audio feature
This change adds DA7219 audio codec and MAX98360A amplifier for sasuke.

BUG=None
TEST= Built and heared speaker sound on OS

Change-Id: Ib48eb74fbfe171d46d0d23859057ba169b56bde2
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-08 08:29:31 +00:00
Seunghwan Kim 07339a5c21 mb/google/dedede/var/sasuke: Configure GPIO NC pads
Configure GPIO NC pads for sasuke.

BUG=b:172104731
TEST="FW_NAME=sasuke emerge-dedede coreboot"

Change-Id: I3bf8f97708536010da82402ea3d49e387e732d61
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-08 08:29:22 +00:00
Felix Singer 9486b1dba6 mb/asrock/h110m: Drop DEVICETREE from Kconfig
Drop DEVICETREE from Kconfig since it matches the default value.

Built with BUILD_TIMELESS=1, coreboot.rom remains the same.

Change-Id: Idbcd49cca6494ae2da0f364c24638d7ca11911da
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-01-08 08:28:36 +00:00
Felix Singer c3c8bed057 mb/clevo/cml-u: Drop VGA_BIOS_FILE from Kconfig
It doesn't make sense to configure that filename in Kconfig, since the
filename can be changed by the user. So remove it.

Change-Id: I3eed05637da29096bc1d134505d7335db5db1439
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49138
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:28:16 +00:00
Jakub Czapiga dd85c82962 tests: Add lib/fmap-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I885ea05d509d3b1330de7a18531f310d290c6965
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-08 08:26:26 +00:00
Marco Chen 525cc4626a ec/google/chromeec: add SSFC CBI support
An API is added to get SSFC value from cros EC.

BUG=b:174118027
BRANCH=octopus
TEST=check SSFC value from EC is correct compared to value in CBI

Change-Id: Ifd521514bbc2e90c789f3760b72e8326e614e2b1
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2021-01-08 08:25:42 +00:00
Furquan Shaikh d3b7e2f94a soc/intel/common/uart: Restrict scope of uart_common_init to uart.c
uart_common_init is not used outside of
soc/intel/common/block/uart.c. This change restricts the scope to this
file and drops the declaration from uart.h

Change-Id: I499a53506f9b2e91ecc7334bf9b023d342e802fc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49211
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:24:38 +00:00
Furquan Shaikh fb29ca0c55 soc/intel/common: Pass in pci_devfn_t into lpss_set_power_state
This change updates the parameter passed into `lpss_set_power_state()`
from struct device * to pci_devfn_t. This allows the users in the
early stages to use pci_devfn_t instead of having to walk the device
tree to get a pointer to the relevant device structure. It is
important for optimizing out unnecessary components of the device tree
from the early stages.

Change-Id: Ic9e32794da65348fe2a0a2791db47ab83b64cb0f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49210
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:24:20 +00:00
Furquan Shaikh e4f7e04050 soc/intel: Drop `dev` parameter from soc_get_gen_io_dec_range()
This change drops the parameter `struct device *dev` from the function
`soc_get_gen_io_dec_range()`. This function uses the parameter dev to
get a pointer to config structure for extracting the decode ranges
configured by mainboard in device tree. However, there is no separate
chip driver for the LPC device which means that the SoC code can use
`config_of_soc()` to get to SoC chip config instead of using the LPC
device.

This change is being done in preparation to clean up the device
tree/chip config access in early stages that allows for optimizing
the inclusion of device tree elements in the early stages.

Change-Id: I3ea53ddc771f592dd0ea5e5e809be2d2eff7f16d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-08 08:23:59 +00:00
Furquan Shaikh 2136c5af5f cpu/x86/smm: Use append instead of assign for smm-c-deps
This change uses append operation (+=) instead of assignment (:=) for
smm-c-deps to ensure that any earlier assignment is not
overwritten.

Change-Id: Ic1d62b414cfe3f61ee2b80b026b7338faa186904
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-08 08:23:20 +00:00
John Zhao 4ead6b3367 soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports
USB3 is in CPU and USB2 in PCH on Tigerlake. Cross die messaging is
implemented between CPU and PCH through the IOSF SB bridge. a PCH xHCI
USB2 port reset event issued by the xHCI driver shall trigger a message
upstream to CPU to wake it from the low power state which allows a USB3
device that downgraded to USB2 to upgrade back to USB3.

BUG=b:176575892
TEST=Built and booted to kernel on Voxel board.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I672f30a117980bc10bd71e9b77c5fa76286b9f5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49052
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:22:47 +00:00
Felix Held 81a4c344e7 util/testing: remove genprof target
commit 8c99c27df1 removed util/genprof,
so it needs to be dropped here as well to avoid spurious breakages of
the build.

Change-Id: I420b5c43e2d97373a8e665f457463a06e16ecfb9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49226
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:21:38 +00:00
Yu-Ping Wu 8a82ea9faa ec/google/chromeec: Check AP reset cause for watchdog reset
Different from mt8183, mt8192 doesn't need to trigger EC reboot on HW
initiated watchdog reset. Therefore, ec_reset_flags cannot be used to
determine AP watchdog reset. Instead we check the cause of the last AP
reset.

BUG=b:174443398
TEST=emerge-asurada coreboot
TEST=crash.WatchdogCrash passed on asurada
BRANCH=none

Cq-Depend: chromium:2607150
Change-Id: I761ecdd8811e5612b39e96c73442cc796361d0f0
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49113
Reviewed-by: Nicolas Boichat <drinkcat@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:20:54 +00:00
Yu-Ping Wu 9ff7823fe1 ec/google/chromeec: Update ec_commands.h
This change copies ec_commands.h directly from the Chromium OS EC repo
at SHA afffc28f2, with the exception of changing the copyright header
to SPDX format.

Change-Id: Ie02e0295312050e803a7d701ec4eed1dadfa6c9a
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-08 08:20:37 +00:00
Angel Pons b6dff82aab cpu/intel/model_206ax: Always return a package from _CST
The _CST method is supposed to return a package. If a mainboard used
zero for all ACPI C-states, the generated _CST would return nothing,
which is invalid. Instead, return a package with no C-state entries.

This change is a no-op, since all mainboards have at least one valid
ACPI C-state. This is what `acpigen_write_CST_package()` does, too.

Change-Id: I1f531e168683ed108a8d6d03dee6f5415fd15587
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49092
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:18:13 +00:00
Angel Pons 04b2bb61fd sb/intel/bd82x6x: Remove space in function definition
Just a small change to follow the code style.

Change-Id: Ie838b82e12627478ea721f426efc4d557feb6ae3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49166
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:14:47 +00:00
hao_chou 1807cfbae9 mb/google/volteer: Update copano device tree
Update device tree override to match schematics.

BUG=b:175896481
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot

Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Change-Id: I1fb006d750bb2d670885ec8ccc627436c5078072
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-08 08:14:13 +00:00
hao_chou d880b5ccc5 mb/google/volteer: Add GPIO to copano support
Add support for gpio driver for copano

BUG=b:175896481
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot

Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Change-Id: I1e0f730c9865ed77c7071245b071315a9c6ea4c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48951
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:14:04 +00:00
hao_chou 6df453724f mb/google/volteer: Copano: Update SPD table
Add memory table to "mem_list_variant.txt", and command to generate files:
go run ./util/spd_tools/lp4x/gen_part_id.go src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/copano/memory/ src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt

DRAM Part Name                 ID to assign
MT53D512M64D4NW-046 WT:F       0 (0000)
H9HCNNNCRMBLPR-NEE             0 (0000)
MT53D1G64D4NW-046 WT:A         1 (0001)
H9HCNNNFBMBLPR-NEE             2 (0010)

BUG=b:175896481
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot

Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Change-Id: I2ace17e8fff12d3f5de15a35f609265d8b6ed6b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48948
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:13:31 +00:00
Raul E Rangel 55cf7088fd mb/google/zork: Unmap FCH IO-APIC PCI interrupts
Now that the _PRT generates a GNB IO-APIC routing table we no longer
need to route the PCI interrupts through the FCH IO-APIC. This change
unmaps the IRQs since they are no longer used.

BUG=b:170595019
TEST=Boot with `pci=nomsi amd_iommu=off` and verify /proc/interrupts

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3467934bfcac14311505bec49a12652490554e6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-08 08:13:07 +00:00
Raul E Rangel 9882dde03f soc/amd/picasso: Generate GNB IO-APIC PCI routing table
This adds support for generating a PCI routing table that routes to the
GNB IO-APIC. This means we no longer need to route to the FCH IO-APIC
for PCI interrupts.

BUG=b:170595019
TEST=Boot ezkinil to OS with `pci=nomsi amd_iommu=off` and verify
all peripherals are working

           CPU0       CPU1
  0:        112          0   IO-APIC   2-edge      timer
  1:          0         99   IO-APIC   1-edge      i8042
  4:          0       2523   IO-APIC   4-edge      ttyS0
  5:      34632          0   IO-APIC   5-fasteoi   mmc1
  7:       5646          0   IO-APIC   7-fasteoi   pinctrl_amd
  8:          0          0   IO-APIC   8-edge      rtc0
  9:          0         33   IO-APIC   9-fasteoi   acpi
 10:      88258          0   IO-APIC  10-edge      AMD0010:00
 11:          0      32485   IO-APIC  11-edge      AMD0010:01
 24:       3301          0  amd_gpio   3  cr50_i2c
 25:          0     235214   IO-APIC  28-fasteoi   amdgpu
 26:      67408          0   IO-APIC  31-fasteoi   xhci-hcd:usb1
 27:          0     488876   IO-APIC   8-fasteoi   mmc0
 28:       1265          0  amd_gpio   9  PNP0C50:00
 29:        656          0  amd_gpio  12  ELAN9004:00
 30:        413          0  amd_gpio  31  chromeos-ec
 31:      14153          0   IO-APIC   4-fasteoi   ath10k_pci
 32:          2          0  sysfstrig0      cros-ec-accel_consumer3
 33:          2          0  sysfstrig0      cros-ec-accel_consumer0
 34:          6          0  amd_gpio  62  rt5682
 35:          0      38937   IO-APIC  29-fasteoi   snd_hda_intel:card0, ACP3x_I2S_IRQ

Cq-Depend: chrome-internal:3452710
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3211ab351a332fafb7b5f9ef486bb6646d9a214c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-08 08:12:53 +00:00
Angel Pons 2ce045385a pineview boards: Drop MAINBOARD_HAS_NATIVE_VGA_INIT
Already selected from northbridge Kconfig.

Change-Id: I5a30769b4186041a15fd1264bb0d6efa32cb6eb4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49182
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:11:35 +00:00
Arthur Heymans 08cb80e6ab arch/x86/Makefile.inc: Clean up generated assembly stubs
At the moment neither verstage nor romstage has a generated assembly
stub. This was used when CAR was set up in romstage which is not the
case anymore.

Change-Id: Ia4a952f269cc2b3edf1290c80b7a63619c8c6c95
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-08 08:10:04 +00:00
Arthur Heymans c6bdabd983 payloads/external: Update cbfs-ints with CONFIG_UPDATE_IMAGE
Change-Id: Icfbfff3ba680a85eb2f683867064b19f40b9d40f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48898
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:09:08 +00:00
Arthur Heymans 17c951b2c4 */Makefile.inc: Add some INTERMEDIATE targets to .PHONY
Change-Id: I125e40204f3a9602ee5810d341ef40f9f50d045b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48897
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:08:07 +00:00
Arthur Heymans 51d23c589b util/crossgcc/.gitignore: Add cmake
Change-Id: I5ce346515f4468699396e214acfaa3b62f6d891d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-08 08:06:34 +00:00
Jeremy Soller dd874c80cd ec/system76/ec: Remove unused EC RAM fields
These fields were originally added for compatibility with the
proprietary ITE EC firmware, but the System76 EC firmware does not use
them. Take the opportunity to document most of the fields as well.

Change-Id: I5581437c67ec67705ce16ba20254183a0261fd83
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-08 08:06:20 +00:00
Julius Werner 1153b2ef5c cbfstool: Use flock() when accessing CBFS files
Trying to do multiple operations on the same CBFS image at the same time
likely leads to data corruption. For this reason, add BSD advisory file
locking (flock()) to cbfstool (and ifittool which is using the same file
I/O library), so that only one process will operate on the same file at
the same time and the others will wait in line. This should help resolve
parallel build issues with the INTERMEDIATE target on certain platforms.

Unfortunately, some platforms use the INTERMEDIATE target to do a direct
dd into the CBFS image. This should generally be discouraged and future
platforms should aim to clearly deliminate regions that need to be
written directly by platform scripts with custom FMAP sections, so that
they can be written with `cbfstool write`. For the time being, update
the legacy platforms that do this with explicit calls to the `flock`
utility.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I022468f6957415ae68a7a7e70428ae6f82d23b06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-08 08:04:04 +00:00
Maulik V Vaghela 7e06a9044a mb/google/dedede: Enable "FastPkgCRampDisable" upd for noise mitigation
As part of acoustic noise mitigation calibration, we need to enable
FastPkgCRampDisable upd along with slew rate = 1. This values has been
derived based on noise calibration done.

Please refer document 575216 for procedure.

BUG=None
BRANCH=dedede
TEST=correct value has been programmed and slew rate measurement
is correct on scope.

Change-Id: Ie42c8ab647ff42fa043b6f717a9834f9b9c551f6
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
2021-01-08 07:41:20 +00:00
Maulik V Vaghela 2e424ff2d7 soc/intel/jasperlake: Update acoustic noise related parameters
We need to fill Acoustic noise mitigation related UPDs only in
case when acoustic noise mitigation is enabled. This will also
clarify the user that they need to enable Acoustic noise
mitigation while using this config in mainboard.

We're only filling UPD for domain VR index 0 since there is only
one VR domain for JSL (VCCIN VR).
Reference: JSL EDS (Document# 613601) (Chapter 3.4)

BUG=None
BRANCH=dedede
TEST=UPD values are getting filled correctly when Acoustic noise
mitigation is enabled.

Change-Id: I0cf4ccfced13b0d32b3d20713eace63e66945332
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
2021-01-08 07:38:26 +00:00
Krishna Prasad Bhat 830306cc84 soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification
USBSUSPGQDIS is a disqualifier bit which will allow platform
to enter s0ix even if USB2 PHY SUS is not power gated. Disabling this
bit will ensure that USB2 PHY SUS is power gated before entering s0ix.

BUG=b:175767084
BRANCH=dedede
TEST=s0ix works on drawcia and USB wake from s0ix works fine.

Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
2021-01-08 01:51:23 +00:00
Kyösti Mälkki 7ae375d3bc ACPI: Remove ACPI_NO_SMI_GNVS
This was used as a guard to not raise SMI with
APM_CNT_GNVS_UPDATE. The handler has been removed
now completely.

Change-Id: I7726367fd16630aa4b4b25b24b05f740645066db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-07 22:23:13 +00:00
Eric Lai d7a364393a soc/amd/picasso: Add GRXS and GTXS method
Add GRXS and GTXS into gpiolib. We can align with Intel ACPI method
for the better usage. This benefits acpi.c to be more clear, too.

BUG=b:176270381
BRANCH=zork
TEST=Confirm the Goodix touchscreen functional.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1aa6a8f44f20577e679336889c849dd67cb99f2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-07 19:38:58 +00:00
Eric Lai 7cee566161 soc/amd/picasso: Add STXS and CTXS method
Add STXS and CTXS into gpiolib. We can align with Intel ACPI method
for the better usage. This benefits acpi.c to be more clear, too.

BUG=b:176270381
BRANCH=zork
TEST=Confirm the Goodix touchscreen functional.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If4fcd68496a712fdccf44b91a6192ef58a0a9733
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48943
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07 19:38:34 +00:00
Kevin Chiu f85a6899ac mb/google/zork: Decrease stamp_boost parameter for dirinboz
Original Stamp_boost parameter will cause boost time over 2500sec(3960sec)
To pass balance performance and skin temperature test, decrease stamp_boost:
2500 -> 1640

BUG=b:175364713
TEST=1. emerge-zork coreboot
     2. run balance performance and skin temperature test

Change-Id: I44f086af6b5dd552efd2bd1ef4db0d69b652826d
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-01-07 18:35:57 +00:00
Arthur Heymans 66dbd9c31e security/intel/txt: Don't run SCHECK on CBnT
This functionality only exists on legacy TXT.

Change-Id: I4206ba65fafbe3d4dda626a8807e415ce6d64633
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-07 17:21:28 +00:00
Sumeet Pawnikar 597a0ead71 mb/google/dedede: Add support for charger throttling
Add charger current throttling support for dedede baseboard

BUG=None
BRANCH=None
TEST=Built and tested on boten system

Change-Id: I79edba579249111294a982590660196f05be7eaf
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49083
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07 11:32:51 +00:00
Kyösti Mälkki 7522a8fe0f arch/x86: Move prologue to .init section
For arch/x86 the realmode part has to be located within the same 64
KiB as the reset vector. Some older intel platforms also require 4 KiB
alignment for _start16bit.

To enforce the above, and to separate required parts of .text without
matching *(.text.*) rules in linker scripts, tag the pre-C environment
assembly code with section .init directive.

Description of .init section for ELF:

This section holds executable instructions that contribute to the
process initialization code. When a program starts to run, the
system arranges to execute the code in this section before calling the
main program entry point (called main for C programs).

Change-Id: If32518b1c19d08935727330314904b52a246af3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47599
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07 11:02:03 +00:00
Angel Pons ca965496ff cpu/intel/haswell: Rename `HASWELL_BCLK` to `CPU_BCLK`
This is just to ease merging with Broadwell.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I9239489fe48f04714e6626b57ef07ca8b3013024
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46910
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07 10:30:49 +00:00
Martin Roth d95fe364aa mb/asrock/h110m: Remove MAINBOARD_POWER_ON_AFTER_POWER_FAIL
The MAINBOARD_POWER_ON_AFTER_POWER_FAIL symbol was removed in
Commit 9faae2b939.
The default is currently to keep power off after a power failure.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ib2ef450f5c64f663b9aa88f8870250e92898e308
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47671
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07 08:20:08 +00:00
Subrata Banik c7bbffa4cd soc/intel/icelake: Remove unused ENABLE_DISPLAY_OVER_EXT_PCIE_GFX
Mainboard user can select VGA_ROM_RUN_DEFAULT Kconfig hence
no need to have another ENABLE_DISPLAY_OVER_EXT_PCIE_GFX Kconfig to
load/execute VGA OpRom.

Change-Id: Id87f82d9c3657afad9db94b1ec0917121edfe2bb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49023
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07 08:19:47 +00:00
Wisley Chen 0363d6da2a mb/google/volteer/var/elemi: Tune i2c frequency
Tuning i2c frequency for elemi
I2C0: 396.6 KHz
I2C1: 395.9 KHz
I2C5: 397.1 KHz

BUG=b:176794161
BRANCH=volteer
TEST=emerge-voleteer coreboot, and measure i2c clock.

Change-Id: I23b04a9b5ff8873d9de12e762e8e2786ef474ac0
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-07 08:19:16 +00:00
Tim Chen fbf6ae127a mb/google/dedede/var/metaknight: update Goodix touch screen sequence
Update Goodix touch screen reset delay time to 180ms.

BUG=b:176213670
TEST=Build and boot Metaknight to OS.

Change-Id: I5801a36fb7c03b23046df16b1eaf4c548241bba5
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07 08:18:37 +00:00
Kane Chen b2510f2999 mb/google/zork: Modify variant to Shuboz support
1. Add ELAN touchscreen/touchpad to overridetree.cb
2. Follow Dalboz setting to add variant.c

BUG=b:174528384
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ic3193ca7957251841e75a7e5c7a16fc5047919fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48001
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07 08:18:21 +00:00
Matt DeVillier d8be3da579 mb/intel/jasperlake_rvp: Fix building with CONFIG_CHROMEOS unset
Make EC_GOOGLE_CHROMEEC_SWITCHES depend on VBOOT, rather than force
selecting it.

Change-Id: If96b2a935d2f7388a24be7d8e65c7dfc2c89a0fc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-07 08:16:50 +00:00
Matt DeVillier 1daa2c6944 mb/intel/adlrvp: Fix building with CONFIG_CHROMEOS unset
Make GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC depend on VBOOT,
rather than force-select it.

Change-Id: I0ec418d4182865636b6350f1ee151420d8e02c33
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-01-07 08:16:38 +00:00
Matt DeVillier d0e1db835a mb/google/lindar: Fix building with CONFIG_CHROMEOS unset
Make CHROMEOS_DSM_CALIB depend on CHROMEOS, rather than force-select it.

Change-Id: I4c3fd04ec00e0787381c58810938dd48f414635c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-07 08:16:27 +00:00
Matt DeVillier f3419b29b7 soc/intel/common/cse: Drop dependency on CHROMEOS for SOC_INTEL_CSE_LITE_SKU
The CSE lite SKU has 2 CSE firmware boot partitions vs 3 for the "normal"
SKU; this has nothing to do with building for ChromeOS or not, and by
having this dependency, boards with select the CSE lite SKU are unable to
build with CONFIG_CHROMEOS unset due to Kconfig dependency issues.

Test: build google/wyvern with CONFIG_CHROMEOS not set.

Change-Id: I6959f35e1285b2fab7ea1f83a5ccfcb065c12397
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-07 08:16:12 +00:00
Tony Huang 8a1e2e1765 mb/google/puff/var/dooly: Config I2C0 SerialIoDevMode
I2C0 has amplifier connection, thus set it to PchSerialIoPci.

BUG=b:170273526
BRANCH=puff
TEST=Build and check PCH serial IO config is set I2C0 to Mode 1

Change-Id: I9540f7b5538d37de53bcf43531488d714874a565
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
2021-01-07 08:15:28 +00:00