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Author SHA1 Message Date
Marc Jones
3a8556354d Missed a const in my previous checkin, r3426 (trivial). 
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2008-07-21 22:23:57 +00:00
Marc Jones
eafceddf6c Add manual HT BUID fixup to detect previously set BUIDs in early init. This fixes the non-coherent(sb) link running at default speed. 
Fix HT event notify to output useful information.

Signed-off-by: Marc Jones <marc.jones@amd.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2008-07-17 19:54:06 +00:00
Marc Jones
212486e9f6 Clean up AMD FAM10 HT variable initialization. The structure init is cleaner, avoid compiler warnings, and matches the AMD example code more closely. 
Signed-off-by: Marc Jones <marc.jones@amd.com>

Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2008-07-17 19:50:37 +00:00
Marc Jones
aee0796506 Clean up comments, whitespace, and copyright date in the AMD HT code. 
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2008-07-16 21:09:31 +00:00
Marc Jones
f0174b5a9c Find matching settings for each CPUs FID, VID, and P-state registers and initialize them. 
Supports single and split plane systems. Set P0 on all cores for best performance.
All APs will be in hlt(C1).

The platform warm rest logic has been updated to alway reset for HT and FID/VID setup. It is not optional anymore.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2008-04-22 23:27:53 +00:00
Marc Jones
da4ce6b451 Add early MSR and PCI register initialization. 
This fixes many default setting as well as erratas.
Some CPU core functions were moved from the HT init and platform specific code to the generic Fam10 CPU code.
 
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2008-04-22 22:11:31 +00:00
Stefan Reinauer
f8ee1806ac Rename almost all occurences of LinuxBIOS to coreboot. 
Due to the automatic nature of this update, I am self-acking. It worked in
abuild.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2008-01-18 15:08:58 +00:00
Stefan Reinauer
7e61e45402 Please bear with me - another rename checkin. This qualifies as trivial, no 
code is changed.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2008-01-18 10:35:56 +00:00
Marc Jones
8ae8c88220 Initial AMD Barcelona support for rev Bx. 
These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2007-12-19 01:32:08 +00:00