Commit Graph

41138 Commits

Author SHA1 Message Date
Michael Niewöhner 2b5892256c mb/intel/adlrvp: do UART pad config at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: I55815a824ea3a77e6e603ba4beb17457f37c48f5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-12 08:47:53 +00:00
V Sowmya 8cb7af8e7c mb/intel/shadowmountain: Enable Type-C subsystem
This patch adds the changes to enable the TCSS.

BUG=b:175808146
TEST= Boot shadowmountain board, Test the functionality of the Type-C
ports on both the mainboard and daughterboard by plugging in the Type-C
devices and verified the devices are detected via EC console and in the
OS.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ieaf1170ca718a14d24b773a4a85516e0bbfbb569
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51026
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12 04:26:39 +00:00
Felix Held 03a4bfc54d soc/amd/common/block/smu: rename mailbox register defines
Since we have the SMN access block now, rename the SMU mailbox interface
registers to clarify that those are in the SMN register space.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic5b7093f99eabd3c29610072b186ed156f335bd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-12 00:48:01 +00:00
Felix Held e995684fa1 soc/amd/common: factor out SMN access function from SMU code
The SMU mailbox interface gets accessed over the SMN register space, so
factor out those access functions into a separate common code SMN access
building block.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iabac181972c02ae641da99f47b2aa9aa28dae333
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-12 00:47:30 +00:00
Stanley Wu 5a702653cd mb/google/dedede/var/boten: Adjust p-sensor detect distance to 20mm
P-sensor vendor fine-tune detect distance as 20mm for WWAN SAR table switch.

BUG=b:179000150
BRANCH=dedede
TEST=run "i2cdump -y -f 15 0x28" to confirm registers as expected.
     un-approach:
       => register address: 0x01 value: 0x00
     approach:
       => register address: 0x01 value: 0x02
     Confirm WWAN SAR table work as expected.

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I659721e60aa0766ed4c277dae43ded222e18ad1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51343
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12 00:33:28 +00:00
Dmitry Torokhov 39c1b4f951 Documentation/acpi: switch example from edge to level interrupts
Configuring touch controllers to use edge-triggered interrupts is not
recommended as it is very easy to lose an edge when kernel drivers
disable the interrupt for one reason or another, and recovering from
this condition requires workarounds in the kernel.

Unfortunately the example setting up a touchpad used edge-triggered
interrupts, and this set up has been propagating through the boards.
Let's switch the example to use level interrupts instead.

Change-Id: I4dc8b91ed070ce117553b00a087ad709aeaf16af
Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-11 22:38:52 +00:00
Angel Pons a70d17dba2 mb/system76/lemp9: Drop unneeded memcfg values and comments
This mainboard uses a Comet Lake SoC and mixed-topology DDR4 memory.
Drop LPDDR-specific DQ and DQS mappings and comment about Cannon Lake.

Change-Id: Icb986d1c074e64b3cfad3897b69d35d108f64bff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-03-11 17:12:25 +00:00
Aamir Bohra 813a3bafa8 driver/intel/fsp2_0: Allow function to run serially on all APs
EFI_PEI_MP_SERVICES_STARTUP_ALL_APS passes in a boolean flag singlethread
which indicates whether the work should be scheduled in a serially on all APs
or in parallel. Current implementation of this function mp_startup_all_aps
always schedules work in parallel on all APs. This implementation ensures
mp_startup_all_aps honors to run serialized request.

BUG=b:169114674

Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I4d85dd2ce9115f0186790c62c8dcc75f12412e92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51085
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11 15:54:04 +00:00
Aamir Bohra 7e0019ef20 src/cpu/x86: Add helper mp_run_on_all_aps
Add a helper function mp_run_on_all_aps, it allows running a given
func on all APs excluding the BSP, with an added provision to run
func in serial manner per AP.

BUG=b:169114674

Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I74ee8168eb6380e346590f2575350e0a6b73856e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51271
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11 15:53:58 +00:00
Felix Held a5cdf75f69 soc/amd: move warm reset flag function prototypes to common code
Even though the implementation is different on Stoneyridge compared to
Picasso and Cezanne, the function prototypes are identical, so move them
to the AMD SoC common reset header file.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-11 15:11:20 +00:00
Eric Lai 4626a6684c mb/google/mancomb: Add eSPI configuration
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie3a3bb7526d734ae1936b8c4db43543b1174829d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11 15:09:39 +00:00
Eric Lai e6b3168ff1 mb/google/mancomb: Enable mancomb variant
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I554e7193494a4bbf005aaf2fb4efd6ded383fe07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11 15:09:29 +00:00
Eric Lai b9204fc012 mb/google/mancomb: Enable console UART
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia03169c524dd12b8e7803ea8039c0e98a2b069e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11 15:09:06 +00:00
Eric Lai c23fa81e94 mb/google/mancomb: Enable ACPI tables
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I623fd052404a08cf0adb471bb654622960f1aa62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11 15:08:51 +00:00
Eric Lai 6f06883856 mb/google/mancomb: Enable CONFIG_CHROMEOS
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I45dcaa8b430721f864d4e5d78ae60883175085c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11 15:07:41 +00:00
Eric Lai 6bb5b9a058 mb/google/mancomb: Add stubs to configure GPIOs
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I7de5e4a4d2273d0ea5a84210ea0ce28d312eaa95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11 15:07:06 +00:00
Subrata Banik 0603902525 soc/intel/common/block/cpu: Use tab instead of space
Convert the lines starts with whitespace with tab as applicable.

TEST=Built google/brya0 and ADLRVP with BUILD_TIMELESS=1: no changes.

Change-Id: Ibd11ad12caa1be866a851a8cd4bd23349e8ffbbe
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51375
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11 05:06:43 +00:00
Jonathan Zhang 492a792d38 soc/intel/common/block: Add PCI IDs for EmmitsBurg PCH
According to Intel EmmitsBurg EDS, doc# 606161:
* Add PCI devid for SPI.
* Add PCI devid for ESPI (LPC).

EmmitsBurg (EBG) PCH is used in the chipset with Sapphire Rapids
Scalable Processor (SPR-SP).

Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ie8925cb739c95c34febf9002149de437d19c8234
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-11 04:26:21 +00:00
Mathew King 238242bda4 mb/google/guybrush: Enable USB ports in devicetree
BUG=b:180529005
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I94d97a38d992f46b32c2c6aca4c8da688d3b76fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51257
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11 01:17:40 +00:00
Mathew King 72cdbfa2f3 mb/amd/majolica: Enable USB ACPI in devicetree
BUG=b:180529005
TEST=boot majolica, all USB ports work

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I6d3506bb4d54c7f8ea1e53576ef68d2aface6c89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-11 01:17:09 +00:00
Mathew King 641690b7ae mb/google/guybrush: Enable Chrome EC SKUID and BOARDID
BUG=b:181910592
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I7851d3b11ea3b026b999019d02df1144f8393753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-11 01:16:20 +00:00
Mathew King 454426d9d0 mb/google/guybrush: Log mainboard events to elog
BUG=b:180653357
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ifd43d9cc1832d8ed8d90c68ba88b5667e3c04f89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-11 01:14:32 +00:00
Mathew King 78f0301ba4 mb/google/guybrush: Add chomeec device to lpc bridge
BUG=b:180507937
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I7b8b2ab73d66e0aaa0e9b7570661c885f7f777ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51296
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 23:49:11 +00:00
Mathew King c519bff9c1 soc/amd/cezanne: Add USB ports to chipset.cb
BUG=b:180529005
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I16de0869abd1eff4e89cf1b8128775858702acb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-10 23:47:03 +00:00
Kane Chen 807ce6258a mb/google/zork/var/shuboz: support regular/numpad touchpad
Define the 26th bit of the fw_config for the regular touchpad
and numpad touchpad selection.

REGULAR_TOUCHPAD: 1
NUMPAD_TOUCHPAD: 0

BUG=b:174964012
BRANCH=zork
TEST=build pass

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ie2055d6bb45a64bc0e59209cecc0f8a31c0f3718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-10 23:44:49 +00:00
Angel Pons 06b20ceb2f mb/{amd/padmelon,google/zork}: Do not select `VGA_BIOS`
The VGA BIOS for AMD Padmelon and Google Zork are stored in `amd_blobs`.
Do not force inclusion of VGA BIOS when `USE_AMD_BLOBS` is not enabled.

Change-Id: I206e8fadc14ec0d9b162dc4d72813fdd3d43958b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-10 23:42:53 +00:00
Angel Pons 83f9f8983b mainboard: Drop unnecessary `VGA_BIOS` default
This option defaults to n already.

Change-Id: I9f6407152f7cf2e2ac6fd1fff874e400f89a27ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-10 23:35:00 +00:00
Raul E Rangel 42c5b010b6 soc/amd/picasso: Fix PSP_SHAREDMEM_BASE
PSP_SHAREDMEM_BASE made the assumption that _psp_sharedmem_dram would
only match once. With CB:49332 there are now two symbols, and it was
grabbing the wrong one.

This change makes it so we match the exact symbol. It also switches to
using awk to simplify the code.

The bootblock.elf target that is added to the list of prerequisites also
creates the bootblock.map file that gets used to extract the base
address of the _psp_sharedmem_dram symbol.

BUG=b:181354692
TEST=Boot zork past bootblock

Fixes: 82d16b150c ("memlayout: Store region sizes as separate symbols")
Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I79675bd73f964282b54bca858830e26de64037c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-10 23:32:46 +00:00
Matt Papageorge a37ec522e1 mb/amd/majolica: Update to use proper APCBs built for Majolica
Some of the previous binaries were incorrect and should not be used
for Majolica because they are templates instead of APCBs specifically
built for the board. This APCB update also places the UMA region under
4G and size 32 MB which is essential for video output.

TEST=Boot with UEFI BIOS and verify we can get to OS. Also verify memory
region size, base and alignment.

Change-Id: Id797e2ad5bd67815c09752aedc19dad7dcf8ad12
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-10 23:28:19 +00:00
Kane Chen d3a767f47e mb/google/zork/var/shuboz: adjust I2C2 data hold time for TP
Add ".data_hold_time_ns" to follow I2C specification.
The adjusted result aobut 0.315us(more than 0.3us)

BUG=b:181091107
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Id92fadcb54b9722709e32ced1f0be001b8c97975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-10 23:10:30 +00:00
Nikolai Vyssotski ad68e69612 soc/amd/common/block/graphics/graphics: GOP: implement vbt_get()
Even though AMD does not need VBT we still need to implement the
vbt_get() function to not break the build with GOP driver enabled
(see fsps_return_value_handler() in fsp2_0/silicon_init.c

BUG=b:171234996
BRANCH=Zork

Change-Id: I80a5131a9852a05998b55b847243748d24cf535f
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-10 23:07:08 +00:00
Mathew King 612e403d53 mb/google/zork: Use SOC defines instead of magic numbers
BUG=b:182269526
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I351fb4fc493bb92b31e2c8bc946dfb048045335c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-10 23:05:41 +00:00
Mathew King 729c61961c soc/amd/picasso: Allow GPIO defines to be used in ASL
BUG=b:182269526
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ib33a46a6eead84eaff2c4ac320800b7993f5c3f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-10 23:05:27 +00:00
John Su 2f67b34e12 mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
To define Mainboard Type config, use the fw_config bit[26].
Check MB Type to modify SDLE settings for different VCORE IC.

BUG=b:177193131
BRANCH=zork

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-10 23:04:32 +00:00
Chris Wang 216d69d459 mb/google/zork: add UPDM updating function before runing FSP-M
Add the UPD updating hook in early stage for customization.

BUG=b:117719313
BRANCH=zork
TEST=build,check the hook function been executed.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4954a438a51b29b086015624127e651fd06f971b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51181
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 23:03:59 +00:00
Felix Held 9a6bc07cc2 soc/amd/cezanne: select common APOB NV cache code
BUG=b:181766974

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I660f19d18810c35dafcd75bcd1993216b7b09644
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51268
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 20:44:45 +00:00
Ronak Kanabar e1a27f2e49 vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2081_02
The headers added are generated as per FSP v2081_02.
Previous FSP version was v2037.
Changes Include:
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
- Add DevIntConfigPtr and NumOfDevIntConfig UPDs in Fsps.h

BUG=b:180758116
BRANCH=None
TEST=Build and boot ADLRVP

Cq-Depend: chrome-internal:3669105
Change-Id: Ib99748a428709ffad27d47f600e00bd91b70d8f3
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51248
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 20:30:20 +00:00
Jakub Czapiga 1add483819 tests/Makefile.inc: Enable support for multiple test groups
Until now output of all test groups run in single unit test were
saved in the same file which caused Jenkins to fail because
of existence of multiple root XML elements.
Now each test group is saved to its own file containing its name
at the end of the filename.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I21ba512073bc8d8693daad8a9b86d5b076bea03f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-03-10 20:23:19 +00:00
Gwendal Grignou 689c25b9d6 drivers/i2c: sx9310: Replace register map with descriptive names
The current driver is using chip registers map to configure the SAR
sensor, which is opaque, especially when the datasheet is not published
widely.

Use more descriptive names, as defined in Linux kernel documentation at
https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/proximity/semtech%2Csx9310.yaml

BUG=b:173341604
BRANCH=volteer
TEST=Dump all tables, check semtech property:
for i in $(find  /sys/firmware/acpi/tables/ -type f) ; do
 f=$(basename $i);  cat $i > /tmp/$f.dat ; iasl -d /tmp/$f.dat
done
In SSDT.dsl, we have:
Package (0x06)
 {
     Package (0x02)
     {
         "semtech,cs0-ground",
         Zero
     },
     Package (0x02)
     {
         "semtech,startup-sensor",
         Zero
     },
     Package (0x02)
     {
         "semtech,proxraw-strength",
         Zero
     },
     Package (0x02)
     {
         "semtech,avg-pos-strength",
         0x0200
     },
     Package (0x02)
     {
         "semtech,combined-sensors",
         Package (0x03)
         {
             Zero,
             One,
             0x02
         }
     },
     Package (0x02)
     {
         "semtech,resolution",
         "finest"
     }
 }

Change-Id: I8d1c81b56eaeef1dbb0f73c1d74c3a20e8b2fd7b
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-10 19:33:01 +00:00
Felix Held e4a7e46a9c soc/amd/stoneyridge/smihandler: sort includes alphabetically
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib317493fe938fe961aed06557e655ed8498e2694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-10 19:18:03 +00:00
Felix Held 2966e0d863 soc/amd/stoneyridge/smihandler: remove unused device/pci_def.h include
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I388cdb1fb9b3decaa6eb6e0e4e538c620d3048a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-10 19:17:56 +00:00
Angel Pons 34be1be240 nb/intel/haswell: Finalize northbridge in ramstage
There's no need to finalize the northbridge in SMM. This also makes
unification with Broadwell easier.

Tested on Asrock B85M Pro4, still boots and registers get locked.

Change-Id: I8b2c0d14a79e4fcd2e8985ce58542791cef9b1fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-10 10:59:36 +00:00
Angel Pons ae999503f6 nb/intel/haswell/pcie.c: Add missing pre-ASPM init
Add devicetree configuration parameters for mainboard-specific settings,
and provide reasonable defaults, which should usually be good enough.
This is based on Haswell SA Reference Code version 1.9.0 (Nov 2014).

Tested on Asrock B85M Pro4, registers now have the expected values.

Change-Id: I0dcdd4ca431c2ae1e62f2719c376d8bdef3054bd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47223
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 10:08:45 +00:00
Angel Pons 517750745f soc/intel/common/block/smm: Ignore PM1 and GPE0 events in SCI mode
When the SCI_EN bit is set, PM1 and GPE0 events will trigger a SCI
instead of a SMI#. However, SMI_STS bits PM1_STS and GPE0_STS can
still be set. Therefore, when SCI_EN is set, ignore PM1 and GPE0
events in the SMI# handler, as these events have triggered a SCI.
Do not ignore any other SMI# types, since they cannot cause a SCI.

Note that these bits are reserved on APL and GLK. However, SoC-specific
code already accounts for it. Thus, no special handling is needed here.

Change-Id: I5998b6bd61d796101786b57f9094cdaf0c3dfbaa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-10 09:52:22 +00:00
Hsin-Hsiung Wang 8d735d2aa3 soc/mediatek/mt8192: mt6315: revise initial setting
Remove unused boot status settings.
Reset the power-off sequence to zero to meet hardware requirement.

BUG=b:179000151
BRANCH=none
TEST=boot asurada correctly

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: Ie9d39be532ec378bd6df6bf1b93307dae4068fc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51246
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 01:29:14 +00:00
Hsin-Hsiung Wang 8579f23353 soc/mediatek/mt8192: mt6315: update initial flow
We saw EXT_PMIC_EN1 and PPVAR_DVDD_PROC_BC power off sequence
failure, and after checking MT6315 MT6315 PMIC protection key
summary.xlsx and MT6315 Top and CLK programming guide.docx,
we found there are something wrong about the sequence of magic
key protection flow and clk setting. Update correct initial
flow.

BUG=b:179000151
BRANCH=none
TEST=boot asurada correctly

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I1b7f970a44904fda09a97f4064eef7c95feefad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51245
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 01:29:07 +00:00
Hsin-Hsiung Wang 670cd9719e soc/mediatek/mt8192: mt6315: update correct slave id
The initial settings for MT6315 were not applied correctly
because the setup process didn't specify correct slave id
(incorrectly always sending 0), and may cause failure in
power off sequence.

BUG=b:179000151
BRANCH=none
TEST=boot asurada correctly

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: Ifd04da8ac55bcc9f9fdbc088d430522c2725ad47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-10 01:28:58 +00:00
Mathew King bac0f26e08 drivers/usb/pci_xhci: Add cezanne xhci pci devce id
BUG=b:180529005
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I836bb838cc97593451f869490ff3c9dd156245b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51349
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 00:47:18 +00:00
Mathew King ee10ce6268 mb/google/guybrush: Add smihandler
BUG=b:180507707
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I25ce0ca869ca854ff33242d2c416319e9688cc6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51264
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 00:38:23 +00:00
Mathew King ad83023425 mb/google/guybrush: Enable Chrome EC
BUG=b:180507937
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I3cdd6422b1bc53ea934346327359cbc6d86baeeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51043
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 00:35:06 +00:00