Double the space for psp2dir to 0x200.
Based on advice from AMD, increase the region containing
the signature to 4K.
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit e03a9402711c3a210816d0aa32865491a0523639)
Change-Id: If60132f913928bab0c2fe4aacedf342080929599
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17148
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit 482b65c219b932fd374f2ac469a023db219a66de)
Change-Id: I0a24a0aa4c7d9f4a8cc3ee9b7da60ea7704e6f17
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17147
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
Make the PSP2 smufirmware2 name unique so the command-line option
gets picked up.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: <marcj303@gmail.com>
(cherry picked from commit 98cf3880797f72aeb7169c3f8718a10092af9624)
Change-Id: I5430cf8b81fb03c95e6ee9d7e53455e6224256ff
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17146
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
1. Change the function which integrated one firmware, to the function
which pushes the whole group. Use fw_table as a parameter instead
of using the global table name.
2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2
can exist without PSP1. For some APU, the PSP directory has to be
put in PSP2 field (ROMSIG 0x14).
3. Reserve 32 more bytes in PSP2 header. It is defined by spec. It
is tested, and it is true.
These above changes are overlapping, hard to split them. Sorry.
Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/13808
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
If we only need to "combo" two PSP directories into one image,
we can put first address in romsig 0x10 and second one in
romsig 0x14.
If we really need to put three, the 0x14 is the combo directory
which points to multiple level-2 PSP directories.
I guess that two PSP can also use combo directory, with only
one level-2 directory. But nobody seems to do that.
Change-Id: Ic450a846bc04db90a75cd417b6d7104fe2a5b177
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/13739
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
I didn't go back through the development guide for this.
But based on test, if the empty entry is filled as 0xFFFFFFFF,
instead of 0, the USB3 port can not be used.
Leave the entries of PSP and PSP2 as 0xFFFFFFFF to be compliant
with the case before the amdfwtool is used.
Change-Id: Icd5f9891e541279dbd551bbceaf091488d22bfef
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/12665
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
PSP2 is for Combo BIOS, which is the idea that one image supports 2
kinds of APU.
The PSP2 feature is for the future, not for current products.
The newest document about PSP2 is not available. I made it from the
draft code I made when I was in AMD.
Change-Id: I65328db197c02ee67f3e99faf4ab8acabd339657
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/12474
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Combine all needed AMD firmware into one single firmware, which going to
be added as one single CBFS module.
Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/12419
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Marc Jones