Commit Graph

39178 Commits

Author SHA1 Message Date
Kyösti Mälkki 61bc2191c3 ACPI: Fix some GNVS field comments
Change-Id: I0d1e7b86d5b98da85bf539a4a3ec23e0eeaa4dfc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-25 02:28:02 +00:00
Kyösti Mälkki e1b4be1470 sb,soc/intel: Fix GNVS OperationRegion
Structure with chromeos_acpi_t is expected to have size
0x1000. Only ones with device_nvs_t have size 0x2000.

Change-Id: I2eaa3a008566853b4144fa34ccffaa232d5d8e24
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-12-25 02:27:37 +00:00
FrankChu 39f582815d mb/google/dedede: Update galtic device tree
Update galtic device tree override to match schematics.

BUG=b:170913840
BRANCH=dedede
TEST=emerge-dedede coreboot

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I270cd2a9783030ad3a080b9cfda8a133e801c5ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-25 02:27:08 +00:00
Matt DeVillier 395ab9da93 soc/intel/common/gfx: rename and guard graphics_soc_init()
Rename to graphics_soc_panel_init, to more accurately convey
operations performed by the function. Guard execution so we
don't attempt to reconfigure the panel after FSP has already
done so.

This fixes FSP/GOP display init on APL/GLK, which was broken by
attempting to configure the panel after FSP had already done so.

Change-Id: I8e68a16b2efb59965077735578b1cc6ffd5a58f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48884
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-25 02:25:57 +00:00
Patrick Rudolph 09cdeba606 drivers/ipmi: Add Supermicro OEM commands
Add a new driver for OEM commands and select it from x11-lga1151-series.

The driver communicates the BIOS version and date to the BMC using OEM
commands. The command should be supported on all X11 series mainboards,
but might work with older BMC, too.

Tested on X11SSH-TF:
The BIOS version strings are updated on boot and are visible in the
BMC web UI.

Change-Id: I51c22f83383affb70abb0efbcdc33ea925b5ff9f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-25 02:25:49 +00:00
Sam Lewis 1c18f8679f Documentation: Add Beaglebone Black documentation
Change-Id: If1a9808d1f20ee61048182d416f25e9a81c631af
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-24 08:30:28 +00:00
Nico Huber 4f7b687fb7 libpayload/i8042: Add API to peek on keyboard input queue
Change-Id: I60699e044b5bacd3f5292fed7edbf529ae133284
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47592
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24 08:29:18 +00:00
Nico Huber 6e021d31f9 libpayload/keyboard: Add debug output to all state transitions
Change-Id: I643a821d4c41fc068f2bab0bd571b0a4a359f59a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24 08:29:07 +00:00
Nico Huber b2569eaa82 libpayload/keyboard: Hide console output by default
Change-Id: I855d975a4729da34a6fa73a63dbbd12c856bdc00
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24 08:20:32 +00:00
Nico Huber e9c572f203 libpayload/keyboard: Implement self-test
The keyboard self-test is required for some devices. At least one
device (integrated keyboard in a ThinkPad X201) actually starts the
test automatically leading to spurious output and no response for
the first seconds.

We wait up to 5s for the self-test result. On failure or timeout,
the command will be repeated until the 30s init timer runs out. This
happens all in the background of the UI polling loop.

To not unnecessarily delay the boot process, we first try an oppor-
tunistic initialization which skips the self-test.

Change-Id: Ie07b31e74d06e116ac81e76309621eed39a19b49
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24 08:20:16 +00:00
Nico Huber 777c599747 libpayload/keyboard: Add timestamp to track time spent in a state
Will be used to time out in states that don't always advance.

Change-Id: I28235e7638d8157cedf81fd915a41d28a1fc070b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47087
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24 08:20:01 +00:00
Nico Huber 260dd9eb7e libpayload/keyboard: Turn init sequence into a state machine
We'll process the init sequence as part of the polling loop. This
should have several advantages:

* It eases error handling, i.e. we can return to an earlier state.
* We don't have to stall initialization when a keyboard takes a
  little longer.
* Generally, these keyboards can be hot-plugged (albeit not by
  design).

Change-Id: I9cf5cf31eb420b3994bec20e56a72d37f3d2996e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24 08:19:48 +00:00
Nico Huber 828f6b428e libpayload/keyboard: Avoid races around input draining
Draining the keyboard's buffer is only possible when the keyboard
port is enabled. We should also disable input scanning before, as
the buffer could be filled again with new keystrokes otherwise.

Change-Id: Ibac9c0d04880ff4a3efda5ac53da2f9731f6602c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24 08:19:18 +00:00
Nico Huber f7faac151a libpayload/keyboard: Introduce keyboard_drain_input()
Move the input-buffer draining into a function. It uses the low-level
i8042 API directly to avoid conflicts with changes in the high-level
keyboard API.

Change-Id: I9427c5b8be4d59c2ee3da12d6168d34590043682
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47084
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24 08:18:57 +00:00
Nico Huber a160d93dda libpayload/keyboard: Revise keyboard_cmd() error handling
Even if we are careful, it's still possible that we read spurious
data from the keyboard, e.g. keystrokes. Namely, when we send the
reset/disable command, there is a race before the command is pro-
cessed.

So we should always process data from the keyboard in a loop. We
break it, when an ACK (0xfa) or a NAK (0xfe) is received, and warn
on unexpected data unless it might be due to the mentioned race.

This also gives us the opportunity to use command-specific timeouts
which we take from Linux: 1s for the keyboard self-test (as there
are keyboards that perform the test before acking the command) and
200ms for all other commands.

Change-Id: I60a2643a8ff4b9231c63bf970c8749c97c7d8926
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24 08:18:41 +00:00
Angel Pons f651022df3 mb/prodrive/hermes: Drop EEPROM address function parameters
Only one EEPROM is used to store the board settings, and its I2C address
is constant. Thus, there's no need to pass its address as a parameter.

In addition, reduce the scope of the `I2C_ADDR_EEPROM` definition, since
using it outside of eeprom.c would bypass the API's abstraction layer.

Change-Id: I958304e6ed6df05af923139d44ff4fd1de204738
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-24 08:17:05 +00:00
Angel Pons 707e03d8b9 mb/prodrive/hermes: Use already-defined SMBus macros
Drop chipset register definitions in mainboard code in favor of existing
definitions in a header. These definitions are not mainboard-specific.

Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.

Change-Id: I29d6f35ec27bff43cf52ae697e905b6a7b48a8d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-24 08:16:53 +00:00
Patrick Rudolph 3e4f4e0229 mb/supermicro/x11-lga1151-series: Select DRIVERS_UART_8250IO
Change-Id: I0251d1193bb36ae73d592a0d17f580b7edaddbf6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48853
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24 08:16:37 +00:00
Kevin Chang 1cfc3a68e2 mb/google/volteer/variant/lindar: Add SSD D3 cold support
This patch add SSD D3 cold support for lindar.

BUG=b:172405687
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ie343bbff3bde4ff2a7e89bd384d5661af372b560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-24 08:16:28 +00:00
David Wu 9e2761fe2b mb/google/volteer/var/voema: Disable PCIe 7 and 8 for WLAN and SD card
Based on latest schematic, disable PCIe 7 and 8 for WLAN and SD card.

BUG=b:169356808
TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I2a4658a382c094c2a5b16b7acaf464f54e9897b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-24 08:16:19 +00:00
Felix Singer b8d614f8cc 3rdparty/fsp: Update submodule pointer to newest master
Newest master introduces the FSP for Tiger Lake client SKUs.

Change-Id: Id437faf72f1b8c5bc5310596bdab980e64614fa0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48712
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24 08:16:05 +00:00
David Wu f0df12dd17 mb/google/volteer/var/voema: Enable RTD3 for the NVMe device
Enable Runtime D3 for the volteer variants that have GPIO power control
of the NVMe device attached to PCIe Root Port 9.

Enable the GPIO for power control for variants that do not already have
it configured to allow the power to be disabled in D3 state.

BUG=b:169356808
TEST=tested on voema

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I28ef074225c533e1a97b6ec4a1a5dd1dcc198168
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48848
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24 08:15:51 +00:00
Johnny Lin 749a78d179 soc/intel/xeon_sp/cpx: Disable isoch operation for performance
Isochronous operation negatively impacts memory performance, as
per Intel MLC (Memory Latency Checker) benchmark results. Thus,
disable isochronous operation, like analogous UEFI firmware does.
The MLC results after disabling isoch:

"--max_bandwidth"
ALL Reads :         106948.17
3:1 Reads-Writes :  101580.46
2:1 Reads-Writes :  100523.26
1:1 Reads-Writes :  99059.44
Stream-triad like : 97762.47

"--peak_injection_bandwidth"
ALL Reads :         105724.3
3:1 Reads-Writes :  100655.8
2:1 Reads-Writes :  99463
1:1 Reads-Writes :  98708
Stream-triad like : 91515

The MLC results before disabling isoch:

"--max_bandwidth"
ALL Reads :         88824.96
3:1 Reads-Writes :  94820.81
2:1 Reads-Writes :  94867.53
1:1 Reads-Writes :  92567.36
Stream-triad like : 91900.43

"--peak_injection_bandwidth"
ALL Reads :         88859.6
3:1 Reads-Writes :  94064
2:1 Reads-Writes :  94186.2
1:1 Reads-Writes :  92516.1
Stream-triad like : 85147.4

TEST=On OCP Delta Lake, verify that MLC benchmark results have
improved.

Change-Id: I08c22ee001b601e607452b3f23fad969ecb484b4
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48738
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24 08:15:43 +00:00
Sunway a858ec86e4 mb/google/kukui: Add a new config 'Katsu'
A new board introduced to Kukui family.

BUG=b:176206134
TEST=make # select Katsu
BRANCH=kukui

Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I09fe2b8f6922dfd2af6424830568466fb98f7aee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-24 08:14:06 +00:00
Marc Jones 3c13af7ec9 soc/intel/common: Remove unused SOC_INTEL_COMMON_ACPI
Remove the unused SOC_INTEL_COMMON_ACPI Kconfig option.

Change-Id: Id62cd44e0f7e4175ae65c9388569231d5c8c1fbc
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-23 19:03:58 +00:00
Marc Jones 5da265c53e src/soc/intel/xeon_sp/acpi.c: Remove unnecessary .h
Remove the unnecessary header file includes.

Change-Id: I0d849cb236f304b87332aa64b2f10c73cad2d4dd
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-12-23 19:03:38 +00:00
Angel Pons d4d3ba0414 nb/intel/sandybridge: Refactor ODT stretch table code
Leverage existing `ch_dimms` value and use constants for brevity.

Change-Id: I4e08166c8e9fbd15ff1dcd266abb0689e4b159f7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-23 16:22:37 +00:00
Angel Pons 323c0aeb64 nb/intel/sandybridge: Refactor `dram_find_spds_ddr3`
Pointers to structs can be very useful, especially when they point to an
array element. In this case, changing one pointer allows the function to
be rewritten more concisely, since most redundancy can be eliminated.

Tested on Asus P8Z77-V LX2, still boots. No functional difference.

Change-Id: I7f0c37ea49db640f197162f371165a6f8e9c1b9c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-23 16:14:45 +00:00
Angel Pons 9f4ed3b550 nb/intel/sandybridge: Always wait for IOSAV after starting it
Ensure that IOSAV is finished before continuing. This might solve some
random failures on the I/O and roundtrip latency training algorithm.

Tested on Asus P8Z77-V LX2, still boots.

Change-Id: Ic08a40346b6c60e372bada10f9c4ee42eb974f9f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48403
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:11:35 +00:00
Angel Pons a853e7acdb nb/intel/sandybridge: Introduce `iosav_run_once_and_wait`
Most ofte, `iosav_run_once` precedes a `wait_for_iosav` call. Add a
helper function to reduce clutter. The cases where `iosav_run_once`
isn't followed by `wait_for_iosav` will be handled in a follow-up.

Tested on Asus P8Z77-V LX2, still boots.

Change-Id: Ic76f53c2db41512287f41b696a0c4df42a5e0f12
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48402
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:10:53 +00:00
Angel Pons edd7cb4d67 nb/intel/sandybridge: Remove unnecessary comments
These comments were helpful before the massive IOSAV refactoring, but
they are no longer needed since the function names are clear enough.

Change-Id: Ieb9bdf3f7fc72f63a8978f2b98e0bc8228c55868
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48401
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:05:50 +00:00
Angel Pons 7e439c9a5d nb/intel/sandybridge: Print delays in decimal
Print delay values in a suitable format for human consumption.

Change-Id: I0d86187d3e458ee2cb3fd11ec896ac363b8d3249
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48400
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:05:26 +00:00
Angel Pons 4d192820cd nb/intel/sandybridge: Add comment to TC_RWP write
Change-Id: I164daa59696f2fe8de3a4b3e7da46c7c723778eb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48602
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:05:06 +00:00
Angel Pons 30791639f8 nb/intel/sandybridge: Use proper names to refer to training steps
Now that the purpose of each training algorithm is clear, replace the
last instances of the original names in comments and print statements
with the current, correct names. Also, print which channel has failed
command training, for completeness and consistency with other errors.

Change-Id: I9cc5c4b04499297825ca004c6bd1648a68449d2c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48601
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:04:43 +00:00
Angel Pons 3aed6ac613 nb/intel/sandybridge: Add comments about I/O and RT latency
Document the algorithm to adjust I/O and roundtrip latencies.

Change-Id: Ic8b9aed54a34bb3252c457e87e81387fd410e305
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48397
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:04:22 +00:00
Angel Pons c8ac2ccf80 nb/intel/sandybridge: Rename I/O data timings
Tested on Asus P8H61-M PRO, still boots.

Change-Id: I147ba0ade8a5317a0fe76e9ea84947fd91d794b4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47773
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:03:44 +00:00
Angel Pons 9fcc110c37 nb/intel/sandybridge: Use bitfields for I/O data timings
Refactor in preparation to split up `program_timings`.

Tested on Asus P8Z77-V LX2, still boots.

Change-Id: I68410165f397d8b4f662e40e88fb6a58ab1c5cff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47772
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:02:17 +00:00
Angel Pons 075d123f6a nb/intel/sandybridge: Compute data timings independently
Use absolute values for the Rx and Tx bus timings instead of values
relative to the CA (Command/Address) bus timing. This makes the
calculations more accurate, less complex and less error-prone.

Tested on Asus P8H61-M PRO, still boots. Training results do not seem to
be affected by this patch, and the margins roughly have the same shape.

Change-Id: I28ff1bdaadf1fcbca6a5e5ccdd456de683206410
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47771
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:01:53 +00:00
Raul E Rangel 81ff33cffc Makefile: Add $(xcompile) to specify where to write xcompile
This file was being written to the root src directory. It is the only
file being written to src during a normal build, while all others are
being written to $(obj). I added a new variable to allow specifying the
xcompile path. This allows generating a single file if building multiple
boards. I also moved the default location into $(obj) so we don't
pollute the src directory by default.

I also cleaned up the generation of xcompile by removing the unnecessary
eval and NOCOMPILE check.

I also left .xcompile in distclean so it cleans up stale files.

Since .xcompile is written into $(obj), `make clean` will now remove it.

The tegra Makefiles are outside of the normal build process, so I just
updated those Makefiles to point to the default xcompile location of a
normal build. The what-jenkins-does target had to be updated to support
these special targets. We generate an xcompile specifically for these
targets and pass it into the Makefile. Ideally we should get these
targets added to the main build.

BUG=b:112267918
TEST=ran `emerge-grunt coreboot` and `make what-jenkins-does`

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia83f234447b977efa824751c9674154b77d606b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-23 03:40:35 +00:00
Subrata Banik deba7deda6 vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1514_11
List of changes:
FSP-S Header:
- Add UPD MicrocodeRegionBase and MicrocodeRegionSize
- Adjust UPD Offset for Reservedxx

Change-Id: I376abf6cd64dcf8c848901074e2c2f30d4f302da
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2020-12-23 03:32:42 +00:00
Nico Huber a69d682a0b libpayload/keyboard: Revise scancode set and translation config
Some background first: The original XT keyboards used what we call
scancode set #1 today. The PC/AT keyboards introduced scancode set #2,
but for compatibility, its controller translated scancodes back to
set #1 by default. Newer keyboards (maybe all we have to deal with)
also support switching the scancode set.

This means the translation option in the controller and the scancode
set selection in the keyboard have to match. In libpayload, we only
support set #1 scancodes. So we either need the controller's trans-
lation on and set #2 selected in the keyboard, or the controller's
translation off and set #1 selected in the keyboard.

Valid configurations:
* SET #1 + XLATE off
* SET #2 + XLATE on

Both with and without the PC_KEYBOARD_AT_TRANSLATED option, we were
only configuring one of the two settings, leaving room for invalid
configurations. With this change, we try to select scancode set #2
first, which seems to be the most supported one, and configure the
controller's translation accordingly. We try to fall back to set #1
on failure.

We also keep translation disabled during configuration steps to
ensure that the controller doesn't accidentally translate confi-
guration data.

On the coreboot side, we leave the controller's translation at its
default setting, unless DRIVERS_PS2_KEYBOARD is enabled. The latter
enables the translation unconditionally. For QEMU this means that
the option effectively toggles the translation, as QEMU's controller
has it disabled by default. This probably made a lot of earlier
testing inconsistent.

Fixes: commit a95a6bf646 (libpayload/drivers/i8402/kbd: Fix qemu)
       The reset introduced there effectively reverted the scancode
       selection made before (because 2 is the default). It's unclear
       if later changes to the code were only necessary to work
       around it.

Change-Id: Iad85af516a7b9f9c0269ff9652ed15ee81700057
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-23 03:29:32 +00:00
Nico Huber 0e1d19baa6 libpayload/i8042: Add API to get/set kbd translation state
Change-Id: I49aa1c244cb60ea290df102f06f641c765f59fa5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-23 03:29:16 +00:00
Subrata Banik 683c95e4ab soc/intel/alderlake: Enable support for extended BIOS window
Port commit ba75c4c (soc/intel/tigerlake: Enable support for
extended BIOS window) for Alderlake

Change-Id: Iaa8464d45884de433cca4f6a250cdd8d4c8f3661
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-23 03:29:00 +00:00
Subrata Banik 65f5932e0c soc/intel/alderlake: Add SPI DMI Destination ID
Port commit 237afda (src/soc/intel/tigerlake: Add SPI DMI Destination ID)
into Alderlake.

Change-Id: Ia0b465d405ab3c70b7d4094d32c182cab30fe531
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-23 03:28:47 +00:00
Subrata Banik 8943183b2c mb/intel/adlrvp: Make SI_ALL region within 16MiB
TEST=Able to build and boot ADLRVP.

Change-Id: I93da53f8835e0eec4cf4e78daab26332fd55d334
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-23 03:28:35 +00:00
Felix Singer e5706b6591 mb/clevo/cml-u: Reorder selects alphabetically
Change-Id: Idd02573e6b47c3bcbdcefa7b04fb9098b600df49
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-23 03:28:14 +00:00
Tim Wawrzynczak 7567890110 soc/intel/common: Fix XHCI elog driver
Commit 56fcfb5 misused the PCH_DEVFNs passed to the XHCI elog driver, by
passing them directly to pci_s_read_config32. This is incorrect, as it
is the wrong PCI devfn encoding to pass to that function.

BUG=b:175996770
TEST=abuild

Change-Id: Id7c146c1f50ee64a725bd50f9f11a7f159013a2b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-22 22:37:56 +00:00
Patrick Rudolph 7a66ffb34a soc/intel/common/block/acpi: Fix get_cores_per_package
Current implementation uses CPUID 0Bh function that returns the number
of logical cores of requested level. The problem with this approach is
that this value doesn't change when HyperThreading is disabled (it's in
the Intel docs), so it breaks generate_cpu_entries() because `numcpus`
ends up being zero due to integer division truncation.

- Use MSR 0x35 instead, which returns the correct number of logical
  processors with and without HT.

- Use cpu_read_topology() to gather the required information

Tested on Prodrive Hermes, the ACPI code is now generated even with
HyperThreading disabled.

Change-Id: Id9b985a07cd3f99a823622f766c80ff240ac1188
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-22 22:22:21 +00:00
Gaggery Tsai 8d127846bc soc/intel/cannonlake: Add Iccmax and loadlines for CML-S
Following up 3ccae2b7, this patch adds Iccmax and AC/DC
loadlines and iPL2 for CML-S CPUs. The information is from
CML EDS volume 1, doc #606599 and pdg #610244.

Change-Id: Id2797a979a8b6a52a34baae66f95c7136ed1dc72
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38288
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22 22:21:00 +00:00
Michael Niewöhner 8ba96b91dc soc/intel/apl/graphics: add missing left-shift
According to doc# IHD-OS-BXT-Vol 2b-05.17 the cycle delay is in the bit
range 8:4 of register PP_CONTROL. The current code writes the value to
bits 4:0, though. Correct that by shifting the value left by 4 bits.

Change-Id: If407932c847da39b19e307368c9e52ba1c93bccd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-22 20:34:27 +00:00