Commit Graph

29154 Commits

Author SHA1 Message Date
Jacob Garber 38b7445ad2 mb/google/poppy/variants/nami: Add fallthrough comment
This fallthrough is intentional (see commit 2257a35862 - Perform PL2
setting for syndra), so add a comment to make that explicit.

Change-Id: I57fe1e08f59aed12544cd2a71f1e0464f432f03b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1397063
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-03 13:18:11 +00:00
Arthur Heymans d44d4f0f4e mb/lenovo/*: Remove useless smihandler code
This code to handle the brightness from SMM is copied from the Lenovo
Thinkpad X60 code, but does not work on later generation. The PCI
device it tries to address does not even exist on those devices.

Change-Id: Ia959eb5b747846048396e66d4c926c96c27f3878
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33138
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 10:14:06 +00:00
Evgeny Zinoviev 60a0a3d629 ec/lenovo/h8: Fix method name in ACPI code
Fix a typo.

Change-Id: I2ab624eccd9bad36908df7fd739828e9ed8a4f62
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-03 10:10:21 +00:00
Nico Huber 2e6c3c8936 mb/google/link: Remove Link's own native graphics init
The code was already orphaned since its hook-up was removed
with a6be58fece (nb/intel/sandybridge: Remove the C native
graphic init).

Change-Id: Ia554c457e2f3a2dc42965ac5cded0be8e82311fb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-03 10:08:46 +00:00
Nico Huber ec93be5208 nb/intel/haswell/gma: Drop NGI remnant
The native graphics init option was replaced with libgfxinit.

Change-Id: I62569b70186b7b068effdadc4b39b3c09ddb7188
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33127
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 10:08:28 +00:00
Nico Huber d1b99d2bbf nb/intel/snb: Don't run VGA oprom when libgfxinit is enabled
This was likely an oversight when libgfxinit got its own Kconfig
symbols.

Change-Id: I647551719b332b5b734720ae4ee0619bbfcbed8c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33126
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 10:08:05 +00:00
Nico Huber bfd23ce87b soc/intel/common/mmc: Replace IS_ENABLED() with CONFIG()
Change-Id: I99d51176f6d7d6a98a3a3c82aa8e8eee73344496
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33111
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 10:05:55 +00:00
Matt DeVillier 0da3a8a91b soc/intel/baytrail: set default VBIOS filename and PCI ID
All Baytrail boards have the same GPU PCI ID, so set it
here to avoid having to set it in each board's config.

Move the VGA_BIOS_FILE config from google/rambi into soc/baytrail
since it likewise applies to all Baytrail boards.

Change-Id: Id1e0580b55e3590d868cb839987f06c49bb07cf5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33026
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-02 22:26:34 +00:00
Matt DeVillier a82f991122 google/buddy: fix Windows ACPI error with WLAN
Buddy's WLAN ACPI code was equivalent to, but formatted
differently from the other auron variants. Since only
differnce is root port used, have buddy use common
WLAN ACPI and use preprocessor guards to set the root
port correctly.

Test: build/boot Buddy, verify Windows 10 boots
without ACPI BIOS ERROR.

Change-Id: I78d994f2bb3981d4d10cb534cd6e0ae673f73527
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30523
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-02 22:26:14 +00:00
Nitheesh Sekar a2c219a91d qcs405: Enable SPI-NOR
Enable support for Gigadevice spi-nor flash.

Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-06-02 19:52:37 +00:00
Patrick Georgi c82acf5931 qualcomm/qcs405: enable SPI bus 4 for TPM
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-02 19:51:50 +00:00
Subrata Banik 2761847f90 Makefile.inc: Remove unnecessary CONFIG dependency
This patch removes unnecessary kconfig depencies as below
1. CONFIG_ARCH_RAMSTAGE_X86_32
2. CONFIG_RELOCATABLE_RAMSTAGE

Include required files as is without specify kconfig option.

Change-Id: Ic9d1a95e80178775dd78e756f97f6da13a24dc95
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
2019-06-02 04:11:29 +00:00
Tim Wawrzynczak f3510cbe36 mainboard/google/hatch: Add Helios support
Add Helios as a variant of Hatch.

BUG=b:133182138
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
  attempts to build a Helios target.

Change-Id: I64ba06932eb0ee32405f7b14a94971a64c8fce71
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32918
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-31 18:54:14 +00:00
Tim Wawrzynczak cdc459e66a mb/google/hatch: Create helios variant
Created helios (hatch variant).  Currenly copied from kohaku.  Helios-
specific changes will come later.

BUG=b:133182138
BRANCH=none
TEST=none

Change-Id: I9d151621a1c42e6f3cadb288f7ea476828c059b5
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-05-31 18:54:04 +00:00
Julius Werner a66c9b8bf4 string.h: Move common string functions into .c file
There's no clear reason why most of coreboot's basic string functions
are static inline. These functions don't particularly benefit from
inlining (at least not notably more than other functions). This patch
moves them to string.c to be more consistent with our usual coding
practices.

Leaving the ctype functions as static inline because they actually seem
small and collapsible enough that inlining seems reasonable.

Also clarified the situation of strdup() and strconcat() a bit more,
optimized strrchr() to be single-pass, fixed a bug with using strchr()
to find '\0' and got rid of unnecessary register keywords.

Change-Id: I88166ba9876e94dfa3cfc06969c78a9e1bc6fc36
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
2019-05-31 18:22:11 +00:00
Paul Fagerburg 7fa3d5673c mb/google/hatch: Create kindred variant
Create the Kindred variant of Hatch by taking a copy of the Hatch files
as placeholders. Kindred-specific changes will happen in future CLs.

BUG=b:133181366
BRANCH=NONE
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_KINDRED

Change-Id: I09ad3da0505d599fc3797d7fa24b4dc170dcd18b
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-31 15:28:25 +00:00
Furquan Shaikh a1d0928b00 soc/intel/common/block/gpio: Fix the mask for gpio_pm_configure
gpio_pm_configure clears out all the bits related to PM configuration
in MISCCFG register and sets only the bits requested by mainboard. The
mask as it is set currently results in preserving all PM bits instead
of clearing them. This change updates the mask to ensure that the PM
bits are cleared before setting the ones requested by mainboard.

Change-Id: I5b8c04952775dc1e94fa229328be2f3c1102a468
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-05-30 23:54:01 +00:00
Subrata Banik 695da71e61 src/vendorcode/amd/pi: Fix CONFIG() check issue in rules.h
This patch fixes problem of adding CONFIG() check inside
rules.h.

Change-Id: Ifb6842d0efef3521642c5c399fdf2876f71b167a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-30 15:12:07 +00:00
Nico Huber d64f889972 mb/lenovo/*20*: Remove default FMAP
These boards don't need a default FMAP. Moreover, having a default FMAP
disables automatic integration of optional regions like `CONSOLE`.

Also, these files contain an error: `COREBOOT` isn't placed at the top
of the image. Resulting in default builds without a reset vector ;)

Change-Id: If6331e19955034c02828e88902a5934c34d3e784
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33110
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-30 14:57:59 +00:00
Nico Huber 10490b98e2 mb/roda/rk9: Document flash header
Change-Id: I5bd131635340ffa0c6b8979fc8e263fc5f09fdc5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-30 13:46:41 +00:00
Patrick Georgi 2b99a01e0d soc/rockchip/rk3288: Disable bootblock console
Bootblock space is tight on this SoC and recent changes increased it
ever so slightly to make this a problem.

Since the bootblock is well-tested, we can get by without console.

Change-Id: I7496a3e313b2c6ee6fb3c4671eac64376d84e0dc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33068
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-30 03:46:20 +00:00
Damien Zammit 9b5e8c1718 xcompile: Remove --rtlib switch from clang CFLAGS
Fix the following error from clang invoking gcc linker with wrong arg:

i386-elf-gcc: error: unrecognized command line option '--rtlib=libgcc';
did you mean '-static-libgcc'?
clang-4.0: error: linker (via gcc) command failed with exit code 1

Just remove --rtlib switch from CFLAGS relating to clang

Change-Id: Ife7ef6b6b47a04598fc67b40751bc59eed93b4af
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/21354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-29 20:33:35 +00:00
Patrick Rudolph a95a6bf646 libpayload/drivers/i8402/kbd: Fix qemu
Reset keyboard controller to fix qemu make scan codes.

Change-Id: I5f8ad2d4be4b9e89d9af3a62726259e77f0403c1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/23584
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29 20:32:44 +00:00
Elyes HAOUAS e39db681df src/mainboard: Add missing 'include <types.h>'
<types.h> is supposed to provide <stdint.h> and <stddef.h>.
So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed.

Change-Id: I3b1a395cfe8b710fb6b468e68f4c92e063794568
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-29 20:29:28 +00:00
Elyes HAOUAS 27d02d8286 src/soc: Add missing 'include <types.h>'
<types.h> is supposed to provide <stdint.h> and <stddef.h>.
When <types.h> is included, <stdint.h> and/or <stddef.h> is removed.

Change-Id: I2db0a647bc657a3626cb5e78f23e9198e290261a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-29 20:28:56 +00:00
Elyes HAOUAS ab89edbccf src/southbridge: Add missing 'include <types.h>'
<types.h> is supposed to provide <stdint.h> and <stddef.h>.
When <types.h> is included, <stdint.h> and/or <stddef.h> is removed.

Change-Id: I4d8628e4ce3c7f80da2590b4cad618b290e0d513
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-29 20:28:41 +00:00
Elyes HAOUAS 51401c3050 src/northbridge: Add missing 'include <types.h>'
<types.h> is supposed to provide <stdint.h> and <stddef.h>.
When <types.h> is included, <stdint.h> and/or <stddef.h> is removed.

Change-Id: Iad5367bed844b866b2ad87639eee29a16d9a99ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-29 20:28:27 +00:00
Elyes HAOUAS 5fd93e0582 src/{ec,vendorcode}: Add missing 'include <types.h>
<types.h> is supposed to provide <stdint.h> and <stddef.h>.
So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed.

Change-Id: I1eb4163fb36a47b584f1fc9dd3c012e2930e9866
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-29 20:28:07 +00:00
Elyes HAOUAS bd1683da29 src/{device,drivers}: Add missing 'include <types.h>'
<types.h> is supposed to provide <stdint.h> and <stddef.h>.
So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed.

Change-Id: I3395715f9e2b03175089186ab2e57d9e508fc87c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-29 20:27:52 +00:00
Elyes HAOUAS b12ece98b0 src/{include,arch,cpu,lib}: Add missing 'include <types.h>'
<types.h> is supposed to provide <stdint.h> and <stddef.h>.
So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed.

Change-Id: I57aead27806e307b9827fc7ee2cd663f12ee6e5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-29 20:27:18 +00:00
Arthur Heymans 62c0b61bed soc/intel/denverton_ns: Don't use CONFIG_CBFS_SIZE
CONFIG_CBFS_SIZE is only meaningful to generate the default fmap
layout and ought not to be used in the code directly.

Change-Id: Iae72a9fb02d62d7548d34689f5eb371f34cd3d81
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31249
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29 20:24:13 +00:00
Christian Walter 543be8d367 payloads/external/Linuxboot: Fix Makefile when not using bash
Adding "SHELL := /bin/bash" to the Makefile makes sure, that we use the
bash shell which is needed here.

Tested with oh-my-zsh.

Change-Id: I71495e15b8f1a495af7d8ab21cc5235feb595e01
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33014
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29 20:22:38 +00:00
Christian Walter a998e28016 src/soc/intel/skylake/chip.h: Add smbios.h for Type9 Entries
In order to add the smbios_slot_desc for the SMBIOS Type9 entries into
the devicetree, and not use numbers but strings like
"SlotTypePciExpressGen3X4", smbios.h needs to be included in the
static.c.

Change-Id: Iace547868b4ce8eb7d3624baf1abd1187c1e5f51
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32965
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29 20:22:13 +00:00
Patrick Rudolph 23cb12b040 payloads/external/iPXE: Add more Kconfig options
Add two new options:
* Disable the prompt "Press Ctrl+B for the iPXE command line..."
Add a boolean that disables the initial 2 second timeout.

* Include a script that is executed instead of showing a shell.
Allows to add a script that will be included into the iPXE ROM.

Tested on Lenovo T500 and PC Engines apu2.

Change-Id: Ie1083d8571d9d1f1c7c71659fb6ff0de2eecad0e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/20782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-29 20:21:42 +00:00
Arthur Heymans 56e2d7d21a soc/intel/skylake: Use common cpu/intel/car romstage code
Setting up the console and entering postcar can be done in a common
place.

Change-Id: I8a8db0fcb4f0fbbb121a8195a8a8b6644c28db07
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32962
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29 20:18:43 +00:00
Arthur Heymans 73ac12196c drivers/intel/fsp1.1: Simplify bootflow and clean up
This gets rid of the boilerplate back and forward calls between the
SOC/FSP-driver code and mainboard code.

Change-Id: I5d4a10d1da6b3ac5e65efd7f82607b56b80e08d4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32961
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29 20:17:48 +00:00
Frans Hendriks 1ac5ecbfd1 soc/intel/braswell/acpi/globalnvs.asl: Remove redundant use of Offset
ASL compiler reports twice warning 'unnecessary/redundant use of Offfset operator'.

Remove redundant offsets.

BUG=N/A
TEST=Facebook FBG-1701 booting Embedded Linux

Change-Id: I16705b9392b17c50d3988012406e03de393cbcd2
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-29 20:14:27 +00:00
Elyes HAOUAS e955fa33f6 src/drivers/xgi: Move coreboot related includes to xgi_coreboot.h
Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-29 20:14:04 +00:00
Patrick Georgi 68999a8b86 commonlib: fix typo LB_TAB_* (instead of LB_TAG_*)
Also adapt all users of these symbols

Change-Id: Ibf924a283d438de49a93ce661b0d9ca1a81cd6d1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-29 20:12:57 +00:00
Patrick Georgi 3f4a987bee commonlib: renumber CB_TAG_TCPA_LOG
It conflicts with VBOOT_WORKBUF but unlike VBOOT_WORKBUF no user can be
identified in the coreboot tree for TCPA_LOG, so renumber this.

Change-Id: Ib8a850c0ccbcacdf7d288316b54eb82fce874a82
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-29 20:12:47 +00:00
Jacob Garber 5b922726e1 cpu/x86/mtrr: Assert that MSR arrays are fully initialized
The initialization logic for the fixed_msrs and msr_index arrays depends
on the contents of the fixed MTRR descriptor. However, Coverity is unable
to check these values and believes (incorrectly) that the arrays may not
be entirely initialized. An assert was added in commit b28025a434 to
ensure that one of the loops is entered, but it is simplest to just
check that msr_num has iterated over the entire array after the loops
are over. This also acts as a sanity check that the values in the MTRR
descriptor were hardcoded correctly.

Change-Id: Ia573792f74aa6ea5e659c1e2253f112184fbb0a5
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1370582
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-05-29 20:11:50 +00:00
Jacob Garber bdcb4d3750 drivers/generic/max98357a: Add extra error handling
It is possible that acpi_device_scope() and acpi_device_name() can
return NULL to indicate an error, so add error handling to check their
return values.

Change-Id: I4c7ab0c592845d9d5f142e078fc2b505a99ecd12
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1362592
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-29 20:11:19 +00:00
Matt DeVillier 924463d1a5 google/clapper: fix up devicetree
When clapper was upstreamed, the devicetree was pulled from
the wrong firmware branch, leading to some incorrect settings
and touchpad, touchscreen, and audio not working.

Correct devicetree settings using Chromium branch firmware-clapper-5216.199.B

Test: build/boot google/clapper, verify touchpad/touchscreen/audio
functional under Linux (GalliumOS 3.0/kernel 4.16.18).

Change-Id: Iacfce575a054b1f484149f36d0aa83d20d034d8a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-29 20:10:58 +00:00
Matt DeVillier 348a44ecae mb/google/{misc}: set default SMBIOS manufacturer
Legacy Google mainboards (pre-Skylake) shipped with the
SMBIOS manufacturer set to GOOGLE, which many Linux drivers
rely on for application of DMI quirks. Set it as the default
to avoid having to do so for each board's config

Change-Id: I61b0217f3535852d7d6e24a1ac78075c20c0825a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-29 20:10:08 +00:00
Nico Huber 342d3180d7 Makefile.inc: Extend version string for timeless builds
With the version string "TIMELESS", binaries are slightly smaller than
for a regular build. This may lead to false positive build tests if the
space is limited (e.g. bootblock). So let's make the string a little
longer.

Change-Id: I3bbf6f71d5bcd74728a3fe39734312690901d0ec
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32986
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29 20:09:24 +00:00
John Zhao 57448845ff soc/intel/apollolake: Fix value stored to gnvs is never read
Clang Static Analyzer found version 8.0.0 gnvs is allocated, but
it is never used. Change sizeof(*gnvs) to sizeof(global_nvs_t)
while adding ACPI GNVS to CBMEM.

TEST=Built and boot up to kernel.

Change-Id: Ie9421af4a556d1d88183aa938ee2a124a10ab727
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-29 20:09:17 +00:00
Patrick Rudolph 6336ee6df9 sb/intel/*: Delete early_spi
The file and all of it's functions are unused. Drop the dead code.

Change-Id: Iaddd7a688d431d40f38293939e084d19b286aed4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-29 20:08:31 +00:00
John Zhao 2bb432ece6 soc/intel/common: Check bios_size and window_size after MIN operation
Clang Static Analyzer version 8.0.0 detects that log2_ceil(bios_size)
and log2_ceil(window_size) are garbage or undefined if the value of
bios_size and window_size is zero. Check bios_size and window_size after
MIN operation to prevent error.

TEST=Built and boot up to kernel.

Change-Id: Ifc3f3da52d129ef5d6063a46b045603a236be759
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-29 20:08:04 +00:00
John Zhao 64fb5aa9c3 soc/intel/common: Set GSPI clock value to prevent division by zero
Clang Static Analyzer version 8.0.0 detects the division by zero if
gspi_clk_mhz is initialized to 0. gspi_clk_mhz is referred to speed_mhz
in devicetree. Set gspi_clk_mhz to 1 if it is detected as 0 in order to
prevent the division by zero in DIV_ROUND_UP operation. Then the value
of (ref_clk_mhz - 1) will be fed into GSPI's Serial Clock Rate value.

TEST=Built and boot up to kernel.

Change-Id: I6a09474bff114c57d7a9c4c232bb636ff287e4d5
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-29 20:07:26 +00:00
Evgeny Zinoviev 3d90d3bfce util/autoport: Add info about rank 1 mirroring
inteltool can't detect whether address mapping is normal or
mirrored, which in turn may be cause RAM initialization to
fail when using spd.bin generated by inteltool.

Mention this in readme as it may help someone.

Change-Id: I8d24e4d9332bdcf484987581dd6941e2bf9c4f87
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-29 20:07:10 +00:00