Commit Graph

30926 Commits

Author SHA1 Message Date
Bora Guvendik 6aeed16422 mb/google/drallion: Adjust GPD3 pin termination
Internal pull up need to be enabled for GPD3 as power button pin for
PCH according cometlake pch EDS vol1 section 17-1. Without that pin will
stay floating and hook up XDP can cause system shutdown as power buttone
event will trigger.

BUG=N/A
TEST=Hook up XDP on drallion platform, able to boot up into OS and stay
at power up state.

Change-Id: Idd1befeb14a251b7c0542ca1f99049d07b28fb98
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-09-30 04:51:31 +00:00
Aamir Bohra b09d44ef2d mb/google/drallion: De-assert WWAN reset signal
BUG=b:141734594

Change-Id: I419f7d11dffebe6c44eefa05750834d07d19857b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-09-30 04:31:10 +00:00
Kyösti Mälkki 23d4d9f368 amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICE
Change-Id: I265d50af1099ae4449b5adebcf21e2043aa02c7a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35654
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-29 03:39:33 +00:00
Kyösti Mälkki 0f639750a1 device/pnp_ops: Add ENV_PNP_SIMPLE_DEVICE
Source files including this may have locally defined
__SIMPLE_DEVICE__ so this cannot be placed in <rules.h>.

Change-Id: I2336111b871203f1628c3c47027d4052c37899dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35653
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-29 03:39:20 +00:00
Kyösti Mälkki 9d5af5b0c2 device/pci_ops: Add ENV_PCI_SIMPLE_DEVICE
Source files including this may have locally defined
__SIMPLE_DEVICE__ so this cannot be placed in <rules.h>.

Change-Id: If700dd10fd5e082568cd6866bfd802fc2e021806
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35652
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-29 03:39:06 +00:00
Kyösti Mälkki 91f2f03759 intel/fsp_baytrail: Drop unnecessary lookup for PCI 0:0.0
It is safe to assume this to be copy-paste from eg. i945
where registers of said PCI device were read.

Change-Id: I387b7fd6caf317543a6438f973d9e1d96e418de3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35668
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-29 03:38:41 +00:00
Kyösti Mälkki 32d47eb688 soc/intel: Rename <intelblocks/chip.h>
The filename chip.h has a special purpose with the generation
of static devicetree, where the configuration structure name matches
the path to the chip.h file. For example, soc/intel/skylake/chip.h
defines struct soc_intel_skylake_config.

The renamed file did not follow this convention and the structure it
defines would conflict with one defined soc/intel/common/chip.h if such
is ever added.

Change-Id: Id3d56bf092c6111d2293136865b053b095e92d6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-29 03:38:13 +00:00
Kyösti Mälkki 44da9e201c cpu,device/: Remove some __SIMPLE_DEVICE__ and __ROMCC__ use
Change-Id: I62d7450c8e83eec7bf4ad5d0709269a132fd0499
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28 21:18:03 +00:00
Kyösti Mälkki f2cc3dd8ea usbdebug: Remove some __SIMPLE_DEVICE__ use
We can always PCI config accessors with pci_devfn_t.

Change-Id: I6d98c2441cc870cdcadbe8fabc9f35b9ffc652d8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28 21:17:33 +00:00
Kyösti Mälkki 8f5138d8a5 drivers/net/ne2k: Remove some __SIMPLE_DEVICE__ use
Note that the code assumes mainboard code to configure
any PCI bridges prior to calling console_init().

Change-Id: I0312d359f153c02e4afcf1c09d79f9eb3019a8b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28 21:16:40 +00:00
Kyösti Mälkki a67eaec0d0 arch/arm,mips: Use generic PCI MMCONF
We need the stub header file. If PCI was implemented, assume
generic MMIO mapped configuration space would work here.

Change-Id: Ia731e5c5a6725fe22ab8b0398cafa1127ed90891
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28 21:16:23 +00:00
Kyösti Mälkki f485d91141 nb/via/vx900: Remove some __SIMPLE_DEVICE__ use
Change-Id: I840131f91e79c740c0c8784c252723ae90ded458
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28 21:16:02 +00:00
Kyösti Mälkki 13ad740701 device/pci: Replace some __SIMPLE_DEVICE__ use
Change-Id: Ide9df46b5ff47fea54b9de0e365638a6223c8267
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28 21:15:47 +00:00
Kyösti Mälkki d7205bebd5 nb,sb/intel: Clean up some __BOOTBLOCK__ and __SIMPLE_DEVICE__ use
Change-Id: Ie3f3c043daa6ec18ed14929668e5acae172177b3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28 21:15:27 +00:00
Kyösti Mälkki 197a3c6cea nb/intel/x4x: Avoid x4x.h header with romcc-bootblock
Change-Id: If8b70298bffd72d1de7f74917131d648c5fcab66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-28 21:15:02 +00:00
Alexander Couzens 3b8deeefa5 superiotool: add basic support for SCH5545
Based on the SCH5627 datasheet which is similiar
SCH5545 id 0xc4, SCH5627 id 0xc6.

Change-Id: I81f3f68690d2000a4fa8a1e703c01f54ebbce953
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/20237
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-28 18:39:10 +00:00
Aamir Bohra f3c485e21f mb/google/variants/drallion: Update the spd index map
BUG=b:141575294

Change-Id: I1b2b4362b84b170bd73b760828ca300ec86c4534
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-09-28 13:24:22 +00:00
Aamir Bohra 78d6ce45d4 mb/google/drallion: Set UART for console to UART controller 0
Drallion uses UART 0 for console, change the config accordindly.

BUG=b:139095062

Change-Id: I0ae2f8459b6225b99b758180413afa22386355d4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35633
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-28 13:22:07 +00:00
Arthur Heymans 965881b7ce Kconfig: Hide CONFIG_CBFS_SIZE when an FMDFILE is provided
CONFIG_CBFS_SIZE should only be used as a parameter to generate the
default FMAP.

This also swaps around FMDFILE and CBFS_SIZE to avoid that the
CBFS_SIZE entry disappears when filling in the FMDFILE entry below it.

One advantage is that if code references CONFIG_CBFS_SIZE the jenkins
buildtest will most likely fail as many boards provide an FMD file.

Change-Id: Ic7926e1638d7fb49ba61af28d682315786c3c39e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-28 12:14:12 +00:00
James Ye ef2e86edeb mb/lenovo/x131e: enable mSATA slot
Per google/stout.

Tested with SanDisk SSD U110.

Change-Id: I7cc9837f572236acac2007e95990e64c25a5d6e2
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2019-09-28 10:46:24 +00:00
James Ye 59de112995 mb/lenovo/x131e: correct USB port config
Based on schematic and register dumps.

Change-Id: I91fc47022988cfe986fb8c1ed21dc073ee7d16bc
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-09-27 22:27:45 +00:00
Furquan Shaikh b33a2b05af fmap: Add get_fmap_flash_offset()
CB:35377 changed the behavior of find_fmap_directory() to return
pointer to CBMEM_ID_FMAP if fmap is cached in
cbmem. lb_boot_media_params() calls find_fmap_directory to add offset
of fmap in flash to coreboot table. However, because of the change in
behavior of find_fmap_directory(), it ended up adding 0 as the offset.

This change adds a new function get_fmap_flash_offset() which returns
the offset of fmap in flash. Ideally, all payloads should move to
using the FMAP from CBMEM. However, in order to maintain compatibility
with payloads which are not updated, ensure that fmap_offset is
updated correctly.

Since find_fmap_directory() is no longer used outside fmap.c, this
change also removes it from fmap.h and limits scope to fmap.c.

In a follow up patch, we need to push a change to libpayload to expose
the fmap cache pointer to lib_sysinfo.

BUG=b:141723751

Change-Id: I7ff6e8199143d1a992a83d7de1e3b44813b733f4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2019-09-27 21:59:44 +00:00
Aaron Durbin 55ef0d25d3 device: add commentary to dev_find_slot()
dev_find_slot() can sometimes fail to return the desired device object
prior to full PCI enumeration. Comment the declaration and
implementation accordingly to help the user understand the problem and
avoid its usage.

Change-Id: I3fe1f24ff015d3e4f272323947f057e4c910186c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35632
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-27 21:08:24 +00:00
Michael Niewöhner 9965553011 mb/supermicro/x11-lga1151-series: remove unneeded vendor id config
The vendor id option set here is useless as most SSVID registers get
filled with 0x8086 (their VID) by default, anyway.

Besides that the Kconfig option isn't meant for retrofit ports, cf.
commit 7e1c83e31b (Add Kconfig options to override Subsystem Vendor and
Device ID). The right place would be the devicetree.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: If67c679bb342f63096902535734106e4f1651118
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-27 16:22:08 +00:00
Patrick Rudolph 0c9d8a4ef5 configs: Build test CONFIG_BOOTSPLASH
Change-Id: I306d107720d51c2b378f739f68c31b8642f7354a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35615
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-27 16:20:16 +00:00
Patrick Rudolph 5ebe431087 lib/bootsplash: Fix compilation
Add missing include.
Tested on Supermicro X11SSH-TF.

Change-Id: Id0c80ac646001a497e96cae4d48a0f09762eb936
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35613
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-27 16:20:04 +00:00
Kyösti Mälkki 9e77d4d037 arch/: Replace __BOOTBLOCK__ with ENV_BOOTBLOCK
Change-Id: I294a3fd7be57b505cd209f7c2718a05770786c51
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-26 17:27:45 +00:00
Himanshu Sahdev d1e18d9a44 coreboot/Makefile: display error when spaces in path of toplevel makefile
coreboot toplevel makefile breaks when path to the coreboot directory
contains spaces.
This patch displays a reasonable message to the user whenever spaces
are found within the path to the coreboot direcrory.

This commit addresses coreboot ticket #179.

Change-Id: Id11deffa01ddca1ff9332d67c7aa33a382b4cdc7
Signed-off-by: Sourabh Kashyap <sourabhka@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35434
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26 10:11:14 +00:00
Richard Spiegel 7ae4a268eb soc/amd/common/block/spi/fch_spi_ctrl.c: Fix SPI vendor id code
All solid state devices have vendor id defined by JEDEC specification JEP106,
which originally allocated only 7 bits for it plus parity. When number of
vendors exploded beyond 126, a banking proposition came maintaining
compatibility with older vendors while allowing for 4 extra bits (16 banks)
through the introduction of the concept "Continuation code", denoted by the
byte value of 0x7f.
Examples:
0xfe, 0x60, 0x18, 0x00, 0x00 => vendor 0xfe of bank o
0x7f, 0x7f, 0xfe, 0x60, 0x18 => vendor 0xfe of bank 2

BUG=b:141535133
TEST=Build and boot grunt.

Change-Id: I16c5df70b8ba65017d1a45c79e90a76d1f78550c
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-26 09:33:00 +00:00
Andrey Petrov 6aea9f9923 soc/intel/fsp_broadwell_de: move get_busno1() into vtd.c
TEST=just build it

Change-Id: I34aee507b8c322c816f92cfcae177c069c749ed7
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-26 09:30:24 +00:00
Michael Niewöhner 0a6c62fbbe mb/supermicro: restructure x11ssh-tf to represent a x11 board series
Most of the X11 boards with socket LGA1151 are basically the same boards
with just some minor differences like different NICs (1 GbE, 10 GbE),
number of NICs / PCIe ports etc.

There are about 20 boards that can be added, if there is a community for
testing.

To be able to add more x11 boards easily like x11ssm (see CB:35427) this
restructures the x11ssh tree to represent a "X11 LGA1151 series". There
were multiple suggestions for the structure like grouping by series
(x10, x11, x...), grouping by chipset or by cpu family.

It turned out that there are some "X11 series" boards that are
completely different. Grouping by chipset or cpu family suffers from the
same problem. This is why finally we agreed on grouping by series and
socket ("X11 LGA1151 series").

The structure uses the common baseboard scheme, while there is no "real"
baseboard we know of. By checking images, comparing logs etc. we came to
the conclusion that Supermicro does have some base layout which is only
modified a bit for the different boards.

X11SSH-TF was moved to the variants/ folder with it's gpio.h. As we
expect the other boards to have mostly the same device tree, there is a
common devicetree that gets overridden by each variant's overridetree.

Besides that some very minor modifications happened (formatting, fixing
comments, ...) but not much.

Documentation is reworked in CB:35547

Change-Id: I8dc4240ae042760a845e890b923ad40478bb8e29
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35426
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26 09:29:25 +00:00
Peichao Wang b68ebfa8fc mb/mainboard/hatch: support elan touchpad for Akemi
Modify IRQ pin from D21 to A21 and support wake-up from touchpad

BUG=b:141519690
TEST=build bios and verify elan touchpad works fine

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6cc5b780ffcee24f1f2a04e88c30628ceb5904e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35551
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26 06:02:49 +00:00
Peichao Wang c7d2235899 google/grunt: add new two DDR source for Treeya
new DDR particle:
1. Samung K4A8G165WC-BCWE
2. Hynix H5AN8G6NCJR-XNC

BUG=b:139085024
BRANCH=master
TEST=rework new source to DUT and re-flash bios to DUT and
verify DUT will bring up successfully

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I0d039af53938086733308a081a77a7398e7bf5d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-09-26 05:46:41 +00:00
Kyösti Mälkki 89c0ef7395 cpu/intel/: Clean up microcode update from __PRE_RAM__
Change-Id: Ib12985dd9a12495533a82be556405f975a0abe27
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-26 01:16:54 +00:00
Kyösti Mälkki 3de8f8c137 cpu/amd/pi/00730F01: Clean up microcode update from __PRE_RAM__
It is only called in ramstage. Even if it was called in
romstage, execution flow is such that BSP and AP CPUs
should not be able to enter update_microcode() routine
concurrently.

Also the Kconfig guarding the spin_lock() calls are not
selected nor are the lock variables declared for these
platforms.

Change-Id: I1c2e106f10e8420e942b3ed082c677c0db95557c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35586
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26 01:16:44 +00:00
Edward O'Callaghan da33246bc5 util/mainboard/google: Fix hatch variant script
The script had a couple of bugs:
 * It didn't create the required directory under variants/
 * It was treating the wildcard as literal and so couldn't
   find variant files to copy.

V.2: Drop verbose cp && fixup wild card usage.

Change-Id: Ie6f4179014b79ea45d0fcf406ca192046438dbf7
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-09-25 13:31:03 +00:00
Matt DeVillier 4721e47064 soc/fsp_broadwell_de: fix flashconsole support for platform
CB:29633 switched platform to use sb/common spi implementation,
which worked until CAR_GLOBAL was removed in CB:30506.

Revert the changes back to usage of CAR_GLOBAL in the common spi
driver so that flashconsole will work again in romsatge for
fsp_broadwell_de.

Test: verify flashconsole functional on out-of-tree Broadwell-DE board

Change-Id: I72e5db1583199b5ca4b6ec54661282544d326f0f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-25 12:56:56 +00:00
Hung-Te Lin 266c58a20b mb/google/kukui: Add new build target 'Juniper'
Add the configuration 'Juniper' for the new mainboard.

BUG=b:137517228
TEST=make menuconfig; select 'juniper' and build

Change-Id: I94e3ac7f6de3fecf177e344cb217eaecf6362d69
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-09-25 12:56:26 +00:00
Furquan Shaikh d1a4a7a7fa util/mb/google/hatch: Update kconfig.py to not select SOC_INTEL_COMETLAKE
Now that SOC_INTEL_COMETLAKE is selected by default in Kconfig,
utility to create a new variant does not need to do that anymore in
Kconfig.name

Change-Id: If68bcf14e2e0812d4f4dcb99371c65790154ff62
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-25 12:56:13 +00:00
Furquan Shaikh d6d416cc96 mb/google/hatch: Move SOC_INTEL_COMETLAKE selection to Kconfig
All variants of hatch are using Comet Lake and so the selection can be
done in Kconfig without requiring each variant to do the same.

Change-Id: Ief34296334ede5ba0f5f13381e92427ccc440707
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-25 12:56:00 +00:00
Frans Hendriks ee8ca86dd6 Documentation/vendorcode: Add Eltan to vendor index
Eltan is missing in the vendor index.

Documentation of the eltan vendorcode is availlabe already.
Add eltan to vendor index.

BUG=N/A
TEST=N/A

Change-Id: I51fe64da91499f0ea7bf97fc240f4e263470c146
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-25 12:53:07 +00:00
Werner Zeh f57b05b573 mb/siemens/mc_apl1: Sort the names of all variant mainboards
Sort the names of all variant mainboards in an ascending order.

Change-Id: I19d502298744c0e0cbc91eb836c62ca90cdb9a5c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-09-25 08:14:56 +00:00
Werner Zeh 255748ea5d mb/siemens/mc_apl{2,4,5}: Enable VBOOT
Enable VBOOT in Kconfig and provide a flashmap that includes all the
needed sections for VBOOT support.

Change-Id: I3d58094256d2730dbd249291a8f1ed8df9dfe62d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-09-25 08:14:46 +00:00
Sridhar Siricilla f35eee94bd soc/intel/(apl,skl,cnl,common): Move mkhi_hdr structure definition to common
Removed mkhi_hdr structure definition from multiple SOCs, and moved to common.

TEST=Built code for Hatch, apollolake boards.

Change-Id: Ifeba0ed4d98975049179d1b47fb22c06a927dc29
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35545
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-25 06:26:14 +00:00
Kyösti Mälkki e39becf521 intel/cpu: Switch older models to TSC_MONOTONIC_TIMER
The implementation of udelay() with LAPIC timers
existed first, as we did not have calculations
implemented for TSC frequency.

Change-Id: If510bcaadee67e3a5792b3fc7389353b672712f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34200
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-24 22:56:52 +00:00
Kyösti Mälkki c00e2fb996 cpu/intel: Use CPU_INTEL_COMMON_TIMEBASE
Change-Id: I0e7159039751a88d86b6c343be5f085e6e15570a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-24 22:56:16 +00:00
Kyösti Mälkki 52b1e2814a intel/socket_mPGA604: Enable TSC_CONSTANT_RATE
We can use intel/common implementation for tsc_freq_mhz().

Change-Id: I728732896ad61465fcf0f5b25a6bafd23bca235e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34199
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-24 19:03:57 +00:00
Kyösti Mälkki fe26be1181 cpu/intel/common: Fix invalid MSR access
Fix regression from commit ecea916

   cpu/intel/common: Extend FSB detection to cover TSC

MSR_EBC_FREQUENCY_ID (0x2c) was not defined for affected
CPU models and rdmsr() caused reset loops. Implementations
deviate from public documentation.

Change to IA32_PERF_STATUS (0x198) already used in i945/udelay.c
to detect FSB to TSC multiplier.

Change-Id: I7a91da221920a7e7bfccb98d76115b5c89e3b52e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-24 19:03:10 +00:00
Alexander Couzens be756f18df Makefile: set TZ LANG LC_ALL
To be reproducible, TZ LANG LC_ALL should be set early
in the build process to be always used.

Change-Id: Iad802968347c8d41f974af930e0d0ad5b66719cb
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-09-24 10:37:06 +00:00
Martin Roth ad84062b0d Makefile: Create the build directory before bootblock.bin
This was causing a failure when building platforms with no bootblock
when building with make -jXX

Change-Id: Ic4cd4fe8ac82bd1e9ce114dbd53763538d125af3
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-09-24 10:36:24 +00:00