Commit Graph

38671 Commits

Author SHA1 Message Date
Sridhar Siricilla f2de1e7e19 mb/intel: Enable ALC711 Audio codec over SNDW0 link
The patch enables ALC711 Audio codec.

Test=Verified on ADL RVP.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I73f480dad1047cebd7ffc66e0104ff10cacc300b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-11-07 08:55:53 +00:00
V Sowmya 73caae9772 mb/intel/adlrvp: Enable TCSS xDCI, TBT PCIe RP and DMA controllers
This patch enables TCSS xDCI, TBT PCIe root ports and DMA controllers
for ADLRVP.

BUG=b:170607415
TEST=Built and booted on ADLRVP.

Change-Id: Iabd6cc7c589d1c20cde9d66c0a63e2cf16316b33
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47288
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-07 08:55:15 +00:00
V Sowmya 14e34fb10b mb/intel/adlrvp: Configure the HPD GPIO's
This patch configures the HPD1 and HPD2 GPIO's.

BUG=b:170607415
TEST=Built and booted adlrvp. Verified the hotplug
functionality is working.

Change-Id: Ied2d4c56220212a15103e9a2fbd01ce6f0811a74
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-11-07 08:55:01 +00:00
Jonathan Zhang 9e0dd96e7e vc/intel/FSP2_0/CPX-SP: update to ww45 release and add watermark option
Intel CPX-SP FSP ww45 release annotates default values for FSP-M UPD
variables.

FSPM MemRefreshWatermark option support is present in FB's CPX-SP
FSP binary, but not in Intel's CPX-SP FSP binary. In FB's CPX-SP
FSP binary, this option takes the space of UnusedUpdSpace0[0].

For DeltaLake mainboard, if corresponding VPD variable is set, use it
to control the behavior. Such control is effective when FB's CPX-SP
FSP binary is used.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I57ad01f33b92bf61a6a2725dd1cdbbc99c02405d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-11-07 00:12:35 +00:00
T Michael Turney 7bfef7d50c sc7180: Correct mmu configuration for AOP SRAM regions
NOC errors detected at runtime in AOP SRAM region
strongly suggested speculative memory accesses were occurring
in memory regions that either don't exist or are device memory
rather than SRAM.

Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Change-Id: I6611dc614c80063c7df057b59337417c8f56fd9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-11-06 22:34:25 +00:00
Felix Held ac2da047ac soc/amd/picasso: add Raven1 GPU PCI ID
Change-Id: Id4460eb596b080dec1a63a20869182170c3388af
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-06 19:59:54 +00:00
Felix Held 53c173e9ef soc/amd/picasso/cpu: add Raven1 CPUID to CPU table
The RV1 CPUID is already in the cpu.h file, but was still missing from
the CPU table in cpu.c.

Change-Id: Iad78cbe933b40e946d421e4c93e523f9e31f1089
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-06 19:59:41 +00:00
Lucas Chen d8c189b669 zork/var/ezkinil: Adjust USB2 phy si fine tune on DVT Board
Adjust USB2 phy si setting fine tune on DVT for Ezkinil.

BRANCH=zork
BUG=b:156315391
TEST=Measuring scope timing and test usb detection

Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: Id537b6e9a17f47481b6aedcea0c6a8474d993b6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-11-06 19:23:04 +00:00
Matt DeVillier ea4db9b8fb mb/purism/librem_mini: Set unused GPIO pads to PAD_NC
Set numerous pads to PAD_NC as per board schematics (they are either
NC, or connected to test pads), and adjust comments as needed.

Change-Id: I4c2ab936256d0031d7a127fbeac42c8951a0b39f
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-06 19:09:29 +00:00
Martin Roth 5632c6bc02 soc/amd/picasso: Set vboot hashing block size to 36k
On picasso's psp_verstage, the vboot hash is being calculated by
hardware using relatively expensive system calls.  By increasing the
block size, we can save roughly 150ms of boot and S3 resume time.

TEST=Build & boot see that boot time has decreased.
BRANCH=Zork
BUG=b:169217270 - Zork: SHA calculation in vboot takes too long

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6642073357327811b415dcbcad6930ac6d2598f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46903
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-06 18:53:05 +00:00
Martin Roth 03d06d3bcd soc/amd/picasso: Up stack size to 40k for vboot hash buffer
Increasing the vboot hash buffer size greatly speeds up the SHA
calculations.  Going from a standard 4k buffer to a 36k buffer
takes ~150ms of the boot and resume time.

TEST=Build & boot see that boot time has decreased.
BRANCH=Zork
BUG=b:169217270 - Zork: SHA calculation in vboot takes too long

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibca868ad7be639c2a0ca1c4ba6d71123d8b83c92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46902
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-06 18:52:49 +00:00
Wisley Chen 1597a21326 mb/google/volteer/var/elemi: Update gpio and devicetree
Update gpio and devicetree for elemi.

BUG=b:170604353
TEST=emerge-volteer coreboot and boot into kernel

Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I5b8880d485ed73aa4e65c1249c58f02c8f0c6501
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-06 18:35:16 +00:00
Wisley Chen 4efd7d9926 mb/google/variant/elemi: config CSE LITE
Config elemi to use CSE LITE

BUG=b:170604353
TEST=emerge-volteer coreboot

Change-Id: I31c7a743645d6a34ee34e750ba92c108b306ee09
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47019
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-06 18:35:08 +00:00
Wisley Chen 5602945e9f mb/google/variant/elemi: Select USE_CAR_NEM_ENHANCED_V2 for elemi
BUG=b:170604353
TEST=emerge-volteer coreboot

Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I1a1ab6f3d57d5023523b85bfb00d48d8b70a6c1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-06 18:34:59 +00:00
Martin Roth 8839b7f109 security/vboot: Add Kconfig symbol to set hashing block size
Generally, this size probably doesn't matter very much, but in the
case of picasso's psp_verstage, the hash is being calculated by
hardware using relatively expensive system calls.  By increasing the
block size, we can save roughly 140ms of boot and resume time.

TEST=Build & boot see that boot time has decreased.
BRANCH=Zork
BUG=b:169217270 - Zork: SHA calculation in vboot takes too long

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I68eecbbdfadcbf14288dc6e849397724fb66e0b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2020-11-06 17:46:13 +00:00
Marc Jones 83729bd430 soc/intel/xeon_sp/skx: Fix MADT CPU indexes
The CPU index wasn't getting updated. Confirm MADT sets IOAPIC and CPU
ID numbers.

Change-Id: I72430cc48f4609ac408e723172ba1ed263cca8e3
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-06 17:05:30 +00:00
Marc Jones 18960ce0c9 soc/intel/xeon_sp: Move CPU helper functions
Continue Xeon-SP de-duplication.
Move CPU helper functions from skx/ and cpx soc_util.c to common util.c.
Functions only used by util.c are updated to be static.

The following functions are moved:
 int get_threads_per_package(void);
 int get_platform_thread_count(void);
 const IIO_UDS *get_iio_uds(void);
 unsigned int soc_get_num_cpus(void);
 void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits);
 void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits,
   uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread);
 void xeonsp_init_cpu_config(void);

Change-Id: I118a451b9468459cf2c2194f31da1055e1435ebe
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47170
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-06 17:00:14 +00:00
Marc Jones c6a6e54d05 soc/intel/xeon_sp/cpx: Reorder cpu.c .h includes
Clean up the header includes.

Change-Id: I9f61d1a82b37bc0ed803967dc64decf18f44adc9
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2020-11-06 16:59:33 +00:00
Zheng Bao af2efbb59b amdfwtool: Use shell command to get depend file list
The amdfwtool is not available at the beginning of the
building. So it may have error if it is missing.

Change-Id: Id4db70986755cef8e98877c4e92841b25ced5452
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-06 13:06:33 +00:00
Zheng Bao 795d73c6d8 soc/amd/picasso: Update coreboot UPD variable names to include units
Use command below to change the variable globally.

sed -i "s/\<variable\>/variable_u/g" `grep variable -rl ./ \
   --exclude-dir=build --exclude-dir=crossgcc`

BUG=b:171334623
TEST=Build

Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-06 13:02:24 +00:00
Kevin Chiu 0cae9008f0 mb/google/octopus/variants/garg: Add new LTE SKU
Add new SKU definition:
Garg360 (LTE DB,1A2C,TS, no stylus, rear camera) SKU ID - 39

BUG=b:170708728
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage

Change-Id: Ifec4e1360bd1aff3825bc6413b0a2ccd8b822075
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47015
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-06 03:11:59 +00:00
Ravi Sarawadi d83e24d9d5 soc/intel/tigerlake: Disable C1 C-state Demotion
Disable C1 C-state auto demotion to decrease SoC power usage.

When set, processor will conditionally demote C3/C6/C7 requests
to C1 based on uncore auto-demote information.

BUG=b:161215906
TEST=Measure and confirm SoC power usage reduction for key use cases
 eg 'Google Meets video call'

Measured on instrumented boards for Volteer EVT and Delbin.

Below measurements for Volteer:

Google meets with 720p 	w/ auto-demotion   w/o auto-demotion
System Power 	        13.14W	              9.4W
SOC Power 	         7.9W	              5.4W

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Shweta Malik <shweta.malik@intel.com>
Change-Id: I649cafbaf03917d76521aa5f76ec58d218e1a1b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-05 22:58:27 +00:00
Felix Held 1032d22152 soc/amd/picasso: move MAX_CPUS setting from mainboard to SoC Kconfig
Since the mainboard Kconfig is sourced before the SoC one, it would
still be possible to override this setting at mainboard level, even
though that shouldn't be needed. The maximum CPU count for Picasso is 8,
since the chips have only up to 4 cores with up to two threads each.

Change-Id: I53449b8fa73c5d13e6ea77bee6eed8896b7d3ec3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47205
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-05 19:57:14 +00:00
Karthikeyan Ramasubramanian b5d9f4a1cf ec/google/chromeec: Remove the check for Internal TypeC MUX
Integrated TypeC MUX is used only in certain SoCs and hence the missing
devicetree configuration is not an error. Remove the check for internal
TypeC MUX device and the associated debug statement.

BUG=b:172186858
TEST=Build and boot to OS in Drawlat.

Change-Id: Ieb76e1ccfd04f1628617b2665b05be6718a25f81
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-05 19:06:31 +00:00
Angel Pons ce1d588f07 mb/msi/ms7707/Kconfig: Drop invalid defaults
The PCI ID corresponds to the iGPU, which is disabled in the devicetree.
Also, the VBIOS file does not exist at the specified location.

Change-Id: I4f128d3057dc7218f32320c4e23466eb31af4e54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45672
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-05 14:17:55 +00:00
Matt DeVillier 6b495bcf16 mb/purism/librem_mini: Drop DW0/DW1 from GPIO config comments
These are generated by inteltool + intelp2m and reflect the
pad configuration of the vendor (AMI) firmware at a specific
point in time, but do not always reflect the correct configuration
of a given pad as per the schematics, so drop them.

Change-Id: Ie337cca5bc0e87a5426cceae8d7ec29ab14a1729
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47200
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-05 12:38:08 +00:00
Subrata Banik 7029665482 mb/intel/adlrvp: Add support for DDR5 memory
This patch adds DDR5 memory configuration parameters to FSP.

TEST=Able to build and boot ADLRVP with DDR5 memory.

Change-Id: I4711d66c7b4b7b09e15a4d06e28c876ec35bc192
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46485
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-05 07:29:44 +00:00
Arthur Heymans 1410224cf4 soc/intel/xeon_sp: Use common cpu/intel romstage entry
This removes some boilerplate like starting the console and also adds
a "start of romstage" timestamp.

Change-Id: Ie85df5d244fa37c41f0b3177ca325c607fa54593
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-05 00:02:07 +00:00
Angel Pons 6c49f40b6e haswell: Add Intel TXT support in romstage
Provide necessary romstage hooks to allow unblocking the memory with
SCLEAN. Note that this is slow, and took four minutes with 4 GiB of RAM.

Tested on Asrock B85M Pro4 with tboot. When Linux has tboot support
compiled in, booting as well as S3 suspend and resume are functional.
However, SINIT will TXT reset when the iGPU is enabled, and using a dGPU
will result in DMAR-related problems as soon as the IOMMU is enabled.

However, SCLEAN seems to hang sometimes. This may be because the AP
initialization that reference code does before SCLEAN is missing, but
the ACM is still able to unblock the memory. Considering that SCLEAN is
critical to recover an otherwise-bricked platform but is hardly ever
necessary, prefer having a partially-working solution over none at all.

Change-Id: I60beb7d79a30f460bbd5d94e4cba0244318c124e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-04 23:53:51 +00:00
Angel Pons 35597435d0 mb/purism/librem_cnl: Set SaGv to FixedHigh
Since the Librem Mini does not run on battery power, SaGv has little
benefits and noticeably slows down testing, since memory training is
run twice. Disabling SaGv cuts the 30-second cold boot time in half.

Change-Id: Ib02e42dcb4f20fdbdca85456c0dceafc59c782d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-11-04 23:47:09 +00:00
Angel Pons 5725ee4f9f sec/intel/txt: Add support for running SCLEAN in romstage
SCLEAN has specific requirements and needs to run in early romstage,
since the DRAM would be locked when SCLEAN needs to be executed.

Change-Id: I77b237342e0c98eda974f87944f1948d197714db
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-04 23:31:11 +00:00
Angel Pons 527647677a sb/intel/lynxpoint/acpi/gpio.asl: Simplify constants
Only LPT-LP includes this file, so `ISLP` is effectively constant. Thus,
eliminate some unnecessary if-blocks, since only one branch gets taken.

Change-Id: Ie8ba787bf5c021845e1e47256a6303697aa97fe1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46776
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 23:22:04 +00:00
Angel Pons df7a887cb5 sb/intel/lynxpoint: Align LP GPIO ACPI with Broadwell
Move the `GWAK` method into the GPIO device, and have lpc.c include the
LP GPIO code. All usages of `GWAK` on mainboards need to be updated.

Change-Id: Id6a41f553d133f960de8b232205ed43b832a83d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46775
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 23:21:44 +00:00
Angel Pons b0d342028d sb/intel/lynxpoint/acpi: Put together LP GPIO code
Rename `lpt_lp.asl` and place all Lynxpoint-LP GPIO ASL there. It has
been named `gpio.asl` to ease diffs between Lynxpoint and Broadwell.

Tested with BUILD_TIMELESS=1, Google Panther does not change.

Change-Id: I7cc4ab3371014be783761f110542471a8c0157a3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46774
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 23:21:36 +00:00
Angel Pons aacabd0bd6 soc/intel/broadwell: Merge `device_nvs.asl` into `globalnvs.asl`
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change.

Change-Id: If5f1feb0cd43fe1e0514b4e3fa766da60e2b7603
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46773
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 23:21:29 +00:00
Angel Pons 040f3be59e soc/intel/broadwell: Include EC and IRQ links ACPI early
Other southbridges such as Lynx Point do it. This eases merging later.

Change-Id: I10196bbc44ce859c2747755845378351f45944ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46766
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 22:59:42 +00:00
Angel Pons a42d37ac3f sb/intel/*/acpi/lpc.asl: Drop unnecessary RCBA offset
Nothing should be using this offset.

Change-Id: Ia4736471e2ac53bec18bfe073f4aa49e3fc524a8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46765
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 22:58:40 +00:00
Angel Pons 9f8e92bae3 sb/intel/lynxpoint: Expose full LPC device ID in ACPI
This is merely to align ACPI files with Broadwell. It is unused.

Change-Id: I8aa297bd3c3734bbd438ff84742aadfc661adcf7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46764
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 22:58:25 +00:00
Angel Pons 34c0b26193 soc/intel/broadwell/pch: Use common PCIe ACPI code
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change.

Change-Id: I1f41ce943e25dceab79c7d7ee2ed797c392dcd52
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46763
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 22:45:20 +00:00
Angel Pons fcc26f54a0 soc/intel/broadwell/pch/acpi: Add PCIe register offsets
These are present in common southbridge ACPI code, and also exist on
Broadwell. Thus, add the definitions to align with common ACPI code.

Change-Id: Ib0ad9da80920fe7c70986e541c50f6adccb49d0c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46761
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 22:38:56 +00:00
Angel Pons 257b00f357 soc/intel/broadwell/gma.c: Align struct with Haswell
Change-Id: Ifd1fb02497e1d326b6b9c5752f471f52b145a8ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-04 22:37:58 +00:00
Angel Pons 2ac4cc6595 sb/intel/common/acpi/pcie.asl: Generalise file comment
This file is no longer specific to 6 and 7 series PCHs.

Change-Id: Ib89378bd6ba1d80281b92a79d37b9fdeaaed40fb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46762
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 22:07:50 +00:00
Angel Pons f1e81e6eb9 sb/intel/common/acpi/irqlinks.asl: Clean up cosmetics
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I8562fc3278144380b0ab842d88176114821be823
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46760
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 22:07:28 +00:00
Angel Pons eeefb022eb soc/intel/broadwell: Use common irqlinks.asl
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I9179c1b449925cc66628fc3266652b8237ab49e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46759
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 22:06:47 +00:00
Angel Pons 284b39f9c8 soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs
Commit 2e1f764 (sb/intel/common/acpi/irqlinks.asl: Add missing IRQs)
added these IRQs for Lynx Point and earlier southbridges. Follow suit
for Broadwell, since it also supports them. Vendor firmware of the Asus
X555LAB laptop also contains these IRQs, as per the disassembled DSDT.

Change-Id: If857352dd25ba61c1f09c1ff4358efafdc3a5c73
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46758
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 22:03:32 +00:00
Angel Pons 0d8924d880 soc/intel/broadwell: Align ACPI with Haswell/Lynxpoint
Drop unnecessary smbus.asl in favor of southbridge common code.

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change.

Change-Id: I13b35d2155a2cede0a56846b8bf8a79d4ebfc7b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46757
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 22:03:18 +00:00
Angel Pons f239b5a9f3 nb/intel/haswell: Place CTDP ASL code in a separate scope
This is just to align the code with what Broadwell does.

Change-Id: I52fb1546d049ca9fa09d0c54304ca1d79f6c4c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46756
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 22:03:03 +00:00
Angel Pons c5381e0f36 nb/intel/haswell/acpi: Align with Broadwell
Align cosmetics and move CTDP-specific ASL into its own file.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.

Change-Id: I476a4e01016caa3658177b0fa8916576f4a5e0e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46755
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 22:02:46 +00:00
Matt DeVillier 4727663931 mb/purism/librem_mini: Drop community comments in GPIO config
These add nothing useful to the GPIO config

Change-Id: Ieecc9bd67d020e141c3a1f1d387034df5e563068
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47190
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 21:22:29 +00:00
Matt DeVillier aa11f9a826 mb/purism/librem_mini: Update GPIO config
Update GPIO config using a fresh dump of inteltool from the
vendor (AMI) firmware on a Librem Mini v2, run through intelp2m
with parameters '-p cnl -n -ii'

Change-Id: I747415fb9ab7b21943d256d248729cb9e2b4b945
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47206
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 21:19:19 +00:00