Commit graph

356 commits

Author SHA1 Message Date
Angel Pons
cfe1016883 mb/**/dsdt.asl: Remove outdated sleepstates.asl comment
Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.

This follows commit 408d1dac9e.

Change-Id: I0c0f4ad8bf743010ebdd2d53fcf297aeab64a662
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-02 11:51:23 +00:00
Angel Pons
59e7a43f9a mb/**/dsdt.asl: Remove "Some generic macros" comment, again
It provides no useful information, so it might as well vanish.

This follows commit 0142d441c6.

Change-Id: Iad41d8d39c6712cebfa5245f37bc69061b5ac552
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-02 11:51:06 +00:00
Edward O'Callaghan
2f55726609 mainboard/google/volteer: Migrate onto SKU ID helpers
Leverage the common sku id space helper encoders.
volteer uses the non-legacy SKU ID space.

BUG=b:149348474
BRANCH=none
TEST=only tested on hatch

Change-Id: Ic66908afb7abb34527b4177cfd07f03ad718317c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-28 14:27:00 +00:00
Paul Fagerburg
1e7da75b77 volteer: allow empty SPD_SOURCES
Some Volteer variants might not use SPD files. Allow SPD_SOURCES in
spd/Makefile.inc to be empty.

BUG=None
BRANCH=None
TEST=Build coreboot and see that it builds without error

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I5a8231b999e16503867d3c8df571b11fa0c1f6a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-18 14:53:47 +00:00
Nick Vaccaro
75f0124c44 mb/google/volteer: use new Tiger Lake memory config
Some of the common memory code that was being performed in
mainboard has moved into the soc to reduce redundant code.
This change adapts volteer to use Tiger Lake's new common code.

BUG=b:145642089, b:145238504, b:145564831
BRANCH=none
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer, boot to kernel, "cat /proc/meminfo" and verify it reports
"MemTotal:        8038196 kB".

Change-Id: I32c9b8a040728d44565806eece6cf60b6b6073b6
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-11 07:52:47 +00:00
Nick Vaccaro
f978191b64 mb/google/volteer: add volteer mainboard initial support
Created a new Google baseboard named volteer from scratch.

BUG=b:142961277
BRANCH=master
TEST="emerge-volteer coreboot" compiles successfully.

Change-Id: I03a13f3df4e819ab9cf63ad69867c807d2a1b651
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09 19:26:23 +00:00