Commit Graph

6 Commits

Author SHA1 Message Date
Karthikeyan Ramasubramanian 0b4f49c792 util/spd_tools/spd_gen/lp5: Remove maxSpeed for Sabrina
Firmware component that does memory training already limits the memory
controller to train at 5500 Mbps for all memory parts in Sabrina. Hence
removing this interim SPD change to limit the speed.

BUG=b:238074863
TEST=Build and boot to OS in Skyrim.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I2bc82c7407a97aac282708c3e0bd56ae99a8fc31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66290
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01 20:30:39 +00:00
Karthikeyan Ramasubramanian d5ea355c73 util/spd_tools: Limit memory speed to 5500 Mbps for Sabrina
In Sabrina platform, memory speed is limited to 5500 Mbps. Update the
SPD generation tool to limit to that speed.

BUG=b:238074863
TEST=Build and boot to OS in Skyrim.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ie3507898167012e0d812c9b1aacba72e9055fcd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-19 15:11:53 +00:00
Karthikeyan Ramasubramanian f53214677c util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)
ADL encodes CK cycle time as tCKMin whereas Sabrina encodes WCK cycle
time. Encode tCKMin as per the respective advisories.

BUG=None
TEST=Generate the SPD and ensure that tCKMin is encoded accordingly.
Minimum CAS Latency time is also impacted and is encoded accordingly.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-08 23:46:50 +00:00
Karthikeyan Ramasubramanian e1d6f5b80d util/spd_tools/spd_gen/lp5: Encode Bank Architecture
ADL supports 8B Bank Architecture, whereas Sabrina supports either BG or
16B Bank Architectures depending on the speed. This influences SDRAM
Density and Banks, SDRAM Addressing bytes in SPD. Encode them as per the
individual SoC advisories.

BUG=b:211510456
TEST=Generate SPDs for Sabrina.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ic854ccccb2b301e75d0f28cd36daf87fd41e07e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-17 21:43:29 +00:00
Karthikeyan Ramasubramanian 3248db0e5a util/spd_tools/spd_gen/lp5: Encode Optional SDRAM features
ADL and Sabrina provide different advisories to encode Optional SDRAM
features (byte indices 7 & 9). Encode those bytes as per the respective
advisories.

BUG=b:211510456
TEST=Generate the SPD binaries for Sabrina.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Icac8ae148458162768a919d9690d7bf96734e6c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-17 21:43:10 +00:00
Karthikeyan Ramasubramanian 876cfe0ee2 spd/lp5: Generate initial SPDs for Sabrina SoC
Mainboards using Sabrina SoC will be using LP5 memory technology.
Generate the initial set of SPDs for the existing LP5 memory parts.

BUG=b:211510456
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-10 12:50:19 +00:00