Commit Graph

14328 Commits

Author SHA1 Message Date
Yunzhi Li aa33609d28 libpayload: usb: dwc2: support interrupt transfer
dwc2 host core do not have a periodic schedule list, so try to send
an interrupt packet in poll_intr_queue() function and use frame
number read from usb core register to calculate time and schedule
transfers.

BUG=None
TEST=Tested on RK3288 with two USB keyboards(connect to SoC without
USB hub), both work correctly.
BRANCH=None

Change-Id: I16f7977c45a84b37c32b7c495ca78ad76be9f0ce
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3d0206b86634bcfdbe03da3e2c8adf186470e157
Original-Change-Id: Ie54699162ef799f4d3d2a0abf850dbeb62417777
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/280750
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: http://review.coreboot.org/10774
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:40:02 +02:00
Daisuke Nojiri 394933640b libpayload: arm(64): add read8/16/32 and write8/16/32
This applys the same change made by
https://chromium-review.googlesource.com/261692
to libpayload.

BUG=none
BRANCH=tot
TEST=built for veyron_jerry, rush_ryu, samus

Change-Id: I26dd66d79cd1559a7852b3c9d252420f2fed5fa0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d0d6f70aa805e18966e80618fbf9e9605274b030
Original-Change-Id: Ib0c199238f8fa58643d51782b17550dbd0d9ebd7
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282541
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:39:48 +02:00
huang lin c2b48e55f1 rockchip: rk3288: correct ddr 300MHz clock setting
CRU request (24MHz * nf) / nr > 440MHz, but now ddr 300MHz
setting can't meet this request, so modify it

BRANCH=None
BUG=None
TEST=Set ddr frequency to 300MHz and boot from mickey

Change-Id: I00324f5864f5ce8c1a3768268e402e0beca214c6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3d292b67245e714cb03ed35ee28c9b838d514da5
Original-Change-Id: I885704542293ed55e429a0b4b30135af7978990f
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/282445
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:39:38 +02:00
David Hendricks a1e5a7761a veyron_danger: EDP changes for v2
EDP-related hardware modifications for v2:
- BL_EN moved from GPIO7_A3 to GPIO7_A2
- EDP_HPD added to GPIO7_B3

BUG=none
BRANCH=none
TEST=built and booted Danger v2 with EDP panel attached, saw dev
mode screen come up

Change-Id: I47383610082b371a612aced656e56f1bd1cfa098
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fb939ff17cca7bbd24aabfdb3cbd444696a5a845
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Id271cdcfcde6fa84c1bb707b9842bddd77a7121b
Original-Reviewed-on: https://chromium-review.googlesource.com/280855
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10771
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:39:25 +02:00
Yunzhi Li d8a3ed49a5 libpayload: udc: dwc2: support force_shutdown() routine
Add force_shutdown() routine for dwc2 udc driver to support
disconnect and reconnect case when fastboot receiving data.

BUG=chrome-os-partner:41687
BRANCH=None
TEST=None

Change-Id: I9ec204d8b7088cfafd3164c9779a6fd85d379dba
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9238f87c065ba8a57bfb4a7e65fd1821ff2922f9
Original-Change-Id: I1e584aaf19efa14409bdfa26039c27fa7034b5f0
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/281130
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-Commit-Queue: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: http://review.coreboot.org/10770
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:39:14 +02:00
Jonathan A. Kollasch 2c2e05ad79 nvidia/l1_2pvv: whitespace: remove spaces that are followed by tab
Change-Id: Ia84df2f4467e102fd5f675dba6432996584d78c1
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10796
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2015-07-05 04:32:23 +02:00
Martin Roth df02c338ef Kconfig: Fix references to obsolete symbols
These are all Kconfig symbols that have been removed or renamed.

USE_PRINTK_IN_CAR was removed in commit 8c4f31b3
Drop the USE_PRINTK_IN_CAR option. It's a bogus decision...

DYNAMIC_CBMEM was removed in commit e2b0affd
Remove Kconfig variable that has no effect

MAINBOARD_HAS_BOOTBLOCK_INIT was removed in commit 342535cc
Remove Kconfig variable that has no effect

CACHE_ROM was removed in commit 4337020b
Remove CACHE_ROM.

SMM_MODULES was removed in commit 44cbe10f
smm: Merge configs SMM_MODULES and SMM_TSEG

INCLUDE_MICROCODE_IN_BUILD was removed in commit eb73a218
soc/fsp_baytrail: Fix use of microcode-related Kconfig variables

CAR_MIGRATION was removed in commit cbf5bdfe
CBMEM: Always select CAR_MIGRATION

REQUIRES_BLOB was removed in commit 70c85eab
build system: Retire REQUIRES_BLOB

CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit
66e0c4c8 - cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS

CONSOLE_SERIAL_UART was renamed to CONSOLE_SERIAL in commit afa7b13b
uart: Redefine Kconfig options

CONSOLE_SERIAL8250MEM was renamed to DRIVERS_UART_8250MEM in commit
afa7b13b - uart: Redefine Kconfig options

Change-Id: I8952ca8c53ac2e6cec5f9c77d2f413f086bfab9d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10766
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-04 23:41:05 +02:00
Patrick Rudolph 8c2f39714f intel raminit: rename register
Found while doing code review.

Rename reg_4004_b30 to cmd_stretch.
Found in 4th-gen-core-family-desktop-vol-2-datasheet.pdf chapter 4.2.1.

Change-Id: Ib07059625ed458332708562e836803f2b587d5d8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10789
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-07-04 23:40:22 +02:00
Patrick Georgi ddb8f80894 buildgcc: Deal with gmp on 32bit Linux on 64bit CPUs
GMP is overeager to detect 64bit ABIs even if the entire running codebase is
32bit (but on a 64bit CPU). Enforce a 32bit build in that situation.

Change-Id: I23e9e57f3c8b0e3ad2e4e1e3eb106f7830aa76a1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/10792
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-04 23:39:34 +02:00
Patrick Georgi 8d7b719c0e xcompile: ask for compiler runtime using appropriate CFLAGS
xcompile keeps two CFLAGS around now, for GCC and CLANG. Normally they're not
required to request the libgcc/compiler-rt path, but with the multilib capable
x86_64-elf target it's required to make it pick the right libgcc when used as
i386-elf builder.

Change-Id: I700e7aa5783dc36698dd2ab8a38642a144e80fe9
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/10795
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-07-04 23:37:01 +02:00
Patrick Georgi 630ad918d4 crossgcc: Fix binutils for aarch64
The gold linker didn't build.

Change-Id: I93c26a7715e781b001a71978d8fadbf65fdfe427
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/10791
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-07-04 09:33:05 +02:00
Kimarie Hoot caa599507f hp/pavilion_m6_1035dx: Remove 'select USBDEBUG_IN_ROMSTAGE'
Since USBDEBUG is not selected by this platform, there is no
benefit to selecting USBDEBUG_IN_ROMSTAGE in the mainboard
Kconfig.  Further, using a 'select' for USBDEBUG_IN_ROMSTAGE
prevents the value from being modified by a user in menuconfig.

Change-Id: I67b71a724a8614882cff4bb43b042f0c092d11d2
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/10671
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-03 22:34:33 +02:00
Martin Roth 45895f1e7d Kconfig whitespace cleanup: Change leading spaces to tabs
Change-Id: Icab6bd9f55f086da7b51ae463f34e29366d50e1a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10764
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-03 22:30:10 +02:00
Martin Roth ac83367a7b SeaBIOS: Change clean to just 'rm -rf seabios/out'
When running 'make clean' if the seabios directory is present, we get
warnings about not having IASL installed or that the C compiler can't
be executed.  It fails to actually run the clean because we're not
correctly passing in the toolchain.

Just do what the SeaBIOS clean does directly and delete the 'out'
directory without actually calling the SeaBIOS clean.

Here were the previous warnings:

% make clean
Unable to execute the C compiler ().

Please install a working compiler and retry.
Makefile:104: *** "Please upgrade the build environment".  Stop.

or

% make clean
The SeaBIOS project requires the 'iasl' package be installed.
Many Linux distributions have this package.
Try: sudo yum install iasl
Or: sudo apt-get install iasl

Please install iasl and retry.
Makefile:106: *** "Please upgrade the build environment".  Stop.

Change-Id: Ice41376bc242f1f622d849e7628f8a9b6ef47404
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10655
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-03 20:12:15 +02:00
Stefan Reinauer 2ba16dbd99 storm: Enable DRIVER_UART since we use CONSOLE_CBMEM_DUMP_TO_UART
This fixes the build with CONSOLE_CBMEM_DUMP_TO_UART.

Change-Id: Ibe79239c5799a5c4a08ed195fce4d0c63d629ca4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10769
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-03 19:38:09 +02:00
Patrick Georgi 885ec48b95 libpayload: update xcompile script
Copy from coreboot. at some point it probably should just reuse coreboot's
version.

Change-Id: Iee905a9060983ff85e2e70bde69a221c64a07cbc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10756
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-03 09:38:18 +02:00
Stefan Reinauer 417f16bc75 tegra124: verified boot fixups
This patch fixes up verified boot (vboot2) configuration of all
tegra 124 bases boards in the tree.

Change-Id: I81f2e83821cbfdbe2a55095543e7447efdde494e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10761
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-02 19:56:18 +02:00
Stefan Reinauer a3aa8da2ac sandy/ivybridge: use LAPIC timer in SMM
This fixes an issue with using the flash driver in SMM for writing
the event log through an SMM call.

Change-Id: If18c77634cca4563f770f09b0f0797ece24308ce
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10762
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-02 08:34:40 +02:00
Stefan Reinauer cdf8ee6071 purin: chromeos.c also needed in romstage
Otherwise the Chrome OS build won't succeed.

Change-Id: Idf93a09f53d08b6c201f1de140f0fff35f928dcc
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10760
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-07-02 03:01:24 +02:00
Stefan Reinauer cecabc19a5 ME/IFD binaries: Implement sane defaults for file paths
Change-Id: I81298aca07c18359e8e4bf5b2d8926d6b45a30c5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10763
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-07-02 03:01:00 +02:00
Martin Roth 57eff2a192 ifdfake: Add prompts and help for the regions in Kconfig
Update the ifdfake region questions in Kconfig with help descriptions
and prompts to allow values to be entered and not just use pre-defined
default values.

Change-Id: Ifdffadc3d74ec49492c2ded66623a1be6945425f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10649
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02 02:26:45 +02:00
Martin Roth 775d50828e Intel Firmware Descriptor: Add Lock ME Kconfig question
Add the Kconfig question to allow the user to lock the ME section
using ifdtool.

Change-Id: I46018c3bc9df3e309aa3083d693cbebf00e18062
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10648
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02 02:26:21 +02:00
Martin Roth c407cb97bc Move baytrail & fsp_baytrail to the common IFD interface.
- Add the common/firmware subdir to the baytrail & fsp_baytrail
makefiles and remove the code it replaces.
- Update baytrail & fsp_baytrail Kconfigs to use the common code.
- Update the IFD Kconfig help and prompts for the TXE vs ME.
- Whittle away at the CBFS_SIZE defaults.  All the fsp_baytrail
platforms have their own defaults.

Change-Id: I96a9d4acd6578225698dba28d132d203b8fb71a0
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10647
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02 02:21:33 +02:00
Martin Roth c528c2e3e9 Intel Firmware Descriptor Kconfig: remove USES_INTEL_ME
When I added the common IFD Kconfig and Makefile, My thinking was that
I could use this symbol to differentiate between the ME and the TXE,
and to exclude the ME questions from platforms that use the IFD, but
don't use an ME, like Rangeley.  In practice this made things a lot
more complicated and isn't worth it.

Change-Id: I4428744e53c6bb7fc00a4fa4f0aa782c25fc9013
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10678
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02 02:17:27 +02:00
Stefan Reinauer 0ab2b25f01 coreinfo: use coreboot's kconfig
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I99e612dca3c2e5678d43b3e85eaf2f51d8f693e7
Reviewed-on: http://review.coreboot.org/10715
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-01 23:39:35 +02:00
Stefan Reinauer ca7794854c tegra132: adjust vboot2 memlayout to make coreboot compile
romstage didn't fit in it's region anymore.

Change-Id: I5a2f41cb0e0a87339dbf61906ee2060e132cc394
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10759
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-07-01 23:37:11 +02:00
Patrick Georgi 0232549621 google/veyron_minnie: Add new board
Copied from speedy, with changes to mainboard.c (and speedy -> minnie renames
across the directory)

Change-Id: Ib38f0b15da8306984869e7ee7b4ddf366b0df82c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10757
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-07-01 23:05:28 +02:00
Stefan Reinauer e559536daa libpayload: always compile with -ffunction-sections
Always compile with -ffunction-sections and -fdata-sections

This does not hurt, and it allows the linker to produce much
smaller binaries in some circumstances.

Change-Id: Ibf9f24c210d6d2ed40451b4cf0d68ce88220bc5f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10750
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-01 22:07:48 +02:00
Patrick Georgi ec88681ca3 nvidia/tegra210: Drop unused Kconfig symbol
The deleted symbols aren't used anywhere in the coreboot tree and come from
the downstream chromeos-2013.04 branch.

Change-Id: I0ebc2936dff400cf8fe68794c86ac583aba2a14b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10752
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-01 22:03:39 +02:00
Patrick Georgi 6a02b3b3e4 linker scripts: Fix symbol handling for pre-RAM cbmem console
Some ld versions (eg. the one used in the chromium build system) mis-handled
the redefined symbol in romstage.ld, so use the feature that exists for
precisely that purpose.

Change-Id: I184310ab20a02f6b3d569798448eac78b13e88a3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10754
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-01 22:03:21 +02:00
Patrick Georgi 20864c1d6d rockchip/rk3288: Initialize CPU in bootblock
Some basic MMU setup is required to allow unaligned memory accesses that
happen across our entire codebase.

Change-Id: If5a84e19a7a3e47d6009fd073b1323dfb25e6a06
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10753
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-07-01 21:43:39 +02:00
Stefan Reinauer 088c1894f8 libpayload: Fix compilation on ARM with GDB enabled
Without this, gdb_enter() is not defined.

Change-Id: I067dce371ee817d6ac77387fcbe42a9a7deb6438
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10755
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-07-01 20:55:29 +02:00
Stefan Reinauer 909b916e56 libpayload: Keep stack boundary small on x86
There is no measurable performance impact, but
this positively impacts the memory used by payloads.

Change-Id: Ib2bdba4a7bf2a4c2391a20b3225bbb44422d3194
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10751
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-01 20:55:18 +02:00
Stefan Reinauer d0ed7eef74 tegra210: Include correct include files
Some include files were unnecessary, and program_loading.h
was missing.

Change-Id: Ief3d970af5fbbb6b79da06ba3ea1d8613bfc314f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10749
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-07-01 20:18:21 +02:00
Stefan Reinauer 04fb7a81c1 coreinfo: Use IS_ENABLED() to query Kconfig variables
This will make the code work with the different styles
of Kconfig (emit unset bools vs don't emit unset bools)

Roughly, the patch does this, and a little bit of fixing up:

perl -pi -e 's,ifdef (CONFIG_.+?)\b,if IS_ENABLED\($1\),g' `find . -name *.[ch]`
perl -pi -e 's,ifndef (CONFIG_.+?)\b,if !IS_ENABLED\($1\),g' `find . -name *.[ch]`

Change-Id: Ia461a33541f58ff39e984119c44ece7e6c05608a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10713
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-01 00:36:36 +02:00
Patrick Georgi d13fd1b013 nvidia/tegra210: reserve more room for the romstage in vboot builds
Change-Id: I11c2e270179c54af8687435ff662a509ac714505
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10733
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-06-30 22:13:04 +02:00
Patrick Georgi e3fe4e7572 google/foster: roll up fixes to compile with vboot
Change-Id: I796e0fa64f9a858a54b09a82fbec1f0576e7e124
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10732
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-06-30 22:06:45 +02:00
Patrick Georgi 84a124de6b google/smaug: roll up fixes to compile with vboot
Change-Id: I256410ff6c0107bbbaaf49b909d63ca61e88a22c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10731
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-06-30 22:06:42 +02:00
Stefan Reinauer 17dd74cf45 coreinfo: Drop local Kconfig copy
Change-Id: Ice29e63149b97de1b943b3655b984b0ce13a42ba
Reviewed-on: http://review.coreboot.org/10714
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-30 21:59:42 +02:00
Patrick Georgi 4d6ad838e7 google/smaug: add new mainboard
This is an nvidia t210 based board.
This includes Chrome OS downstream up to Change-Id: Ic89ed54c.

Change-Id: I4d77659f4f2d21b1bbdcfc3467e1a166c02ddd47
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10635
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:47:22 +02:00
Patrick Georgi fd49d6faf9 google/foster: add new mainboard
This is an nvidia t210 based board.
This includes Chrome OS downstream up to Change-Id: Ic89ed54c.

Change-Id: I8630e86a4b0e8756693f8989ce147d6d762cefe1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10634
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:47:12 +02:00
Stefan Reinauer b12a448c97 kconfig: Fix defconfig targets
The syntax of "conf" has changed, but we never adapted
our Kconfig Makefile since we are not typically using those
targets (except for coreinfo)

Change-Id: Ib95b53d255d7456cc6d6bcc7048fcaa0db1ce142
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10716
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-30 21:45:50 +02:00
Patrick Georgi 40a3e321d4 nvidia/tegra210: add new SoC
This includes Chrome OS downstream up to Change-Id: Ic89ed54c.

Change-Id: I81853434600390d643160fe57554495b2bfe60ab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10633
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:43:01 +02:00
Patrick Georgi 7f641e68f2 google/peach_pit: disable Chrome OS support
The Exynos SoC code and vboot really don't get along and things are not even
in a good shape in Chrome OS' top of tree. Disable but don't rip out the
support functions, so it could be revived.

Change-Id: I982c5a3731b527fd1f1579e9de353819da656452
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10730
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:35:00 +02:00
Patrick Georgi 3756de0762 google/nyan: remove timestamp leftovers from upstreaming
Initializing timestamps and writing the "start romstage" timestamp already
happens earlier.
One question to sort out is what to do about the migration into cbmem, but at
least this compiles again.

Change-Id: Ie8a0b7998c6c9da71f036857987f3c781385034f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10729
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:34:39 +02:00
Patrick Georgi 78390f1303 drivers/i2c/tpm: move tpm driver around a bit more.
The many different places to put vboot support in can be confusing.
Instead of using libverstage (which isn't enough since those functions are
sometimes called outside that, too), mention all stages where it can resides
explicitly.

Change-Id: Idddb9f5e2ef7bcc273f429d9f432bd37b4573567
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10728
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:34:19 +02:00
Patrick Georgi 2f31ef1115 google/link: implement get_write_protect_state
Current vboot wants that function.

Change-Id: I9d3a592c448cf2af10f76cae4518341cbc0a6f41
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10727
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:34:05 +02:00
Patrick Georgi 94b8ad4879 samsung/stumpy: implement get_write_protect_state
Current vboot wants that function.

Change-Id: Ie3b49aa716d9711223ec71a142878e847eedfe4e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10726
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:33:48 +02:00
Patrick Georgi 961e8a46af samsung/lumpy: implement get_write_protect_state
Current vboot wants that function.

Change-Id: I08590739112a7fcce7a983b6d77ff500692ef7d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10725
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:33:36 +02:00
Patrick Georgi 03decc0c5e intel/sandybridge: initialize variable
Otherwise cache_base may be uninitialized.

Change-Id: Ie91f9567cea24114723a5362f52052d6ec22a6b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10724
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30 21:33:27 +02:00