Commit Graph

39334 Commits

Author SHA1 Message Date
Kyösti Mälkki 81b8472237 ACPI: Drop redundant CONSOLE_CBMEM setup in GNVS
Already done from common gnvs_get_or_create() implementation
after gnvs_cbmc_ptr() is defined.

Change-Id: I77c292cd9590d7fc54d8b21ea62717a2d77e5ba4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48702
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 11:16:26 +00:00
Kyösti Mälkki 3139c8dc05 ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocations
Allocation now happens prior to device enumeration. The
step cbmem_add() is a no-op here, if reached for some
boards. The memset() here is also redundant and becomes
harmful with followup works, as it would wipe out the
CBMEM console and ChromeOS related fields without them
being set again.

Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10 11:15:10 +00:00
Felix Singer fb777b5da8 mb/google/parrot: Replace while-loop with do-while
Fixes linter error complaining about trailing semicolon.

Change-Id: I3f74f25cb2e3edcdd509abd86d80098241c05741
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-09 16:31:29 +00:00
Felix Singer 57ef7c37d8 mb/google/parrot: Let else statement follow closing brace
Fixes a linter error.

Change-Id: I1302e32b0d52e37d9cb4503128edc7d1df1c3bd8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-09 15:22:37 +00:00
Felix Singer 81ffd00856 mb/google/parrot: Get rid of hard-coded function names in printks
Instead of hard-coding function names in strings, use the __func__
constant for better maintainability.

Change-Id: I151560cd5a135e00f494eda3f9d3b592ee9d984a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-09 15:22:11 +00:00
Felix Singer 98b51f4cf9 mb/google/parrot: Fix spacing issues
Add a space after each comma to fix linter issues.

Change-Id: I5533c4fc7aa0e986da4350ec56b84903b3111a07
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-09 15:20:52 +00:00
Felix Singer 32d893bfbb mb/hp/pavilion_m6_1035dx: Replace leading spaces with tabs
Replace leading spaces with tabs so that linter doesn't complain. Also,
remove an unneeded empty line.

Change-Id: I5809c1ca13782393cb4c4051a7061186c1c144e4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-09 15:20:38 +00:00
Felix Singer a4ee796115 mb/hp/pavilion_m6_1035dx: Replace (foo*) with (foo *)
Change-Id: Iff38caf5f4a4d25f4bafdd821c51de24f54e3ce5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-09 15:20:05 +00:00
Felix Singer c299123608 mb/hp/pavilion_m6_1035dx: Put opening braces in previous line
Put opening braces in previous line to fix linter errors.

Change-Id: I7bd49393056f80ce4f6078c646db46c2a67f2381
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49234
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-09 15:19:53 +00:00
Felix Singer 5ad019b092 mb/hp/pavilion_m6_1035dx: Remove trailing semicolon from macro
Macros should not use a trailing semicolon.

Change-Id: Ibbcd589c7afa72e9e468e5f4b557bb2c665bbec0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-09 15:19:14 +00:00
Felix Singer 21dd4793b4 mb/hp/pavilion_m6_1035dx: Fix spacing issues in mptable.c
Align the bytes of picr_data[] and intr_data[] with 8 bytes per line and
add spaces after commas so that the linter doesn't complain.

Also, remove spaces before the postfix '++' operator.

Built with BUILD_TIMELESS=1, coreboot.rom remains the same.

Change-Id: I90bec7fdfabca6f8afd1508c673241e0742e2ee9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49191
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-09 15:18:59 +00:00
Felix Singer 21106e3505 vc/intel/fsp1_1/skylake: Remove unused header file
Change-Id: I329a1484cbd16296a2aa047876c2506c74d4452d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-09 14:45:02 +00:00
Felix Singer 7722dc32d1 mb/asrock/h110m: Drop VR configuration from devicetree
Drop VR configuration since it matches the platform defaults.

Change-Id: I92007f4ff9d093c9573bb1ee13e64eb2f38af4f4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-09 14:44:13 +00:00
Felix Singer 5b256dfad6 mb/asrock/h110m: Remove zeroed options from devicetree
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.

Change-Id: Ic39b4c70ccb9ec21780c937322d63820064abbd1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49185
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-09 14:43:35 +00:00
John Zhao 9c1a335fbc mb/google/volteer: Configure Delbin USB2 ports for Type C
Two USB2 ports 4 and 9 are assigned to type C connectors on Delbin
board. This update configures these USB2 ports for Type C which will
allow USB2 port reset message upstream from PCH to CPU to recover a USB3
device that downgraded to USB2 to upgrade back to USB3.

BUG=b:176575892
TEST=Booted to kernel on Delbin board and verified usb2 port reset
message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE
where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4.
Validated various USB3 devices enumeration.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Idb3ce949e1ecf3adc7615e0af79a38a0cc9be18f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49202
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 22:01:26 +00:00
Felix Held e862a004d7 util/amdfwtool,post: add missing distclean target
Without this target some spurious errors occurred when running make
distclean at the top level of coreboot.

Change-Id: I3d3061b386fc5b4a043cfc7ff8fd3c0da33c0e83
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49227
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 21:10:51 +00:00
Felix Held f9608cd8f4 soc/amd/picasso: add missing GNB I/O APIC initialization
Change-Id: Iddb0c20e769e6921ba5d0dd4a84ab9e494d522e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48269
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 15:18:18 +00:00
Marshall Dawson 663c17c78d amd_blobs: Advance pointer for picasso FSP 0x25
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I2aa5f353432cd8f79005153a06ac35c1e654f6f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-08 15:18:07 +00:00
Marco Chen 07c80b2164 mb/google/octopus: add audio codec into SSFC support for Bobba
BUG=b:174118027
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.

Signed-off-by: Marco Chen <marcochen@google.com>
Change-Id: Id37c4c5716ade0851cfcb24e12b390841e633ac9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2021-01-08 14:29:31 +00:00
Tzung-Bi Shih 3f80a7aa6d mb/google/asurada: Support audio
- Turns audio-related things power on.
- Selects I2S pin-muxing.
- Exposes GPIO "speaker enable" for switching on and off.

BUG=b:176856418

Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: If595657bbddad85bc9a154b3648bae1190cb00b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-08 08:31:32 +00:00
Seunghwan Kim 3436bb03f6 mb/google/dedede/var/sasuke: Add internal USB camera support
This change adds internal USB camera into devicetree for sasuke

BUG=None
TEST=Built and checked camera device existence with lsusb

Change-Id: I51b9bb174205d984f1d060afd603f1d087095645
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49162
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:30:05 +00:00
Seunghwan Kim 9c5a3cbc0d mb/google/dedede/var/sasuke: Enable ELAN touchpad
This change adds ELAN touchpad into devicetree for sasuke.

BUG=None
TEST=Built and verified touchpad function

Change-Id: If9c25f23ee1c0e88382fff036f77a6753775b81e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-08 08:29:44 +00:00
Seunghwan Kim c6466aa893 mb/google/dedede/var/sasuke: Enable audio feature
This change adds DA7219 audio codec and MAX98360A amplifier for sasuke.

BUG=None
TEST= Built and heared speaker sound on OS

Change-Id: Ib48eb74fbfe171d46d0d23859057ba169b56bde2
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-08 08:29:31 +00:00
Seunghwan Kim 07339a5c21 mb/google/dedede/var/sasuke: Configure GPIO NC pads
Configure GPIO NC pads for sasuke.

BUG=b:172104731
TEST="FW_NAME=sasuke emerge-dedede coreboot"

Change-Id: I3bf8f97708536010da82402ea3d49e387e732d61
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-08 08:29:22 +00:00
Felix Singer 9486b1dba6 mb/asrock/h110m: Drop DEVICETREE from Kconfig
Drop DEVICETREE from Kconfig since it matches the default value.

Built with BUILD_TIMELESS=1, coreboot.rom remains the same.

Change-Id: Idbcd49cca6494ae2da0f364c24638d7ca11911da
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-01-08 08:28:36 +00:00
Felix Singer c3c8bed057 mb/clevo/cml-u: Drop VGA_BIOS_FILE from Kconfig
It doesn't make sense to configure that filename in Kconfig, since the
filename can be changed by the user. So remove it.

Change-Id: I3eed05637da29096bc1d134505d7335db5db1439
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49138
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:28:16 +00:00
Jakub Czapiga dd85c82962 tests: Add lib/fmap-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I885ea05d509d3b1330de7a18531f310d290c6965
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-08 08:26:26 +00:00
Marco Chen 525cc4626a ec/google/chromeec: add SSFC CBI support
An API is added to get SSFC value from cros EC.

BUG=b:174118027
BRANCH=octopus
TEST=check SSFC value from EC is correct compared to value in CBI

Change-Id: Ifd521514bbc2e90c789f3760b72e8326e614e2b1
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2021-01-08 08:25:42 +00:00
Furquan Shaikh d3b7e2f94a soc/intel/common/uart: Restrict scope of uart_common_init to uart.c
uart_common_init is not used outside of
soc/intel/common/block/uart.c. This change restricts the scope to this
file and drops the declaration from uart.h

Change-Id: I499a53506f9b2e91ecc7334bf9b023d342e802fc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49211
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:24:38 +00:00
Furquan Shaikh fb29ca0c55 soc/intel/common: Pass in pci_devfn_t into lpss_set_power_state
This change updates the parameter passed into `lpss_set_power_state()`
from struct device * to pci_devfn_t. This allows the users in the
early stages to use pci_devfn_t instead of having to walk the device
tree to get a pointer to the relevant device structure. It is
important for optimizing out unnecessary components of the device tree
from the early stages.

Change-Id: Ic9e32794da65348fe2a0a2791db47ab83b64cb0f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49210
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:24:20 +00:00
Furquan Shaikh e4f7e04050 soc/intel: Drop `dev` parameter from soc_get_gen_io_dec_range()
This change drops the parameter `struct device *dev` from the function
`soc_get_gen_io_dec_range()`. This function uses the parameter dev to
get a pointer to config structure for extracting the decode ranges
configured by mainboard in device tree. However, there is no separate
chip driver for the LPC device which means that the SoC code can use
`config_of_soc()` to get to SoC chip config instead of using the LPC
device.

This change is being done in preparation to clean up the device
tree/chip config access in early stages that allows for optimizing
the inclusion of device tree elements in the early stages.

Change-Id: I3ea53ddc771f592dd0ea5e5e809be2d2eff7f16d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-08 08:23:59 +00:00
Furquan Shaikh 2136c5af5f cpu/x86/smm: Use append instead of assign for smm-c-deps
This change uses append operation (+=) instead of assignment (:=) for
smm-c-deps to ensure that any earlier assignment is not
overwritten.

Change-Id: Ic1d62b414cfe3f61ee2b80b026b7338faa186904
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-08 08:23:20 +00:00
John Zhao 4ead6b3367 soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports
USB3 is in CPU and USB2 in PCH on Tigerlake. Cross die messaging is
implemented between CPU and PCH through the IOSF SB bridge. a PCH xHCI
USB2 port reset event issued by the xHCI driver shall trigger a message
upstream to CPU to wake it from the low power state which allows a USB3
device that downgraded to USB2 to upgrade back to USB3.

BUG=b:176575892
TEST=Built and booted to kernel on Voxel board.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I672f30a117980bc10bd71e9b77c5fa76286b9f5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49052
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:22:47 +00:00
Felix Held 81a4c344e7 util/testing: remove genprof target
commit 8c99c27df1 removed util/genprof,
so it needs to be dropped here as well to avoid spurious breakages of
the build.

Change-Id: I420b5c43e2d97373a8e665f457463a06e16ecfb9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49226
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:21:38 +00:00
Yu-Ping Wu 8a82ea9faa ec/google/chromeec: Check AP reset cause for watchdog reset
Different from mt8183, mt8192 doesn't need to trigger EC reboot on HW
initiated watchdog reset. Therefore, ec_reset_flags cannot be used to
determine AP watchdog reset. Instead we check the cause of the last AP
reset.

BUG=b:174443398
TEST=emerge-asurada coreboot
TEST=crash.WatchdogCrash passed on asurada
BRANCH=none

Cq-Depend: chromium:2607150
Change-Id: I761ecdd8811e5612b39e96c73442cc796361d0f0
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49113
Reviewed-by: Nicolas Boichat <drinkcat@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:20:54 +00:00
Yu-Ping Wu 9ff7823fe1 ec/google/chromeec: Update ec_commands.h
This change copies ec_commands.h directly from the Chromium OS EC repo
at SHA afffc28f2, with the exception of changing the copyright header
to SPDX format.

Change-Id: Ie02e0295312050e803a7d701ec4eed1dadfa6c9a
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-08 08:20:37 +00:00
Angel Pons b6dff82aab cpu/intel/model_206ax: Always return a package from _CST
The _CST method is supposed to return a package. If a mainboard used
zero for all ACPI C-states, the generated _CST would return nothing,
which is invalid. Instead, return a package with no C-state entries.

This change is a no-op, since all mainboards have at least one valid
ACPI C-state. This is what `acpigen_write_CST_package()` does, too.

Change-Id: I1f531e168683ed108a8d6d03dee6f5415fd15587
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49092
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:18:13 +00:00
Angel Pons 04b2bb61fd sb/intel/bd82x6x: Remove space in function definition
Just a small change to follow the code style.

Change-Id: Ie838b82e12627478ea721f426efc4d557feb6ae3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49166
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:14:47 +00:00
hao_chou 1807cfbae9 mb/google/volteer: Update copano device tree
Update device tree override to match schematics.

BUG=b:175896481
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot

Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Change-Id: I1fb006d750bb2d670885ec8ccc627436c5078072
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-08 08:14:13 +00:00
hao_chou d880b5ccc5 mb/google/volteer: Add GPIO to copano support
Add support for gpio driver for copano

BUG=b:175896481
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot

Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Change-Id: I1e0f730c9865ed77c7071245b071315a9c6ea4c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48951
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:14:04 +00:00
hao_chou 6df453724f mb/google/volteer: Copano: Update SPD table
Add memory table to "mem_list_variant.txt", and command to generate files:
go run ./util/spd_tools/lp4x/gen_part_id.go src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/copano/memory/ src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt

DRAM Part Name                 ID to assign
MT53D512M64D4NW-046 WT:F       0 (0000)
H9HCNNNCRMBLPR-NEE             0 (0000)
MT53D1G64D4NW-046 WT:A         1 (0001)
H9HCNNNFBMBLPR-NEE             2 (0010)

BUG=b:175896481
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot

Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Change-Id: I2ace17e8fff12d3f5de15a35f609265d8b6ed6b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48948
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:13:31 +00:00
Raul E Rangel 55cf7088fd mb/google/zork: Unmap FCH IO-APIC PCI interrupts
Now that the _PRT generates a GNB IO-APIC routing table we no longer
need to route the PCI interrupts through the FCH IO-APIC. This change
unmaps the IRQs since they are no longer used.

BUG=b:170595019
TEST=Boot with `pci=nomsi amd_iommu=off` and verify /proc/interrupts

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3467934bfcac14311505bec49a12652490554e6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-08 08:13:07 +00:00
Raul E Rangel 9882dde03f soc/amd/picasso: Generate GNB IO-APIC PCI routing table
This adds support for generating a PCI routing table that routes to the
GNB IO-APIC. This means we no longer need to route to the FCH IO-APIC
for PCI interrupts.

BUG=b:170595019
TEST=Boot ezkinil to OS with `pci=nomsi amd_iommu=off` and verify
all peripherals are working

           CPU0       CPU1
  0:        112          0   IO-APIC   2-edge      timer
  1:          0         99   IO-APIC   1-edge      i8042
  4:          0       2523   IO-APIC   4-edge      ttyS0
  5:      34632          0   IO-APIC   5-fasteoi   mmc1
  7:       5646          0   IO-APIC   7-fasteoi   pinctrl_amd
  8:          0          0   IO-APIC   8-edge      rtc0
  9:          0         33   IO-APIC   9-fasteoi   acpi
 10:      88258          0   IO-APIC  10-edge      AMD0010:00
 11:          0      32485   IO-APIC  11-edge      AMD0010:01
 24:       3301          0  amd_gpio   3  cr50_i2c
 25:          0     235214   IO-APIC  28-fasteoi   amdgpu
 26:      67408          0   IO-APIC  31-fasteoi   xhci-hcd:usb1
 27:          0     488876   IO-APIC   8-fasteoi   mmc0
 28:       1265          0  amd_gpio   9  PNP0C50:00
 29:        656          0  amd_gpio  12  ELAN9004:00
 30:        413          0  amd_gpio  31  chromeos-ec
 31:      14153          0   IO-APIC   4-fasteoi   ath10k_pci
 32:          2          0  sysfstrig0      cros-ec-accel_consumer3
 33:          2          0  sysfstrig0      cros-ec-accel_consumer0
 34:          6          0  amd_gpio  62  rt5682
 35:          0      38937   IO-APIC  29-fasteoi   snd_hda_intel:card0, ACP3x_I2S_IRQ

Cq-Depend: chrome-internal:3452710
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3211ab351a332fafb7b5f9ef486bb6646d9a214c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-08 08:12:53 +00:00
Angel Pons 2ce045385a pineview boards: Drop MAINBOARD_HAS_NATIVE_VGA_INIT
Already selected from northbridge Kconfig.

Change-Id: I5a30769b4186041a15fd1264bb0d6efa32cb6eb4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49182
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:11:35 +00:00
Arthur Heymans 08cb80e6ab arch/x86/Makefile.inc: Clean up generated assembly stubs
At the moment neither verstage nor romstage has a generated assembly
stub. This was used when CAR was set up in romstage which is not the
case anymore.

Change-Id: Ia4a952f269cc2b3edf1290c80b7a63619c8c6c95
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-08 08:10:04 +00:00
Arthur Heymans c6bdabd983 payloads/external: Update cbfs-ints with CONFIG_UPDATE_IMAGE
Change-Id: Icfbfff3ba680a85eb2f683867064b19f40b9d40f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48898
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:09:08 +00:00
Arthur Heymans 17c951b2c4 */Makefile.inc: Add some INTERMEDIATE targets to .PHONY
Change-Id: I125e40204f3a9602ee5810d341ef40f9f50d045b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48897
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:08:07 +00:00
Arthur Heymans 51d23c589b util/crossgcc/.gitignore: Add cmake
Change-Id: I5ce346515f4468699396e214acfaa3b62f6d891d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-08 08:06:34 +00:00
Jeremy Soller dd874c80cd ec/system76/ec: Remove unused EC RAM fields
These fields were originally added for compatibility with the
proprietary ITE EC firmware, but the System76 EC firmware does not use
them. Take the opportunity to document most of the fields as well.

Change-Id: I5581437c67ec67705ce16ba20254183a0261fd83
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-08 08:06:20 +00:00
Julius Werner 1153b2ef5c cbfstool: Use flock() when accessing CBFS files
Trying to do multiple operations on the same CBFS image at the same time
likely leads to data corruption. For this reason, add BSD advisory file
locking (flock()) to cbfstool (and ifittool which is using the same file
I/O library), so that only one process will operate on the same file at
the same time and the others will wait in line. This should help resolve
parallel build issues with the INTERMEDIATE target on certain platforms.

Unfortunately, some platforms use the INTERMEDIATE target to do a direct
dd into the CBFS image. This should generally be discouraged and future
platforms should aim to clearly deliminate regions that need to be
written directly by platform scripts with custom FMAP sections, so that
they can be written with `cbfstool write`. For the time being, update
the legacy platforms that do this with explicit calls to the `flock`
utility.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I022468f6957415ae68a7a7e70428ae6f82d23b06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-08 08:04:04 +00:00