Commit Graph

22813 Commits

Author SHA1 Message Date
Marshall Dawson a05fdcb269 amd/stoneyridge: Change SMM setup functions
Remove the APMC-specific initialization call.  Make the function
which programs the event type not static and call it from the
southbridge.c file.

Change-Id: I1e3cf898637720fa835de0a6e735c6a65fe2d3a2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:31:32 +00:00
Marshall Dawson f039a0befc amd/stoneyridge: Add PM defintions to southbridge.h
Change-Id: I2534ab34f8a8d151e80004ee05d3061f013316b0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21747
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:31:14 +00:00
Marshall Dawson 36a2356fb1 amd/stoneyridge: Refactor SMI handler
Rewrite the handler to be more compact and extendable.  The old
functionality is duplicated after the rewrite.  All SMI source registers
(except for SmiSciStatus) behave identically so these are consolidated.
Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on.

Create a table of mini-handlers to be supported in the soc directory.
As SMI sources are discovered, attempt to find the corresponding handler
and then execute it.

Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21746
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:30:57 +00:00
Marshall Dawson c6c4a213c5 amd/stoneyridge: Clean up smihandler.c
Replace hardcoded values with defined ones.

Change-Id: Ic72a51516a1763b2380e60397f5a3aeb32457b65
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:30:20 +00:00
Marshall Dawson 66e62da4c7 amd/stoneyridge: Check SMI command address before reading
Use the currently programmed address of the SMI command port before
checking the passed command.  This ensures we're reading the right
port in case the port was relocated without our knowledge.

Change-Id: I8a3ca285d3a9afd4a107cd471c202abf03f372ac
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02 22:30:02 +00:00
Marshall Dawson eecb794c96 amd/stoneyridge: Move pm/smi_read/write functions to util file
Pull all pm_read and write, smi_read and write variants into a single
file.

Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:27:38 +00:00
Marshall Dawson 16745e39b6 amd/stoneyridge: Add pm_read32 and pm_write32 to southbridge
Duplicate existing pm_read and pm_write and create 32-bit register
access functions.

Change-Id: I916130a229dc7cef8dae1faf00a38501d3939979
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21749
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:27:19 +00:00
Marshall Dawson f7ace0da45 amd/stoneyridge: Fix pm_read16 argument size
Make pm_read16() consistent with the other PM register access functions.

Change-Id: Iba017b8090ed07d8684cc7f396a3e9a942b3ad95
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21748
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:27:00 +00:00
Marshall Dawson 9db0a2dcc8 amd/stoneyridge: Clean up smi_util.c
Replace hardcoded values with defined ones.

Change-Id: If963a817a4bea9b6dbb0d41a2bc0789a44a01391
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:26:50 +00:00
Marshall Dawson 714c087788 amd/stoneyridge: Add more SMM definitions
Change-Id: I4c8069a18ea430ec6e66d41879c8e77f1ef2b340
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:26:38 +00:00
Marshall Dawson abac64d4d0 amd/stoneyridge: Add uart.c to smm-y list
This corrects a build error when a developer needs DEBUG_SMM and one
of the APU's internal UARTs is used.

Change-Id: Ie1962e969a8cb93eefc0b86bf4062752580e5acd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21740
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:26:05 +00:00
Julius Werner e0459c78e4 google/gru: Fix pmu1833_volsel handling
RK3399 has a pin that can decide whether GPIO port 1 is driven with 1.8V
or 3.0V. We thought this mechanism was disabled by default, but it turns
out it wasn't. We want to use that pin as an output GPIO on Scarlet so
we need to reconfigure the respective SoC controls before we do that. It
seems that we also need to explicitly pinmux the pin away from that
special function (to normal GPIO) or weird things happen on some boards.

BUG=b:66534913
TEST=Sprinkled several long udelays, poked test points with a
multi-meter on Scarlet.

Change-Id: Ia02cbb4f3b2f14b0d958b84adcddb0c5f4259efa
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/21727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-02 18:32:11 +00:00
Aaron Durbin cf20c90430 util/cbmem: fix feedback for 'be explicit about memory map sizes'
Julius made some suggestions to fix/improve commit 46300aa2.
Implement those.

BUG=b:66681446

Change-Id: I6becac9ffdcc65745e88734dfb80d12b581584a1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-10-02 17:16:14 +00:00
Martin Roth 7c48b891fe mainboard/amd: Add required callouts to Stoney BiosCallouts.c
Hook the new required AGESA callout functions into the callouts tables.

BUG=b:66690176
TEST=Build and boot Kahlee - see the functions get called.

Change-Id: Ife9c2b20e59ede404edb1f700238e425fea35914
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02 16:24:53 +00:00
Martin Roth f80a431c11 soc/amd/common: Add framework for missing AGESA callouts
These are required callout functions that currently are not implemented.
agesa_LateRunApTask does not seem to be called, but the others are.

BUG=b:66690176
TEST=Build Kahlee.  Tested in next commit.

Change-Id: Iee5f9c4847a5309a25045fca8c73be4f811c281a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21707
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02 16:24:49 +00:00
Shelley Chen da6e4f6935 google/fizz: Enable wake-on-usb attach/detach
BUG=b:62095784, b:35775024
BRANCH=None
TEST=Run powerd_dbus_suspend from kernel.  Plug in
     usb device and make sure wakes up.

Change-Id: I214d6557998bdaf1d327c2a45532461b95d56a96
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02 16:20:31 +00:00
Marshall Dawson df31904133 cpu/x86: Align stack in SIPI handler
Ensure the stack is properly aligned in the SIPI handler.  This
avoids an exception when an aligned instruction is performed on
stack data.

BUG=b:66003093
TEST=boot kahlee built with gcc 6.3

Change-Id: Ibdd8242494c6a2bc0c6ead7ac98be55149219d7c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02 16:15:42 +00:00
Richard Spiegel 38f19400f9 soc/amd/stoneyridge/southbridge.c: Remove preprocessor #if
Replace #if and #endif with runtime <if (condition) {> and <}>

Code Files: southbridge.c
BUG=b:62200891

Change-Id: I69877bf301fa89781381e3eb8e6b4acd7e16b4b4
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-02 16:08:17 +00:00
Marshall Dawson e9b862eb2c amd/stoneyridge: Use generic SMM command port values
Remove the old Hudson-specific SMM command port definitions and use the
ones in cpu/x86/smm.h.

Change-Id: I3de9a178e5f189ac1dbc921e41b69d47e3796a4f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-30 20:34:28 +00:00
Marshall Dawson 6746d3784f amd/stoneyridge: Remove HAVE_SMI_HANDLER from makefile
Stoney Ridge always now selects HAVE_SMI_HANDLER so it is pointless
to use the variable in Makefile.inc.  Make all files built into smm
unconditional.

Change-Id: I4ea89d7bce83a99328c58897a4098debacd86d66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-30 20:32:48 +00:00
Marshall Dawson b639bef836 soc/amd/common: Add included directory
If the symbol SOC_AMD_COMMON is selected, include the soc/amd/common
directory.  Until now this has been working due to the directory being
included as part of AGESA_INC in vendorcode.  That one is still
necessary in order to build the AGESA code so it is left in place
for now.

Change-Id: Ia8191897d2030c475c9268ae86faaf01952c6ace
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-30 20:29:11 +00:00
Patrick Rudolph c060fb5aac soc/intel/braswell/acpi: Clean OpRegion up
Reorder code and put platform specific bits into update_igd_opregion.
Get rid of get_fsp_vbt and init_igd_opregion.
Write GMA opregion in case a VBT was provided, even when no FSP_GOP
is to be run.
Use SOC_INTEL_COMMON_GFX_OPREGION to reduce code duplication.

Change-Id: Ibabeb05a9d3d776b73f6885dcca846d5001116e7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-30 01:24:47 +00:00
Kyösti Mälkki 7c60498de7 AGESA binaryPI: Drop amdlib.h in BiosCallouts.c
Some fam14 boards will need more work on this area,
those are to be addressed with followup patches.

Change-Id: I14208cf8519a4cf71e4944d08a2dae36b7f1f878
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-29 05:46:19 +00:00
Kyösti Mälkki 8e2f6caaf0 AGESA binaryPI: Drop amdlib.h in dimmSpd.h
Change-Id: Ic1713d1530071e29bd04b525f68d4a44d20ea2e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-29 05:45:53 +00:00
Kyösti Mälkki 4286502140 AGESA binaryPI: Fix indirect AGESA.h include
Change-Id: I5e2affe337f7e61ca79530b3a77af963e8692ff1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-29 05:45:44 +00:00
Nick Vaccaro d3e00ab209 google/zoombini: Add new board
Add zoombini board files using cannonlake and FSP 2.0.
Copied most initial files from poppy and cannonlake_rvp.

BUG=b:64395641
BRANCH=None
TEST=Compiles successfully using "./util/abuild/abuild
-p none -t google/zoombini -x -a"

Change-Id: I13ebaae403d08f1b2e6881eeba4dc1787c792b4e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/21273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-28 18:28:59 +00:00
Nico Huber bc652b9717 Kconfig: Move libhwbase related options into lib/Kconfig
More will follow so better move them where they are used. Also remove
defaults and add dependencies to not clutter .config files up that
don't have any of these options selected.

Change-Id: I3a255c821cc26aeb66e4fd6adf7142d7e856f5ac
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-28 11:47:07 +00:00
Mario Scheithauer 0b42c8ae0c siemens/nc_fpga: Move some parameters to another function
For general use of this driver it is necessary to move some parameters
from init_fan_ctrl() to init_temp_mon(). This shift does not lead to any
functional change.

Change-Id: I6b8f770c768f3dacf96087eb0194cc99f0d11e17
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-28 09:01:26 +00:00
Kyösti Mälkki d2fa337333 amd/stoneyridge: Drop FieldAcccessors
It was either SAGE or AMD AES who implemented these for
binaryPI, and it is not part of the documented AGESA API.

My conclusions of these are:

AmdGetValue() returns values from build-time configuration,
these may not reflect the actual run-time configuration as
there are OEM customization hooks to implement overrides.

AmdSetValue() in __PRE_RAM__ will fail, as configuration
data is const. Also AmdSetValue() in ramstage may fail, if
said configuration data has already been evaluated.

Semamtics of these calls are unusable unless one also has
access to PI source to make exact decision on when they
can be called. Remove these now that stoneyridge does not
actually require them.

Change-Id: I3379a75ce3b9448c17ef00eb16d3193c296626cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-28 08:10:49 +00:00
Aaron Durbin 46300aa2ce util/cbmem: be explicit about memory map sizes
The cbmem utility has inherited some workarounds that originated
from the default 1 MiB mapping always working. This 1 MiB mmap
won't necessarily succeed if the 1 MiB encroaches on a subsequent
memory range that has different cacheability.

To fix this, map in only 4 KiB when the table size is not known which is
the case for any forwarding entry or any low table entries on x86. That
smaller mapping is then searched for a valid header. Once a valid header
is found the full table is mapped and parsed allowing a forwarding entry
to take precedence.

Lastly, the lbtable is kept mapped in such that other operations can
just operate on mapping that was previously parsed.

In order to allow multiple in-flight mappings a struct mapping was
added which caused the ripple within the code. However, there shouldn't
be any more reasons for putting weird heuristics for when to fail. If
the tables are bad then it's very much possible that mappings will fail.
Retrying when the exact sizes are already known won't fix those issues.

BUG=b:66681446

Change-Id: Ica0737aada8dc07311eae867e87ef2fd24eae98d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-28 04:48:52 +00:00
Aaron Durbin f2a3822488 util/cbmem: make data structure accesses const
Since the mapping is const just make all the data structure accesses
const.

BUG=b:66681446

Change-Id: I018cf2f2bfea2e736b097ecd1242af19c878ecb5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-28 04:48:45 +00:00
Felix Held 6d717ae55f drivers/usb/Kconfig: remove USBDEBUG_DONGLE_BEAGLEBONE_BLACK
Remove the USBDEBUG_DONGLE_BEAGLEBONE_BLACK option that does the same as
USBDEBUG_DONGLE_STD and update the description of USBDEBUG_DONGLE_STD that it
also should be selected for the BeagleBone Black.

Change-Id: I3093a6d2c39e7b5e81785028e436109090d9e6dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/21486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-28 01:32:49 +00:00
Paul Menzel 395b469958 commonlib: Consistently spell *romstage* without space
Make the spelling of *romstage* consistent without a space. Choose this
version, as *ramstage* is also spelled without a space, since commit
a7d924412a (timestamps: You can never have enough of them!).

Fixes: 0db924d74c (cbmem: print timestamp names)
Change-Id: I1b1c10393f0afb9a20ac916ff9dc140a51c716cd
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-27 22:20:25 +00:00
Martin Roth 37b8bdef6b soc/amd/stoneyridge: Enable SSE
BUG=b:66997392
TEST=Flash to Kahlee, system no longer resets when the compiler uses
SSE instructions.

Change-Id: I7c1aed9ecfa6f3496760dcda422ddf184e2a043c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27 17:38:47 +00:00
V Sowmya 77be394b1d soc/intel/skylake: Remove CCA object for IMGU and CIO2 devices
IMGU and CIO2 devices do support the hardware managed cache
coherency and hence removing the CCA object which was
reporting that cache coherency is not supported.

BUG=none
BRANCH=none
TEST=Build and boot soraka. Dump ACPI tables and verify that
CCA object is not present.

Change-Id: I14b0a92eafe193e9004d2dad0957a3fe8d05d313
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27 16:43:54 +00:00
V Sowmya c6c4217968 mb/google/poppy: Modify HID and add device tree support for VCM device
Modify the HID to align with ACPI spec. Add the DSD object
for the device tree support in kernel which will probe
the DW9714 device based on the HID.

BUG=b:65423422
CQ-DEPEND=CL:654383
BRANCH=none
TEST=Build and boot soraka. Verified that the VCM device
probe is successful.

Change-Id: Ic4a59dd2027267fbd3837fcd7dbc00551a69f7d6
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-27 16:43:22 +00:00
Patrick Rudolph 5a061852b2 nb/intel/sandybridge/raminit: Improve readability
Add debug messages for SPD probing.

Change-Id: I722102b7981781b88cdc4877f698294eb719ff32
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-27 16:41:49 +00:00
Jonathan Neuschäfer 3b2712d757 arch/riscv: hls_init: Initialize time{,cmp} with dummy pointers
In current versions of spike, the config string is not available
anymore, because RISC-V is moving toward OpenFirmware-derived device
trees (either in FDT or text format). Using query_config_string leads to
a crash in these versions of spike.

With this commit and If0bea4bf52d ("riscv: Update register address"),
coreboot reaches the romstage again, on spike.

Change-Id: Ib1e6565145f0b2252deb1f4658221a4f816e2af4
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-27 16:41:03 +00:00
Jonathan Neuschäfer 69a143d682 arch/riscv: Document mprv_{read,write}_* functions
Change-Id: Iaf0cb241f0eb4de241f0983c0b32dbcc28f96480
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-27 16:39:49 +00:00
Jonathan Neuschäfer d54c1cc770 mb/emu/*-riscv: Remove outdated memory map
Change-Id: I8919719865bc7ae8d13f025999caf8b5836b88ab
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-27 16:39:25 +00:00
Jonathan Neuschäfer 5a01d6a152 arch/riscv: trap handler: Print load/store access width in bits
This is easier to read than the raw shift amount that's extracted from
load/store instructions.

Change-Id: Ia16ab9fbaf55345b654ea65e65267ed900eb29e1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-27 16:39:03 +00:00
Jonathan Neuschäfer 7090377a87 smbus: Fix a typo ("Set the device I'm talking too")
Change-Id: Ia14bbdfe973cec4b366879cd2ed5602b43754260
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-27 16:38:18 +00:00
Peggy Chuang 7a2d4e56c7 Coral: Add Synaptics touchpad support
We need support two touchpad for Robo project,
so adding Synaptices touchpad to coral.

BUG=b:63134907
TEST=Compiled, verified by ODM

Change-Id: If5a650338d5a7e6f01e9525d28588b871d390e50
Signed-off-by: Peggy Chuang <peggychuang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/21696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27 16:37:45 +00:00
Marshall Dawson d61e832e53 soc/amd/stoneyridge: Revert CAR teardown wbinvd
Change the cache-as-ram teardown to use invd instead of wbinvd.
Save the return and recover the call's return address in
chipset_teardown_car.

CAR teardown had been modified to use wbinvd to send CAR contents
to DRAM backing prior to teardown.  This allowed CAR variables,
stack, and local variables to be preserved while running the
AMD_DISABLE_STACK macro.

Using the wbinvd instruction has the side effect of sending all
dirty cache contents to DRAM and not only our CAR data.  This
would likely cause corruption, e.g. during S3 resume.

Stoney Ridge now uses a postcar stage and this is no longer a
requirement.

BUG=b:64768556

Change-Id: I8e6bcb3947f508b1db1a42fd0714bba70074837a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20967
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-27 16:31:21 +00:00
Marshall Dawson 18b477ea41 soc/amd/stoneyridge: Add postcar stage
Insert a postcar stage for Stoney Ridge and move romstage's CAR
teardown there.

The AMD cache-as-ram teardown procedure currently uses a wbinvd
instruction to send CAR contents to DRAM backing.  This allows
preserving stack contents and CAR globals after the teardown
happens, but likely results in memory corruption during S3 resume.
Due to the current base of the DCACHE region, reverting to an
invd instruction will break the detection mechanism for CAR
migrated variables.  Using postcar avoids this problem.

The current behavior of AGESA is to set up all cores' MTRRs during
the AmdInitPost() entry point.  This implementation takes control
back and causes postcar's _start to clear all settings and set
attributes only for the BIOS flash device, TSEG, and enough space
below cbmem_top to load and run ramstage.

BUG=b:64768556

Change-Id: I1045446655b81b806d75903d75288ab17b5e77d1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27 16:29:05 +00:00
Marshall Dawson 9db8a44081 amd/stoneyridge: Move AmdInitEnv to ramstage
Relocate the call to AGESA in preparation for implementing postcar.
This change should have no net effect as long as the ordering is
maintained and AmdInitEnv stays later than CAR teardown.

BUG=b:66196801

Change-Id: I0e4a5fd979b06cf50907c62d51e55db63c5e00c5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-27 16:27:17 +00:00
Marshall Dawson 6c74706856 amd/stoneyridge: Put AGESA heap into cbmem
Now that soc/amd supports EARLY_CBMEM_INIT, put the HEAP into cbmem,
allowing better control of its cacheability in subsequent patches.
This relocates the heap initialization from the common directory into
a romstage cbmem hook.  The conversion relies on cbmem_add() first
searching cbmem for the ID before adding a new entry.

Change-Id: I9ff35eefb2a68879ff44c6e29f58635831b19848
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-27 16:27:09 +00:00
Marshall Dawson ed501d5b3f soc/amd/common: Clean up GetHeapBase function
Make GetHeapBase a static function.  Change the type of return value to
a void pointer and remove the unused StdHeader argument.  This should be
innocuous and will allow a subsequent patch to be simpler.

Change-Id: Id4a024d000a514ea9a44f9dfc2caffae9ff01789
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21593
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-27 16:27:02 +00:00
Marshall Dawson f82aa10d56 amd/stoneyridge: Clean up include files in northbridge.h
Add an extra include file to northbridge.c for completeness.  cpu/msr.h
is already included in cpu/amd/mtrr.h which allows the file to build
properly.

Remove include files that are no longer required for the file.

Change-Id: I3e5ab39fd0640d2983fc5b7b202fb65d42c5ce3d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27 16:26:54 +00:00
Marshall Dawson b617211910 amd/stoneyridge: Enable SMM in TSEG
Add necessary features to allow mp_init_with_smm() to install and
relocate an SMM handler.

SMM region functions are added to easily identify the SMM attributes.
Adjust the neighboring cbmem_top() rounding downward to better reflect
the default TSEG size.  Add relocation attributes to be set by each
core a relocation handler.

Modify the definition of smi_southbridge_handler() to match TSEG
prototype.

BUG=b:62103112

Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-27 16:26:40 +00:00