While running the s0ix cycling test, we observed SMM Handler caused
a stack overflow. This error happens during event log access.
This change is to increase the SMM_MODULE_STACK size to 0x800
BUG=b:135551854
TEST=suspend_resume test pass 500+ cycles, originally issue happenes
within 150 cycle
Change-Id: Ib4686b4d2d4fc3976068779314f4ee15ef4a8ae2
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
To call dev_find_slot(0, xx) in romstage can produce
invalid results since PCI bus enumeration has not
been progressed yet.
Replace this with method that relies on bus topology
that walks the root bus only.
Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Find the NIC device based on the PCIe root port function.
Change-Id: Ia8c6e115c9b836ee60862427dfc9d46ca3dd1b69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Like the line above it, this should be & instead of | (otherwise it will
always incorrectly return true). spi_locked() is only used internally to
decide which opcodes will be used to talk to the flash, and if it is
falsely reported as locked, the worst case should be a denial of service
(unless there are more bugs).
Change-Id: I5208b523c815d15d7263594f06ccfacd8a9510b1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1402092
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
With VBOOT=y && VBOOT_MEASURED_BOOT=y message
digest will be allocated from the stack and
1 KiB reserve used with the recent platforms
was no longer sufficient.
The comment of LZMA scratchpad consuming stack
was obsolete for postcar, so these can be reduced
to same 4 KiB.
Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Use of romstage_ram_stack_bottom() was invalid, it
potentially uses a different ROMSTAGE_RAM_STACK_SIZE
from the postcar_frame_init() call.
If alignment evaluated to 1 MiB, that WB MTRR may not
have covered all of CBMEM range, having some impact
on boot speeds.
There is no need to accurately describe write-back
MTRR ranges for postcar.
Change-Id: Icb65cef079df56fadcc292c648cab8bdbb667f47
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This reverts commit f70cb8bf96.
It was merged prematurely with some vague argumentation in the commit
message and not all issues of reviewers were addressed.
Change-Id: Ia336f3499fb29976a6b80383ef8b0f3d552f5640
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
It's forbidden to use dereference CAR_GLOBAL variables
directly. The notation fails after CAR teardown for
romstage.
Change-Id: I6e6285ca0f520608c2a344517fbac943aeb36d87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33995
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the mailbox call to notify the PSP that DRAM is ready. This
is not supported on Family 17h.
Remove the selectable SMU firmware. This is a feature of the PSP
bootloader and the standard bootloader doesn't contain the ability.
Clean up additional mentions of PSP within picasso.
Change-Id: I8abeb4c375dbff3b438cd18ccaaf66e11c86e72e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
The command line options for picasso will look different than
stoneyridge. Remove the fanned/fanless distinction to simplify
the makefile.
Picasso will use subprograms instead of fanned/fanless SKUs.
Change-Id: I50d8751e14b00ca53a6498f8e6c7f3f42543dace
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33753
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Picasso doesn't implement the AcpiMmio XHCI_PM registers. Remove
source that uses these. Remove USB devices from the AOAC registers.
Remove the D0/D3 support from ASL, including all supporting xHCI
firmware loading support. Remove xHCI firmware from amdfw.rom.
Change-Id: Iae4c72c5a8e353ca8db02d04735f8d2b28441793
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
It was never tested or injected.
Change-Id: I3fd82aaa11afc5adab212ec6709580b4bcc67ca3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34001
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only (conditionally) used part was dump_pci_device()
and that was never particularly useful either.
Change-Id: Iaacfa511de1ce1e0bdbd2e8a74e41d336e505670
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Google project name is Bloog.
Bloog is 12-inch LCD.
Blooguard is 14-inch LCD so would prefer to use a different SAR values instead.
Use sku-id to load the SAR values.
BUG=b:135078377
BRANCH=octopus
TEST=build and verify SAR load by sku-id
Change-Id: Id80df28a961eb1f62714558df2b219aa552ecb97
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
When we added CONFIG_VBOOT_MIGRATE_WORKING_DATA, the idea was that on
some Arm platforms the original working data buffer was in SRAM, which
stays accessbile for the whole runtime of the system. There is no reason
to migrate it into CBMEM on those platforms because ramstage and the
payload could continue to access it in SRAM.
Now that we've had a couple of months of experience with this option, we
found that most of our Arm platforms have some issue that requires
migrating anyway, because BL31 often claims SRAM for itself and makes it
inaccessible to the payload. On the remaining platforms, accessing SRAM
from the payload is possible but still an issue, because libpayload
doesn't have enough memory layout information to set up proper page
tables for it, so we're accessing it uncached and at risk of alignment
errors.
Rather than having to figure out how to map the right SRAM range for
every platform in the payload, let's just get rid of the option.
memcpy()ing 12KB isn't worth this much hassle.
Change-Id: I1b94e01c998f723c8950be4d12cc8f02b363a1bf
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Use literals KHz & MHz for kilohertz and megahertz frequency usages
in macro definition.
Change-Id: If1ca6e5e7b0603f93f3c980cc85af470fdcd54ba
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
MMIO_BUS_RANGE_SHIFT is a numerical value and not a bit field.
Change it to simply 2. Otherwise its usage winds up evaluating
to BusRange << (1 << 1).
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I2a6ecfc9fbfd45f69194b8daef43ff84a1dfd5fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Also don't define the default as this results in spurious lines in the
.config.
The only difference in the generated config.h is that for most board
ARCH_RISCV_M goes from 1 to 0. This should not matter.
Change-Id: I3e8c1cc5696d621e243696a3b5e34f62ab69a688
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31311
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enhance elog wake source information with more details about which USB port
resulted in a wake from S3 or S0ix.
BUG=b:123429132
BRANCH=none
TEST=``FW_NAME=hatch emerge-hatch chromeos-ec depthcharge vboot_reference
libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch
coreboot chromeos-bootimage``
Ensure /build/hatch/firmware/image-hatch.serial.bin has been built.
Plug a keyboard into a USB port on the DUT.
Switch the DUT to the console (Ctrl-Alt-F2, or use the AP console via
servo).
On the console, run ``powerd_dbus_suspend``.
Wait for the DUT to enter low power mode.
Verify low power mode by issuing the ``powerinfo`` command on the EC
console (via servo). Expect to see ``power state 4 = S0ix``.
Press a key on the USB keyboard.
The DUT wakes up.
On the console, run ``mosys eventlog list`` and look for the wake source.
156 | 2019-06-26 09:46:07 | S0ix Enter
157 | 2019-06-26 12:14:05 | S0ix Exit
158 | 2019-06-26 12:14:05 | Wake Source | Internal PME | 0
159 | 2019-06-26 12:14:05 | Wake Source | GPE # | 109
Program image-hatch.serial.bin into the DUT using flashrom.
Repeat the ``powerd_dbus_suspend``, ``powerinfo``, ``mosys eventlog list``
sequence.
12 | 2019-06-26 14:52:23 | S0ix Enter
13 | 2019-06-26 14:53:07 | S0ix Exit
14 | 2019-06-26 14:53:07 | Wake Source | PME - XHCI (USB 2.0 port) | 3
15 | 2019-06-26 14:53:07 | Wake Source | GPE # | 109
Change-Id: Ie9ef870e219733dea9806c766f5351db25689b32
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Previously, We had to use GPP_A21 for trackpad wake and GPP_D21 for
trackpad interrupts due to ITSS not honoring the INVERT config. Now
that's fixed, we can configure trackpad wake and interrupts on GPP_A21
only.
BUG=b:130436471
BRANCH=None
TEST=1. boot a hatch device and make sure we can move the cursor with the trackpad
2. Run powerd_dbus_suspend and wake by clicking on the trackpad and ensure
through "mosys eventlog list" that the wake source is the trackpad.\
3. Run "echo mem > /sys/power/state", wait until device goes into S3,
click trackpad to ensure device wakes.
Change-Id: I26a99206c42ba442f91ae577b98366fc2fd6c0ca
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Now that ITSS config is fixed, we can set the IOAPIC pad configs
correctly.
BUG=b:123967687
BRANCH=None
TEST=Make sure Hatch is booting and tested out trackpad to make
sure can move cursor and wake by clicking on the trackpad
after running powerd_dbus_suspend.
Change-Id: I0b125996338b6f16e03b7ca184f6337c696a5f64
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33819
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove all Picasso bootblock support. CAR is not a supportable
feature, and the first code executed at the reset vector will be
a hybrid romstage. Details for this implementation may be found
in Documentation/soc/amd/picasso/family17h.md.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8edf45c02dc5bfcdca03abf1294db4be508682cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Update paths. There are still a few paths in Kconfig relating to PSP
and the firmware directory table. Those will be updated in a follow-on
commit.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I18f3d80dbeabd754ebcee6593864fd613fc2ef7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32412
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the Makefile is updated, we can change the name back without
it affecting the Stoney build.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I18ee48865fb64265f38179560265827783d50820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Remove files that aren't needed for the picasso port.
Remove traces of AGESA v5 (includes binaryPI support files). Remove
SPD helper.
Picasso (and all AMD Family 17h processors) have a very different
boot flow from previous products. Memory is initialized by the PSP
before the x86 processor is released from reset. The SPD is read by
the PSP, so it's not needed in coreboot.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I743ffd6058982f8f182ea4d73172a029967f3ea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
So that everyone can see what's being updated from stoney, we're
starting with a direct copy of the stoney directory. There are
arguments both for and against doing it this way, but I believe
This the most transparent way. We've moved much of the duplicated
stoney code into the soc/amd/common directory and will continue
that work as it becomes obvious that we have unchanged code between
the SOCs.
Makefile.inc has been renamed as makefile.inc so that it won't
build in jenkins until the directory is updated.
Other than that change, this is an exact copy of the stoneyridge
SOC directory which will be updated in the follow-on commits in
the patch train.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For the PCI_VENDOR_ID_ATI case, we can rely on
pci_rom_acpi_fill_vfct() to make the call if necessary.
For hardware other than ATI, pci_rom_probe() was already
called from pci_rom_ssdt() and pci_dev_init(), so
PCI_ROM_ADDRESS BAR is already enabled, if requested so.
Change-Id: I0ea893a9ac7ba480840ebf5570d8fe0d9e20938f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
The function pci_rom_probe() may be called multiple times
for a device. For cases where CBFS does not contain optionrom
file, only the first time probing for the on-board ROM
chip worked.
PCI_ROM_ADDRESS_ENABLE is set on the first run. Mask out all
the reserved bits of PCI_ROM_ADDRESS register to get correct
physical address for rom_header.
Change-Id: I14374954af09201494bf2f13e5a6e4dc640c05ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
* Add architecture independend way of clearing all DRAM
* Implemented in ramstage as MTRRs need to be set to speed up
clearing. Takes up to 15 seconds per GiB otherwise.
* Use memset_pae on x86
* Add quirks for FSP1.0
Tested on P8H61M-Pro:
* Clears 4GiB in less than 1 second
Tested on wedge100s:
* Clears 8GiB in 2 seconds
Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31550
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To clear all DRAM on x86_32, add a new method that uses PAE to access
more than 32bit of address space.
Add Documentation as well.
Required for clearing all system memory as part of security API.
Tested on wedge100s:
Takes less than 2 seconds to clear 8GiB of DRAM.
Tested on P8H61M-Pro:
Takes less than 1 second to clear 4GiB of DRAM.
Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31549
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since ttyS0 isn't used for UART0, configure ttyS4 as default
Change-Id: Ia0469226253b08328807d5401c05633296e43d22
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33785
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No message is reported in tlcl_lib_init() when tis_init() or tis_open()
returned an error value.
Add debug string.
BUG=N/A
TEST=Build binary and verified logging on Facebook FBG-1701
Change-Id: I522e488ddd3a1bd94a1a8c8470c757bd79c6d5c5
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Prior to commit
d731a24 src/cpu/intel: Set get_ia32_fsb function common
value of 200 was silently used as a default for fsp_rangeley
(model_406dx) in cpu/x86/lapic/apic_timer:set_timer_fsb().
After the commit, get_ia32_fsb() returns -2, eventually
resulting with divide-by-zero in timer_monotonic_get(), as
get_timer_fsb() returns 0.
Add Rangeley CPUID model 0x4d to get_ia32_fsb() as a fix,
using BCLK = 100 MHz based on the comments in
northbridge/intel/fsp_rangeley/udelay.c
Change-Id: I306f85dba9b1e91539fc0ecc9b2ae9d54f82be6c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This patch makes CONFIG_RAMPAYLOAD default enable upon selection
of HAVE_RAMPAYLOAD kconfig from mainboard for x86 platform.
Without this CL, CONFIG_RAMPAYLOAD is still disabled although
mainboard has selected CONFIG_HAVE_RAMPAYLOAD.
Change-Id: I40308bbf970a0dbe5f7e2086ed8a7a70c2a3a32c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33859
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It looks like in days gone by that these switches were once parts of
loops that incremented 'index' as they went along. However, we don't
have any loops anymore, so remove the needless increments and streamline
the rest of the assignments.
Change-Id: Iaabee984333c273af7810f9c11ed26bbb2a995d1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: scan-build 8.0.0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
- Add documentation comment
- Use 'unsigned int' to make checkpatch happy
- Return early if no more links need to be added
- Add error handling if malloc fails
- Clean up whitespace
Change-Id: I70976ee2539b058721d0ae3c15edf279253cd9b7
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229634
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33238
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This function is duplicated in many AMD northbridge files, and all
the definitions have started to diverge somewhat. This moves a single
copy into device utils and deletes the rest. The function definition
from nb/amd/amdfam10 was chosen to be kept, since it contains several
fixes from commit 59d609217b (AMD fam10: Fix add_more_links) that
the others don't have.
For the ease of diffing, the checkpatch lints and other small cleanups
will be done in a follow-up patch.
Change-Id: I5ea73126092449db3f18e19ac0660439313072de
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33237
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All the clocks are switched on anyway, so this series of if statements
isn't needed.
Change-Id: I654043fd6736caa6890fd697015c577ddaa7cd41
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 13473{27-30}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
By default printram() expands to nothing in normal builds, and so
scan-build thinks that the assignment to reg8 is unused. Inline the
value of reg8 into the print statement to silence the warning.
Change-Id: I921fe08949c4135367bee9646b3b365097fab19e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: scan-build 8.0.0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Pstate_num is initialized later when it is used as a loop index, so this
duplicate assignment can be removed.
Change-Id: I71429bd3306139a823ed39e751d779e4d874f657
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: scan-build 8.0.0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
FSP sets the use of the 8254 timer via the Enable8254ClockGating
UPD, which defaults to enabled, overriding what is set by coreboot.
Per the FSP integration guide, this UPD needs to be disabled when
a legacy OS is booted (ie, when SeaBIOS is used as the payload).
Add a Kconfig option to set the UPD properly based on payload
selection, and remove the existing coreboot code in lpc.c since
it is either ineffective or being overridden by FSP.
Test: build/boot out-of-tree WHL board with both SeaBIOS and
Tianocore, ensure 8254 timer usage set correctly for each.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I0e888bf754cb72093f14fc02f39bddcd6d288203
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
It has been observed by me and Elisenda Cuadros / Gergely Kiss [1] that
the boot process of this board is super slow when UART 0 is being used -
even if nothing is connected to it. Enable UART according to
CONFIG_UART_FOR_CONSOLE - and, if UART 0 is selected, it will be initialized
at romstage and this problem will not happen.
[1] https://mail.coreboot.org/pipermail/coreboot/2018-February/086132.html
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I6579aa8fd092da84f8afdcc33496db45c582919f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Correct i2c address of trackpad. It should be 0x20.
BUG=None
BRANCH=None
TEST=Verified trackpad works on pre-evt system
Change-Id: I7ded21ce8ff9e907e436777a27edb4273512011d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
We want to catch warnings as early as possible.
Change-Id: Ifdb2ff8f7973d557a437ac127e073306f76ca6f6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33848
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop hacked uart code and use the generic 8250 uart driver for ns16550a.
Tested on qemu-system-riscv64:
* The UART is still working.
Change-Id: I6efda913fa39e0cfa466b52c570572aca90dacdf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33735
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The printk has no effect as console_init() hasn't been called.
Also drop unused variables and headers.
Change-Id: I5bf5a8822c69bbcc3de1de460d19585b8330649f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
This string is printed in dump_te_table() so we should make sure it's
properly null-terminated.
This fixes Coverity issue 1401305.
Change-Id: I45827f552c2d8a4e01b50a699ac88ee457043282
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
By default, the LPC SIRQ mode is set to Quiet mode. Therefore, COM-port
from the SurerIO chip don't work correctly after the LPC controller (PCI
0:1f.0) initialization. Console output is broken. The patch fixes this
bug by overriding the serirq_mode option in the devicetree.cb to set
Continuous SIRQ mode
Change-Id: I37e26b271fb61f6c0343d6bf65c029924df82caf
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33801
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add files to introduce a memory clearing framework.
Introduce Kconfig PLATFORM_HAS_DRAM_CLEAR that is to be selected by
platforms, that are able to clear all DRAM.
Introduce Kconfig SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT that is user
selectable to always clear DRAM on non S3 boot.
The function security_clear_dram_request tells the calling platform when
to wipe all DRAM. Will be extended by TEE frameworks.
Add Documentation for the new security API.
Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Depthcharge no longer reads this data structure, and uses
the vboot workbuf in vboot_working_data instead.
Since vboot2 downstream migration is not yet completed, the
vboot2 -> vboot1 migration code is still required, but has
been relocated to depthcharge.
BUG=b:124141368, b:124192753
TEST=make clean && make runtests
BRANCH=none
Change-Id: I769abbff79695b38d11fb6a93c2b42f64d4bafde
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33535
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A FPMCU power-control pin (GPP_C11) is added to the latest
hatch reference schematic.
Even though this is not implemented in hatch rev1 board, the future
hatch family boards with FPMCU should all have this control pin.
On the old boards without this control pin, GPP_C11 is a floating TP,
and thus this patch should be backward-compatible.
BUG=b:130307667, b:135216932
TEST=build
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: I6a84eeb6aab562258e749a8a5d09dadfa0e43587
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is no need to add internal termination (PU/PD) on the
not-connected pads. This change gets rid of the terminations on the NC
pads.
Change-Id: I3df538d7127e5ef75e6e6ff9db3524e26f0450ed
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This allows to use Kconfig options to differentiate between SOC
variants.
Change-Id: Ica11c68377e3d0dc8a8f48198e01a74d7bebe642
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33559
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The value for that macro should be 1<<19. This is confirmed by the
Intel doc and also by N_PCH_GPIO_RX_SCI_ROUTE.
See Intel Atom® Processor C3000 Product Family Datasheet
(February 2018) :
https://www.intel.com/content/www/us/en/products/docs/processors/atom/c-series/c3000-family-datasheet.html
Signed-off-by: Patrick Havelange <patrick.havelange@essensium.com>
Change-Id: I808d9131032a9796d837e00ad6fb3369b792e597
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33573
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CBFS_SIZE equals size of whole SPI device.
The descriptor and ME need to be placed in bottom part.
Reduce the CBFS_SIZE to maximum avalaible size.
BUG=N/A
TEST=Boot Embedded Linux 4.20 on Facebook FBG-1701
Change-Id: Iecfae4573100c6787b6e8b1c4f2583a7fb3d95a3
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
tc348860_table contains the eDP to MIPI Bridge controller type.
b101uan08_table used the LCD Panel type.
Use LCD Panel type for name of tables.
Remove the incomplete resolution comments and specify the resolution at
the start of the table to 1200x1920.
BUG=N/A
TEST=Config eDP and verify LCD panels are working on Facebook FBG-1701
Change-Id: Ic152ea1f95f155ab76638b57a259d37ce6f43037
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33736
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It seems that the EC on t60/x60/z61t doesn't support it. This wasn't
even introduced in z61t so let's remove the remaining bits.
This commit follows up on commit a5fcc2e4 with Change-Id
Id2964002406a5fcf992f0ffc3627e3f66a2bb13f ("mb/lenovo/x60/t60: Remove
`fn_ctrl_swap` option").
Tested on a real hardware.
Change-Id: Ifd5e7823af305cc4a0194ee2097a749e43680c55
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Andrey Korolyov <andrey@xdel.ru>
Sometimes coreboot needs to compile external code (e.g.
vboot_reference) using its own set of system header files. When
these headers don't line up with C Standard Library, it causes
problems.
Create ctype.h header file. Relocate ctype.h functions from
string.h into ctype.h. Update source files which call ctype.h
functions accordingly.
Note that ctype.h still lacks five functions which are not used
in coreboot source:
isalnum, isalpha, iscntrl, isgraph, ispunct
BUG=b:124141368
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I31b5e8af49956ec024a392a73c3c9024b9a9c194
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested with SeaBIOS as a payload, booting Arch Linux with
a Linux kernel. The new code is based on autoport and the
existing GA-H61M-S2PV code.
The GA-H61M-S2PV has been boot-tested too, it still boots.
Working:
- S3 suspend/resume
- USB ports and headers (Intel USB2 and EtronTech USB3)
- Gigabit Ethernet
- Integrated DVI/VGA graphics (libgfxinit)
- PCIe x16 graphics
- PCIe x1 ports
- PS/2 port with a keyboard
- SATA controllers (Intel SATA2 and Marvell SATA3)
- User-space fan control (fancontrol on Linux)
- Native raminit (4+4GB DDR3-1333)
- flashrom, using the internal programmer. Tested with coreboot,
as well as with the vendor firmware. Backup chip is untested.
Untested:
- VGA BIOS for integrated graphics init
- Audio: Only front/read outputs has been tested.
- Non-Linux OSes
- ACPI thermal zone and OS-independent fan control
Not working:
- Default IFD defines the BIOS region as the entire flash chip.
Using 'flashrom --ifd -i bios' is asking for a failed flash!
Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The ifittool is used instead. Drop old code.
Change-Id: I70fec5fef9ffd1ba3049badb398783f31aefb02f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This patch relying on new rule, ENV_PAYLOAD_LOADER which is set
to ENV_RAMSTAGE.
This approach will help to add future optimization (rampayload) in
coreboot flow if required.
Change-Id: Ib54ece7b9e5f281f8a092dc6f38c07406edfa5fa
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
On RISC-V the argument to a payload is always the hartid and a pointer to a FDT.
selfboot sets the coreboot tables as an argument, work around this here.
Change-Id: If6929897c7f12d8acb079eeebaef512ae506ca8b
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31477
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fixes a logic error that sets MPIE, but didn't use mret to return to the payload.
This left MIE set to an undefined value.
Now all modes are handled the same way:
- Trap vector base address point to the payload
- Disable Interrupt
- Return to payload using mret
TEST=Run an M-mode payload
Change-Id: Iaab595f916949c57104ec00f8b06ea047fe76bba
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33462
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FBG1701 contains a TC358860 eDP to MIPI Bridge controller which needs
to be configured.
Add mainboard_configure_edp_bridge() to program the controller.
CPLD version is used to determine which table must be programmed.
The eDP is an i2c slave which expects the next i2c bus data for block
write:
<Slave Addr> <Reg Addr[15:8]> <Reg Addr[7:0]> followed by data with LSB
first.
BUG=N/A
TEST=Config eDP and verify LCD panels are working on Facebook FBG-1701
Change-Id: I262cb4376b86db94e3bb9522c556b5cc3ff38335
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The SUPERIO_NUVOTON_NCT6776_COM_A symbol should only be visible if
SUPERIO_NUVOTON_NCT6776 is selected as well.
Change-Id: I9c52d596080360bf3fc25265749ced66ec44f5dc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33440
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The asrock/h110m has a NCT6791D, but is selecting the NCT6776-specific
SUPERIO_NUVOTON_NCT6776_COM_A symbol. Use the NCT6791D symbol instead.
Change-Id: I9f3fde161844f919b070f2b6ce7e106411439a9a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <m.poliakov@yahoo.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Like the NCT6776, the NCT6791D has muxed COMA/GPIO8 functions. Since it
requires setting different bits, add a new Kconfig symbol to do it.
Change-Id: I62dc18810026f9b1550da19950f66af605600ec8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <m.poliakov@yahoo.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
ALIGN((a), b) and ALIGN_UP(a, b) needs 'helpers.h'
Change-Id: I029c7c5cbb19c7e69997b3d84f929cb61e8e2b23
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Enable decoding the IPMI KCS to LPC
* Select the IPMI driver
* Add the PNP device that holds the IPMI KCS base address
Tested on Wedge100s.
Change-Id: I35634bbcbe6893bd72ec7e41f6ca7bba09d819a2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Add chips ops for IPMI KCS.
* Get IPMI version over KCS.
* Generates ACPI SPMI table for IPMI KCS.
* Generates SMBIOS type 38 for IPMI KCS.
* Generates ACPI SPMI device for IPMI KCS on LPC device.
* Add documentation
To use this driver on BMC that support KCS on I/O:
1. Add an entry to the devicetree.cb:
chip drivers/ipmi
device pnp ca2.0 on end # IPMI KCS
end
2. Select IPMI_KCS in Kconfig.
3. (Optional) enable LPC I/O decode for the given address.
Tested on Wedge100s.
Change-Id: I73cbd2058ccdc5395baf244f31345a85eb0047d7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The ALIGN_UP macro is basically an alias of the ALIGN macro; with this change
it's more obvious in which direction the alignment happens.
Change-Id: I6f1b9f9bbcafeb85a6ef5c10ce4b57edc0740e72
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
This patch contains the rest of the fixes for this subtree; having one change
for every area would create an unnecessary amouint of patches.
Change-Id: Id92c11d58693292d58cba323c8468db858becfb5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33630
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ALIGN_UP is an alias for ALIGN.
Change-Id: Ie723ebe80f8f627021151413cb43adce6c88a0dc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33628
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Support SAMSUNG KMDP6001DA-B425 and MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X DDR
From the calibration log of MICRON MT29VZZZAD8DQKSL, we found
the begin pass range of RX window earlier than with other DDR type.
So need change the DQS starting offset to increase the scan range of RX window.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on EMCP DRAM
Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com>
The mode register setting of DRAM may fail without some
delay after each MR write.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly and stress test pass on Kukui.
Change-Id: I51785e90b2014994be5018bfe543245d44626242
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32284
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Garg proto build has 3 SKUs:
garg 2A2C DB: SKU ID - 1
garg HDMI DB: SKU ID - 9
garg LTE DB: SKU ID - 17
For SKU#9, VBT will need to be overridden to enable DDI_C output to HDMI
BUG=b:134912735
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
Cq-Depend: chrome-internal:1380847
Change-Id: I6c0ec086496eaf217ea8e326f5084d886d0e698f
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Make the linker script dynamic to support non default ROM sizes.
Prevents weird runtime issues due to stages overwriting parts of the
CBFS while decompressing stages.
Change-Id: I37b9187c719b907959f02a272ec0459aabbcda3c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
This code was copied from depthcharge which uses C99 comment style, but
coreboot uses C89 comment style. Update to match coreboot.
Change-Id: Ib67bb9ff17b7688826071453ab58894a0835ce10
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32875
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The compat string matching code was mostly copied from depthcharge. One
of the few differences is that we now store the list of compat strings
we're willing to match in a list rather than an array. Since our lists
insert at the front, that means the strings are now ordered lowest to
highest (not highest to lowest like in depthcharge).
We did rewrite the compat_rank matching code to accomodate for that...
however, what we didn't do is remove the break-statement in the loop
that matches all compat strings. When we search the lowest priority
first, we can't abort the search as soon as we found a match -- we have
to keep looking because we might find a higher priority match later.
This patch fixes the issue so that my Kevin can actually match for
google,kevin-rev5 (and doesn't just jump at the first best google,kevin
match).
Change-Id: Ibe3d84bbce6de3cd49c746a667ae1ccfdc843105
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32874
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support to boot FIT image configurations consisting of
a base device tree and one or more overlays. Since extracting the right
compatible string from overlay FDTs is problematic, we'll only support
this for FIT images that have the compatible string pulled out into the
config node.
This patch was adapted from depthcharge's http://crosreview.com/1555293
Change-Id: I0943f9a1869c9e416887c7ff16e33f7d91b74989
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32873
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support for compressing individual device trees in the
FIT image. In order to make this efficient, we'll have to pull the
compatible property out of the FDT and store it directly in the config
node of the FIT image, so that we don't have to scan (and therefore
decompress) every single FDT on boot. Device tree compression is only
supported for FIT images that have this external compatible property.
For older images with no compression, we still support fallback to
scanning the FDT for the property.
This patch was adapted from depthcharge's http://crosreview.com/1553458
Change-Id: Ifcb6997782c480c8ef6692df17b66ad96264e623
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32872
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kernel handoff on all architectures supporting FIT images already
includes flushing and disabling the cache. No need to waste any more
time flushing individual components (especially since in the case of
compressed DT overlays they will still get accessed again afterwards).
Change-Id: I7b483e920c5a71663b024b5b50804ffc84939830
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32871
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes some minor refactoring to the way the FIT parser
handles config nodes. A lot of this code was written in the dawn age of
depthcharge when its device tree library wasn't as well-stocked yet, so
some of it can be rewritten nicer with more high-level primitives.
There's no point in storing both the string name and the actual FDT node
of a FIT image node separately, since the latter also contains the
former, so remove that. Also eliminate code for the case of not having
an FDT (which makes no sense), and move some more FDT validity/compat
checking into fit_update_compat() (mostly in anticipation of later
changes).
This patch was adapted from depthcharge's http://crosreview.com/1553456
with a couple of modifications specific to coreboot's custom FIT loading
code.
Change-Id: Ia79e0fd0e1159c4aca64c453b82a0379b133350d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32870
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support for merging a device tree overlay (as defined in
Documentation/dt-object-internal.txt in the dtc repository) into a base
device tree. It was adapted from depthcharge's
http://crosreview.com/1536387.
Change-Id: Ibec833cd471201bcc7a79eebf360d5f12adb8ff9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32869
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is needed for SPI flash console in bootblock/romstage/postcar.
Change-Id: I18253cc028e87cd31879d722a6d788917e9c97b3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Code is based on microcode update procedure from fam10-15h with necessary
microcode blob structure updates for fam16h.
Currently updating microcode in romstage seem to be impossible. AGESA is
overriding the microcode patch regardles of the current microcode revision
patched on CPU. Use ramstage CPU init procedures to update microcode easily.
Tested with microcode blob 07030106 released 2018-02-09 from
platomav/CPUMicrocodes GitHub repository on apu2 platform.
TEST=boot Linux kernel 4.14.50 on PC Engines apu2 and run dmesg to see
patch_level=0x07030106 on all cores
Change-Id: Ic15cba06f3cd9cfbc538b6764b158fa699f0ecf6
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29272
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DIMM manufacturing ID was not being initialized and so the DIMMs
were not described in SMBIOS tables properly.
The module type can also be provided, but the SMBIOS code expects
SPD module type values from DDR2 so the DDR3/4 values are adjusted
before sending to SMBIOS.
BUG=b:134897498
BRANCH=sarien
TEST=dump and compare with dmidecode
BEFORE:
Type: DDR4
Manufacturer: Unknown (0)
Form Factor: Unknown
AFTER:
Type: DDR4
Manufacturer: Hynix/Hyundai
Form Factor: SODIMM
Change-Id: Id673e08aa6e3dad196009c3c21a3dda2f40c9e42
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As described in the comment, the BKDG-recommended algorithm causes
problems and isn't being used, so just delete it.
Change-Id: Ib3d4eba7ea2d7f6545613af5670b243bc011275f
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1347325, 1347326
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This function attempts to set bits in the 20s of state and state_save,
which won't work since those variables are only 16 bits wide. Extend
them to 32 bits to capture all the bit operations.
Change-Id: I5616a2d879a85ff5f57af5af20384516659c62d6
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1347384
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The literal needs to be cast to a uint64 to prevent num_nodes
from being implicitly promoted to a signed int.
Change-Id: Id2fa328fb8d0a9827c7c78157c024736e9b26dc4
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1347343
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Chengdu Haiguang IC Design Co., Ltd (Hygon) is a Joint Venture
between AMD and Haiguang Information Technology Co.,Ltd., aims
at providing high performance x86 processor for China server
market. Its first generation processor codename is Dhyana, which
originates from AMD technology and shares most of the architecture
with AMD's family 17h, but with different CPU Vendor ID ("HygonGenuine")
/Family series number (Family 18h).
More details can be found on:
http://lkml.kernel.org/r/5ce86123a7b9dad925ac583d88d2f921040e859b.1538583282.git.puwen@hygon.cn
Change-Id: I8af8b0f0675f978ac07522029696e43651a3153f
Signed-off-by: Jinke Fan <fanjinke@hygon.cn>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32876
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set up generic decode ranges based on the devicetree settings.
Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
What it really means to do is to use different FSP headers.
Change-Id: I3c75d4aac8525ab2639608fb9c1b3a9afef0e943
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Regarding 64 and IA-32 Architectures Software Developer’s Manual, the register
name of the msr at 0x35 is MSR_CORE_THREAD_COUNT.
Change-Id: I5134619dc3a42187ddd5f46c85873c4278229e27
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33015
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Files onboard.h and mainboard.h are not used for building.
Remove these files as include.
BUG=N/A
TEST=Build and boot embedded Linux 4.20 on Facebook FBG-1701
Change-Id: Ifeb0047357e641cbe1affbbaf5402213802c774c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Fix value of 1 is used for asl_compiler_revision.
Use asl_revision for this.
BUG=N/A
TEST=booting Linux 4.20 kernel on Facebook FBG1701
Change-Id: Iffd8fe637d4669b7099fb6eafc9873560502bf80
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
This does the following:
- select MAINBOARD_USES_FSP2_0 on Kabylake (does not support FSP1.1)
- Remove stale Kconfig option on intel/saddlebrook
- select SOC_INTEL_KABYLAKE on intel/kblrvp
Change-Id: I64f48eeb00150aea039d533b0ac471fdd8483b90
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is never used.
Change-Id: I414acc38f72e206eb48cfd98214985c320862c91
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Increase the size of bootblock from 96K to 128K.
Change-Id: Ifc6e7239ed2978a8490fa229945ebd5ed9182298
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33159
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is already an external pull-up/down resistor tied to
this pin to identify if the board is single-channel or
dual-channel memory SKU.
BUG=b:135496271
BRANCH=none
TEST=build
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: Ie218657fd9dde113ab26cf5551d1dff1b6e392b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
I increase the size oof the postcar stack to prevent a stack overflow
during the measured boot feature. After common string functions have
been moved from inline into .c file
(https://review.coreboot.org/c/coreboot/+/32901), I experienced a stack
overflow in the postcar stage while verifiying the romstage during
measured boot. To prevent this, the stack size should be increased. To
play it safe, it should be increased to 8 KiB - though this is open for
discussion.
Change-Id: I6f1a4631bcadfb8c7d1de5bf0919e40990a65606
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This copies the makefile code from the smm/smm.o.
Now works with clang version 7.0.1 from my OS using
CONFIG_ANY_TOOLCHAIN.
Change-Id: I298d24d54b8fb27da96257ccda65b7fbee988ebb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30504
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The correct address for vproc12 register of sw mode is 0x1426 instead
of 0x140a.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui and see that regulator is not stuck to
1.05V anymore:
grep vproc12 /sys/kernel/debug/regulator/regulator_summary
Change-Id: I13867b11c44019875e0ed607343197950a3b38b2
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33168
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code to handle the brightness from SMM is copied from the Lenovo
Thinkpad X60 code, but does not work on later generation. The PCI
device it tries to address does not even exist on those devices.
Change-Id: I0c25c3e5bec651b27158a84cc91289639a04ceb6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Those are copied from Lenovo X60 code, but are unused.
NOTE: No ACPI C-state are generated on this platform but Linux has a
separate driver for that.
Change-Id: Ie9b49f5451d8cde9c36672cac1f0f14cb3f0095e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33140
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TODO: There is no reason to do this in SMM.
Change-Id: I8bbb2f65bbe674bd1bc4ae8a4086bd1f5e9a79fa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33139
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
tss_marshaling.c and tss.c depends on VBOOT for postcar.
Eltan vendorcode used function in these file, but has VBOOT disabled.
Remove depency of VBOOT for postcar fo tss/tcg-2.0/tss-marshaling.c and
tss/tcg-2.0/tss.c
BUG=N/A
TEST=Created binary and verify logging on Facebook FBG-1701
Change-Id: I195c79283abf403208f406518372bf52289772ed
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add infra group DCM (Dynamic Clock Management) settings,
which slows down OR gate clocks while hardware is in idle state.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui.
Change-Id: I4741dfb7b984deb92171f370e5fb2593829d74c2
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
The upstream vpd_decode.c has been revised to prevent overrun of decoded
contents.
BUG=chromium:967209
TEST=select VPD config on kukui; make; boots on at least kukui boards.
Change-Id: I1a50670a66b7b174d2a432c29d90152b86c32982
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Switch the default clock output for single LVDS mode to odd bus only.
Change-Id: I278e761566a112d95cbd6c79e09c076d70b93e8f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch enables TPM on SPI and adds the needed devicetree entry for
mc_apl5.
TEST=Build coreboot for mc_apl5 board and check the TPM console output.
In addition the TPM was correctly verified by our Linux driver.
Change-Id: Iafc967c7a2bfee9bdb9b6591d12328620e2887cc
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33173
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase SPI flash speed from 26MHz to 56MHz and set correct tick_dly
to get faster boot process.
BUG=b:80501386
BRANCH=none
TEST=emerge-kukui coreboot; emerge-elm coreboot
Change-Id: I8f44883b4f4a198146330caf5420dc39d5592a0a
Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32462
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable RTC so that we can see correct timestamp in CrOS eventlogs.
BUG=b:134461866
TEST='mosys eventlog list' shows correct timestamp on Kukui
Change-Id: Ie9ef7c9343c781e348429cd5376a4a5519641e16
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
We need to support RTC in ramstage so that we can see correct timestamp
in ChromiumOS eventlog.
BUG=b:134461866
TEST='mosys eventlog list' shows correct timestamp on Kukui
Change-Id: Idb0fe5c05e4ecdf0e6398e3c781c71d14f85f19b
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The values from auxadc may be incorrect if not calibrated by efuse.
Without calibration, the value error range is about +/-50mv,
and after being calibrated the error range is about +/-10mv.
BUG=b:131391176
TEST=make clean && make test-abuild; boots on Kukui rev 2 units.
BRANCH=none
Change-Id: Iccd6ea0ad810c993f9b62c0974279c960f890e52
Signed-off-by: Po Xu <jg_poxu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32800
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: JG Poxu <jg_poxu@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust FMAP sections that
- ELOG only needs 4K (by driver limitation)
- SHARED_DATA only needs 4K or less (for netboot params)
- SMMSTORE is probably not needed since UEFI@ARM is not available yet
- VPD can be smaller (most x86 devices have only 16/8K for RO/RW)
- Increase RW_LEGACY to 1M (recommended value)
- Move all new saved space to CBFS
BUG=b:134624821
TEST=Built Kukui image and boots on Rev2 units.
Change-Id: Id2910df73ea47bfa32e056d631d1c3e5f1eed0d1
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
'else' is not needed after a 'break' or 'return'.
Change-Id: Ib3371ef6edb85a47ed734dd2ff9ce94008aa4e65
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33336
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Vlado Cibic
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Free the tree before returning to prevent a leak.
Change-Id: I1132c0e7404eec1af3adc19a83257f28563f8a58
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1401799
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Coverity believes there is a path where StdHeader is possibly
null. This *should* be incorrect, since the header is actually
initialized through the module dispatch framework, though Coverity
can't see it due to the extensive type-punning. However, the control
flow is so dizzingly complicated that I'm not even completely sure,
so adding an extra assert to be careful won't hurt anyway.
Change-Id: If3d7c5d5c5bba846e7453b3dbc824e2208d749fb
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1379932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The case when Speed == 5 is already dealt with on line 111.
Change-Id: Icc41c00fb333a51001568f588c17f7b6c6a3a923
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229626
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This check is already performed at the beginning of
dct_ddr_voltage_index().
Change-Id: Ia73025333c152f14249afb16d05f66791e69e7cb
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1347322, 1347323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This conditional is exactly the same as the one right below it, except
the operations are reorganized slightly.
Change-Id: I00c19a467d23a0736bc2a33b516f97080039e634
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1347321
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Logging and clearing the recovery mode switch doesn't have
anything to do with vboot_handoff. Move it to the main verstage
logic file.
BUG=b:124141368, b:124192753
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I2e74f3893463e43fe5fad4a8df8036560f34e0db
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
These functions are no longer used and may be removed:
* vboot_handoff_check_recovery_flag
* vboot_get_handoff_flag
BUG=b:124141368, b:124192753
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Ie05652ef1288eef74bd2e7e8bea79fd29d523859
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33533
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Two functions retrieve vboot recovery_reason:
* vboot_handoff_get_recovery_reason
* vboot_get_recovery_reason_shared_data
Previously, when CBMEM comes online, a vboot_handoff data
structure is created, and depending on the architecture,
coreboot may eventually lose access to vboot_working_data.
After implementing vboot_working_data CBMEM migration,
vboot_working_data is always guaranteed to be accessible.
vboot_get_recovery_reason_shared_data is corrected to also
allow accessing vboot_working_data in ramstage and postcar.
Now, vboot_handoff_get_recovery reason returning a valid recovery
reason implies that vboot_get_recovery_reason_shared_data should
*also* return a valid recovery reason. Thus we may remove the
former.
BUG=b:124141368, b:124192753
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Iac216dc968dd155d9d4f8bd0f2dfd5034762f9a0
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The default voltage of vsim2 is set to 2.76V for sim card usage.
In general, 2.76V of vsim2 is composed of 2.7V main voltage and 0.06V calibration voltage.
However, vsim2 is used for the tx_ovdd power of display port IT6505 on the kukui board design which needs 2.7V.
So we set it to 2.7V with modifying calibration value.
BUG=b:126139364
BRANCH=none
TEST=measure vsim2 voltage with multimeter
Change-Id: I4dffdde89cbde91286d92e6c2b445f0b3d0ad2fe
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Intel Braswell supports i2c block writes using SMBus controller.
This support is missing in actual smbus routines.
Add do_i2c_block_write() which is a based on do_smbus_block_write() but
also write first byte to SMBHSTDAT1.
The caller needs to configure the SMBus controller in i2c mode.
In i2c mode SMBus controller will send the next sequence:
SMBXINTADD, SMBHSTDAT1, SMBBLKDAT .. SMBBLKDAT
To ensure the the command is send over the bus the SMBHSTCMD register must
be written also
BUG=N/A
TEST=Config eDP for LCD display on Facebook FBG-1701
Change-Id: I40f8c0f5257a62398189f36892b8159052481693
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Hatch newer board revision do not use USB port5 for discrete BT.
Hence remove the port configuration and UBS2 P5 asl entry. The older
board version would continue to use USB2 P5 hence moved the entry to
overridetree.cb
Change-Id: I98297d6b81e3184b7b0a14710f3790f5df30d68b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This patch configures FSP UPD values for HPD and DDC of DDI ports for
WHLRVP.
BUG=none
TEST=Tested that eDP & DP works on WHLRVP
Signed-off-by: Usha P <usha.p@intel.com>
Signed-off-by: sridhar <sridhar.siricilla@intel.com>
Change-Id: I576469f5564e3e56159762752dbe4557e9dc1912
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33435
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
LONG_FADT is not used at all. So remove it and use sizeof(acpi_fadt_t) for
header length.
Change-Id: I433d1b2e0f3b9505d7c52eb14f1a476fbe52a284
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
The clock was previously set to 52MHz to workaround the fact that
depthcharge didn't support tuning.
Tuning has now been enabled in depthcharge:
https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/1655553
BUG=b:122244718
TEST=Verified on grunt that it speeds up boot by 130ms
Change-Id: If847cea2a7848bcd175958db86e652d4f710201a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit follows up on commit commit 89989cf6 with Change-Id:
I1f44ffeb54955ed660162a791c6281f292b1116a ("src: Drop unused include
<arch/acpi.h>").
Change-Id: I3dc12373b32b95d25ba7b302cbca5f927678315d
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33365
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit follows up on commit 8b7a1614 with Change-Id:
I73c557d6ef009fb2cac35fdea500dee76f525330 ("src/mainboard: Remove
unneeded include <arch/io.h>").
Change-Id: I7f307bf5b6cdcfebe1a290ce344b962fcecc8781
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Change the SMBIOS Version from 2.7 to 2.8. Necessary changes were
already pushed in https://review.coreboot.org/c/coreboot/+/33031
Change-Id: I237cdee7d43e814397b958e4cf941bf58949088d
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Print I2C SAR device info so that it is available in cbmem logs.
BUG=none
BRANCH=none
TEST=Boot up and check cbmem -c can find the SAR I2C info
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia143932bb660ed2c2cea76310f11ede2b727adf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33432
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
data &= !BIT0 will clear data, since !BIT0 evaluates to 0 (oops). We
only want to clear bit 0, not the whole thing, so use bitwise negation
instead.
Change-Id: I2179119e0d2d4aceaf4f8b499bf4c5baf4ef677f
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1241812
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This was done to update the global variable g_ichspi_lock but this is
now removed in favor of reading the lock bit during runtime instead of
keeping track of the state.
Change-Id: I8cb69a152b0e050d64d8979ee92de2d24136f8dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33390
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SPI swseq controller can be locked in other parts of the code, for
instance when it's locked down in the finalize section. The driver
has to be made aware of that. The simpler solution is to not keep
track of the state and simply read out the lock bit on each SPI
transfer.
Change-Id: Ifcd5121b89d6f80fc1c1368786982d0d9fa1bf61
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We had a value that was overloaded thrice.
By moving them in a common structure and ordering them by value such
issues are hopefully avoided in the future.
Also add a few values to libpayload that were only defined in
commonlib.
Change-Id: I227d078eebee2d92488454707d4dab8ecc24a4d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32958
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Set abort command define
* Set debug level to SPEW
* Support zero length data packet in ipmi_kcs_send_message
That's required for commands like GET_DEVICE_ID, which have no
additional data to send.
* Read reply even if given no receive buffer
* Prevent buffer overflow in read reply processing
Tested on Wedge100s.
Change-Id: Iefddd88a744c3b96751d3fe8c2951ca2115548ce
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33488
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The temperature delta between on-board thermistor and
surface temp change, so update DPTF parameter accordingly.
BUG=b:113101335
TEST=Tested in thermal chamber by thermal team.
See comment 148 / 153 in the bug.
Change-Id: Ie18be94fc1e7476755fb0e6947cce559854a82dd
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
The sandybridge systemagent-r6 blob is modified:
- To be more flexible about the location of the stack w.r.t. the heap
- Place the MRC pool right below the MRC_VAR region
- to work with the same DCACHE_RAM_BASE from the native raminit (could
make the CAR linker symbols easily compatible if desired)
This allows CAR setup compatibility between mrc.bin and native
bootpath and also allows for BIOS/memory mappeds region larger than
8MB.
This changes the semantics of CONFIG_DACHE_RAM_MRC_VAR_SIZE to also
include the pool on top of MRC_VAR region.
TESTED on T520 (boots and resumes from S3 with mrc.bin).
Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33228
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix 'do not use assignment in if condition'.
Change-Id: I6e1b81a1b87de4315391618968c59cc3d3a66a77
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move the memory strap gpios to variant/gpio.h, as the memory straps
are different for helios.
Change-Id: I1833c9539687011ee27fd3e88c0581e30ca59354
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
All usage of pci_read_config8 was removed in commit d44d4f0f with
Change-Id Ia959eb5b747846048396e66d4c926c96c27f3878 ("mb/lenovo/*:
Remove useless smihandler code"). So we don't need this include anymore.
Change-Id: Ic4f038c80e17799016ae7e92a5675cfe7c71e400
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This patch ensures to boot platform without onboard GFX (PCI B0:D2:F0)
enabled from mainboard devicetree.cb.
TEST=Previously platform was dying at "GMADR is not programmed!" with
IGD disabled.
Change-Id: I8c907ee25db4538a84890f2ccc3187afa86604b8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33449
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Selecting which cbfs prefix to load is only implemented with the romcc
bootblock.
Change-Id: I09523b94605f00ab15b5f0ea3986ac08e3a6afc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
"if (_pcidata != 0xFFFFFFFF || _pcidata != 0)", is always true.
The right test should be && not ||.
Error found using -Wlogical-op warning option.
Change-Id: I537fa4867499e1e6e5f662086fabc99b91aa0c70
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
These if statements can be combined to merge the two branches of the
conditional and remove the duplicate pDCTstat->Speed == 3 check.
Change-Id: I41aa19b4b7ed7b1a0e4f83f72e66869760e677dd
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229583
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Helios has a number of GPIO changes w/r/t to its baseboard.
Override early, sleep and normal GPIOs as appropriate.
BUG=b:135257452
BRANCH=none
TEST=Compile only (no boards to test with)
Change-Id: I45793ad6515df5af5b925d92106bd943374353d4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change tcc offset from 0 to 10 degree celsius for bloog.
BUG=b:135225497
BRANCH=octopus
TEST=Build and verify test result by thermal team.
Change-Id: I4cbff846914a776c67692005f8b40cd73cfaf231
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Memory id's are 1-indexed for DDR4, so we need to check that the SPD
index is non-zero before converting it to the 0-indexed value in the
bitmap.
Change-Id: Icc542239d91c39b89c23f31856c28e7c20b2fc4d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1387028
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Rather than force the user to create the RW_MRC_CACHE FMAP region,
simply select CACHE_MRC_SETTINGS so it's done automatically for them.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: Iaa1da6015c1bfafe8ea81ca34ef8851f0c689487
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The gpio_key wakeup_event_action in the ACPI tables was backwards, causing
devices to wake up on pen insertion instead of removal. Changed to
EV_ACT_DEASSERTED.
BUG=b:134547896
BRANCH=none
TEST=Verified in OS, device only wakes up on pen removal
Change-Id: I0816ed9fb23cf00fd8e40bcdd25ff7a9f48badbd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33427
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the SPD makefile to use the LPDDR3 SPDs. Set up the arrays
for mapping SoC DQS pins to LPDDR3 pins.
BRANCH=none
BUG=b:133455595
TEST=`FEATURES="noclean" FW_NAME="helios" emerge-hatch chromeos-ec
depthcharge vboot_reference libpayload coreboot-private-files
intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`
Ensure the firmware builds without error.
Change-Id: Iebaba2ec65dfcf36674b4733b421ada107b22b09
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33456
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We are seeing an EC interrupt after setting the EC RAM offset that
indicates that the EC should transition to S0ix mode and this is
preventing the kernel from going into S0ix on the first try.
As a workaround if we read back from the EC RAM while still in the
_DSM handler it seems to prevent this problem.
BUG=b:130644677
BRANCH=sarien
TEST=ensure s0ix entry works on the first try with sarien
Change-Id: Id607c4c2b14b79d0cd1bcea0c2032be2f2c0c141
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33455
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These 4 GPIOs are being disconnected in the next board so use the
board ID to configure these pins as not connected to ensure
they do not cause leakage.
Also remove the ACPI _PTS S5 code that was configuring the GPIOs.
This does mean they will cause small leakage in S5 on existing boards,
but it will not affect the new boards.
BUG=b:132393441
TEST=boot on sarien with fake board ID and ensure that coreboot
configures these pads as expected.
Change-Id: I6ac04b9a635829811a09aeab7cba3bb58cfcff47
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
These two functions try to access arrays of lengths 32 and 64 at indices
of at most 259 and 71 (respectively). Something here is seriously wrong.
This code was introduced in 2007, and aside from cosmetic changes, has
had no modifications since then. I don't know what this code is supposed
to do, and asking around on IRC, no one else did either. Until someone
has the interest and time to work on it, let's at least add a die() to
prevent the out of bounds access and alert the user that something is
wrong.
Change-Id: I5fc15a50a9f0e97add31e3a40da82a15f7427358
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 12296{79-82}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch is not actually disabling HECI1 as it requires a dedicated FSP UPD
for WHL/CML SoC code to set this HECI1 chip config.
Change-Id: Ia88f3315a9dc3365d0acc13ed887e7c596c97c91
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch provides an additional option to skip HECI function
disabling using SMM mode for WHL and CML platform, where FSP has
dedicated UPD to make HECI function disable.
User to select HECI_DISABLE_USING_SMM if FSP doesn't provided dedicated
UPD.
Right now CNL and ICL platform will use HECI_DISABLE_USING_SMM kconfig
to make HECI disable and WHL/CML has to rely on FSP to make HECI
disable.
Change-Id: If3b064f3c32877235916f966a01beb525156d188
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI,
hence modify SoC code to reflect the same.
This patch replaces all SoC specific PCI LPC references with ESPI
except anything that touches intel common code block.
Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available.
Enable support and add required files for the Braswell Bootblock in C.
The next changes are made support C_ENVIRONMENT_BOOTBLOCK:
- Add car_stage_entry() function bootblock-c_entry() functions.
- Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE.
- Add bootblock_c_entry().
- Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init()
Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init()
BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701
Building Google Banos
Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Recovery path should finalize work context, and trim
vboot_working_data buffer_size. Otherwise, depthcharge ingests
the full 12 KB workbuf in recovery path.
BUG=chromium:972528, b:134893812
TEST=Build with vboot_reference CL:1584488. Check that USB disks
are properly verified in recovery path.
BRANCH=none
Change-Id: Icf2600d2eb5d846a26aec35a153946dd2f7f128c
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Disable dynamic clock gating for the community cr50's IRQ lives on.
That IRQ is pulsed very quickly, and with clock gating enabled pulses
tend to be missed. This is expecially true on the default 0.0.22
firmware that cr50 comes with out of the factory.
BUG=b:130764684 b:130338605
BRANCH=None
TEST=Boot hatch with cr50 "intap" firmware that can vary the pulse width,
observe that even with sub-microsecond pulses no IRQs are missed.
Change-Id: I34d14fb7cc97e33eecfda2c99cc53a541c87662d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
It was determined through testing that 16MB of reserved VRAM is
sufficient. Additional RAM for the graphics driver is allocated out
of system memory.
BUG=b:123579702
TEST=Boot Grunt, watch VRAM usage with graphics driver logging.
Change-Id: I44b640f015b45c0dc3d701929549f3a1082a9268
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33368
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The prototype of vprintk() is currently declared unconditionally, which
prevents it from being used in situations where the console is disabled.
The code will compile correctly, but not link, since the definition in
console.c isn't being provided. This adds a shim around the declaration
so that, like printk(), a call to vprintk() in this situation will expand
to a no-op function instead.
Change-Id: Ib4a9aa96a5b9dbb9b937ff45854bf6a407938b37
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
die() currently only accepts a fixed message string, which is rather
inconvenient when there is extra information that would be helpful to
print in the error message. This currently requires an extra call to
printk(), which is somewhat awkward:
printk(BIOS_EMERG, "Bad table, opcode %d at %d", id, i);
die(""); // what do I say here?
die() already has a printk() inside it to print the error message, so
let's just make it variadic to combine the two.
die("Bad table, opcode %d at %d", id, i); // much better
Forwarding variadic arguments from one function to another is rather
tricky, so die_with_post_code() is redefined as a variadic macro
instead.
Change-Id: I28b9eac32899a1aa89e086e0d3889b75459581aa
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
This patch removes all possible dependencies in order to build platform
with CONFIG_RAMPAYLOAD enable(without ramstage).
A. Create coreboot separate stage kconfigs
This patch creates seperate stage configs as below
1. HAVE_BOOTBLOCK
2. HAVE_VERSTAGE
3. HAVE_ROMSTAGE
4. HAVE_POSTCAR
5. HAVE_RAMSTAGE
B. Also ensures below kconfigs are aligned with correct stage configs
1. COMPRESS_RAMSTAGE and RELOCATABLE_RAMSTAGE are now enable if
CONFIG_HAVE_RAMSTAGE is selected.
2. COMPRESS_BOOTBLOCK will enable if CONFIG_HAVE_BOOTBLOCK is set
3. COMPRESS_PRERAM_STAGES will enable if CONFIG_HAVE_VERSTAGE
|| CONFIG_HAVE_ROMSTAGE is selected.
C. Also fix compilation issue with !CONFIG_HAVE_RAMSTAGE
On x86 platform:
Case 1: ramstage do exist: CONFIG_HAVE_RAMSTAGE=1
>> rmodules_$(ARCH-ramstage-y) will evaluate as rmodules_x86_32
Case 2: ramstage doesn't exist: CONFIG_HAVE_RAMSTAGE=0
>> rmodules_$(ARCH-ramstage-y) will evaluate as rmodules_
This patch fixes Case 2 usecase where platform doesn't select
CONFIG_HAVE_RAMSTAGE.
Also add option to create sipi_vector.manual based on $(TARGET_STAGE)
variable.
$(TARGET_STAGE)=ramstage if user selects CONFIG_HAVE_RAMSTAGE
$(TARGET_STAGE)=postcar if user selects CONFIG_RAMPAYLOAD
Change-Id: I0f7e4174619016c5a54c28bedd52699df417a5b7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a method for the soc/amd/<product> to indicate what AcpiMmio
ranges are supported. Induce a build error if soc or mainboard
code is added which attempts to use an unsupported block.
This patch attempts to dissuade accessing unsupported blocks without
requiring the complexity of structures or reinitializing at the
beginning of a new stage.
TEST=boot grunt, force build errors by removing blocks in iomap.h
BUG=b:131682806
Change-Id: I2121df108fd3caf07e5588bc3201bcdd8dcaaa00
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
This patch adds support for the Dual SPI feature (SDR 2-bit in Qualcomm
terminology) to the QSPI controller.
Change-Id: I7aed2ccd9627f5de5dd760b418f74d56d2c031d3
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33284
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support to read SPI flash in Dual SPI mode, where both
MISO and MOSI lines are used for output mode (specifically Fast Read
Dual Output (0x3b) where the command is still sent normally, not Fast
Read Dual I/O (0xbb) whose additional benefit should be extremely
marginal for our use cases but which would be more complicated to
implement). This feature needs to be supported by both the flash chip
and the controller, so we add a new dual_spi flag (and a new flags field
to hold it) to the spi_flash structure and a new optional xfer_dual()
function pointer to the spi_ctrlr structure. When both are provided,
Dual SPI mode is used automatically, otherwise things work as before.
This patch only adds the dual_spi flag exemplary to all Winbond and
Gigadevice chips, other vendors need to be added as needed.
Change-Id: Ic6808224c99af32b6c5c43054135c8f4c03c1feb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
All SPI flash chip drivers currently in coreboot use the generic read
functions (spi_flash_cmd_read_fast()/_slow()) as their read callback.
The only use case for specialized read callbacks we have left is with
specialized flash controllers like Intel fast_spi (which sort of
impersonate the flash chip driver by implementing their own probe
function).
This patch unifies the behavior for all normal flash drivers by making
the read callback optional and letting them all fall back to a default
read implementation that handles normal fast/slow reading. Most of the
drivers used to install the respective callback after checking
CONFIG_SPI_FLASH_NO_FAST_READ, but some hardcoded either slow or fast
writes. I have found no indications for why this is and spot-checked
datasheets for affected vendors to make sure they all support both
commands, so I assume this is just some old inaccuracy rather than
important differences that need preserving. (Please yell if you
disagree.)
Also take the opportunity to refactor some of the common spi_flash.c
code a bit because I felt there are too many nested functions that don't
really do enough on their own, and centralizing stuff a bit should make
it easier to follow the code flow. (Some of this is in preparation for
the next patch.)
Change-Id: I2096a3ce619767b41b1b0c0c2b8e95b2bd90a419
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch changes the Gigadevice SPI flash driver to adopt the same
structure packing improvements for the hardcoded parameters of
individual chips that was implemented for Winbond last year. This cuts
the size of the hardcoded info nearly in half and should save us a few
hundred bytes in every stage.
Change-Id: I9910dcb9b649f51b317f3f8fcba49e5e893f67d2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The SPI transfer speed logging in cbfs_spi is super useful, doesn't get
in the way (just adding one line per stage, essentially) and should have
no notable overhead. Let's enable it by default for the BIOS_DEBUG log
level rather than having to recompile to get it.
Also fix an issue with building this code on MIPS due to lack of 64-bit
division primitives. (This means MIPS and arm32 board may display
incorrect results when reading more than 4MB in a single transfer, which
sounds very unlikely.)
Change-Id: I03c77938afe01fdcecf917e8c4c25cc29cdc764e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support for generating IndexField, which is similar to Field.
Change-Id: If66a627e64953696b0b68488256bd5c141e4c205
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33032
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
One variant is asking for support for 16G 2666 LPDDR3, so adding
generic SPD for that.
BUG=b:133455595
BRANCH=None
TEST=None as this is not being used yet
Change-Id: If16a101119aabc30d6ea83e95e9ded2e089a982d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
One variant is asking for support for 8G 3200 DDR4, so adding generic
SPD for that.
BUG=b:132920013
BRANCH=None
TEST=None as this is not being used yet
Change-Id: I89cd3287aaf0baf384c4fe82d0881b0c48e09753
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33258
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Skip GT specific programming in coreboot to support early
parts without GT enable.
Change-Id: I231e13367cbfbafbfb0cb4235487dbcbcae76820
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33189
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The RAMPAYLOAD symbol added by 7e893a02c0 (Kconfig: Create RAMPAYLOAD
kconfig) is shown unconditionally for all x86 systems. It generally
creates a lot of confusion to prompt for something that isn't imple-
mented or not working. So guard it with another Kconfig that can be
selected by platforms that actually support it.
Change-Id: I6d158382d1000b8b40ca1368e2efff0c39884f15
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33263
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Select ONBOARD_VGA_IS_PRIMARY in driver/lenovo/hybrid_graphics to fix
disabling iGPU in 'Dual Graphics' on Lenovo T430.
* Remove ONBOARD_VGA_IS_PRIMARY in mainboards that already select
DRIVERS_LENOVO_HYBRID_GRAPHICS.
Change-Id: I6594fbb957c9a8135fe670d38b5755adf29d2dff
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Move the contents of iommu.c to early_init.c.
* Name the functions like done in intel/soc/common.
* Move PAMx register setup to own function
Preparations for integration in soc/intel/common/*
Tested on Lenovo T520 (Intel Sandy Bridge).
Still boots to OS, no errors visible in dmesg.
Change-Id: I3ec395bf6722bceb84316e92733dcfcd7a093639
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32068
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the Return statement within the PS0, PS3 methods. PS0/3 are not
allowed to return anything. Even an empty return will be resolved to
Return(Null). In order to be conform with the specification, the code
has been refactored to remove the return statements.
Change-Id: I7b4820e8dd40a9169a7facce67282b8af5af67af
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33293
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Skylake C236 to the PCH Table. The one which was already in there is
actually the CM236 and not the C236. This can be checked in datasheet:
100-series-chipset-datasheet-vol-1 p. 25.
Change-Id: I435927f15e9d3219886375426b09c68632dfe3d9
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change adds support for the UCSI specification in order to
provide information about the Type-C port and an interface to
perform power and data role swap.
This change is split across the DSDT and SSDT, with the shared
memory and operation region declared in the SSDT after being
allocated in CBMEM.
The OS will fill in the registers in the system memory region and
then call the _DSM method wtih a read or write argument. The DSM
method will copy the required registers to/from the system memory
and the EC and perform the write or read action.
Responses from the EC will generate a new SCI with event code 0x79
which will notify this UCSI ACPI device and the OS driver will take
action to read status from the EC.
BUG=b:131083691
Change-Id: I438a2bdfaf6720acd8354e0339dcef2844b63a4e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The USB Type-C Connector System Software Interface (UCSI) defines a
required memory oregion for the OS UCSI driver to use to communicate
with the BIOS and EC.
This provides a CBMEM ID that can be used by drivers to allocate this
shared memory region for the UCSI driver to use.
BUG=b:131083691
Change-Id: Id5b7fa19436443bc11a6ebe3ce89cd552cee4d85
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The SD controller seems to take some time after restarting
the clock at 1.8V before it actually switches from 3.3V to
1.8V. Add a _DSM method that simply sleeps when switching
between 3.3V and 1.8V. Otherwise, the kernel times out too
quickly waiting for the card to acknowledge the 1.8V switch.
The card itself is waiting until it sees the clk signal being
driven at 1.8V.
BUG=b:125441242
TEST=Boot Hatch with SD card and CR2 removed, observe voltage
switch succeeds.
Change-Id: I15090ed9f9bc90b35dfcba47c913e3d37b799d0b
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signef-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
These are documented in the Intel Datasheet entitled
"6th Generation Intel® Processor Datasheet for S-Platforms"
"6th Generation Intel® Processor Datasheet for H-Platforms" (Volume 2)
Without them, coreboot fails to properly inform the payload of the
amount of available memory.
Signed-off-by: Keno Fischer <keno@juliacomputing.com>
Change-Id: I5b810c6415c4aa0404e5fa318d2c8db292566b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The values are generated from the respective VBTs.
Change-Id: Ic74e9dac898c17ce64a94b06682997a39daeff69
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30247
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Logs from Linux' i915 suggest that not even the FSP/GOP takes proper
care of this. The sequence is mostly the same as on older platforms,
with a slightly different configuration of the backlight PWM.
We light the panel up with 50% PWM duty cycle. This often results in
an already rather high perceived brightness, but shouldn't be too
blinding.
Change-Id: I762a77c8df023a4c14af502af5edfeeb961da1ae
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Modify the 16 and 32 bit BIOS RAM access functions that had been
originally moved from stoneyridge. This was suggested in the
review of
69486cac7: Create AcpiMmio functionality from stoneyridge
Change-Id: I5b491da6f263cbab2b549301e16a7e19896f2428
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32932
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Document the AcpiMmio individual blocks better. This is in response
to a request in gerrit for
69486cac7: Create AcpiMmio functionality from stoneyridge
Correct comments that were inadvertently left in place from older
patches.
Change-Id: I4c16a866de5622e8cfbd3a08816b9d3182950d0e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32931
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable VBOOT MIGRATE_WORKING_DATA so that the data
required by depthcharge is copied into the coreboot tables
and made available to depthcharge after BOOT_IMEM is cleansed.
Change-Id: I0317b73d24b07553672695998589f86677e0be64
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Kane Chen