Commit Graph

39579 Commits

Author SHA1 Message Date
Huayang Duan c43e989966 soc/mediatek/mt8192: Do dramc duty calibration
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-31 03:07:52 +00:00
Huayang Duan 2d0117e2fe soc/mediatek/mt8192: Add dramc 8 phase calibration
To get better PI linearity, perform 8 phase calibration to do
MCK 0/180/45 training and select the best PI settings.

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: Ib4ccaa8d43b8382cbc64cf82de86ad1ac16cb89a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-31 03:07:37 +00:00
Huayang Duan 4cb885e5be soc/mediatek/mt8192: Update initial settings of dramc
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I08326cd1e6f7415d3a91d1591678e1b2c52c6781
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-31 03:07:16 +00:00
Matt DeVillier c6589aefc1 drivers/intel/gma: Include gfx.asl by default for all platforms...
which select INTEL_GMA_ACPI. Rework brightness level includes and
platform-level asl files to avoid duplicate device definition for GFX0.

Include gfx.asl for Skylake/Kabylake, since all other soc/intel/common
platforms already do. Adjust mb/51nb/x210 to prevent device redefinition.

Some OSes (e.g. Windows, MacOS) require/prefer the ACPI device for
the IGD to exist, even if ACPI brightness controls are not utilized.
This change adds a GFX0 ACPI device for all boards whose platforms
select INTEL_GMA_ACPI without requiring non-functional brightness
controls to be added at the board level.

Change-Id: Ie71bd5fc7acd926b7ce7da17fbc108670fd453e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-30 16:35:36 +00:00
Matt DeVillier 5cf4c87da7 soc/intel/common: Move gfx.asl to drivers/intel/gma
Adjust platform-level includes as needed.

Change-Id: I376349ccddb95c166f0836ec1273bb8252c7c155
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-30 16:35:21 +00:00
G.Pangao 142e6f5ecf soc/mediatek/mt8192: eint: unmask eint event mask register
eint event mask register is used to mask eint wakeup source on mt8192.
All wakeup sources are masked by default. Since most MediaTek SoCs do
not have this design, we can't modify the kernel eint upstream driver to
solve the issue 'Can't wake using power button (cros_ec) or touchpad'.
So we add a driver here to unmask all wakeup sources.

BUG=b:169024614

Signed-off-by: G.Pangao <gtk_pangao@mediatek.com>
Change-Id: I8ee80bf8302c146e09b74e9f6c6c49f501d7c1c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46409
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-30 06:04:10 +00:00
Matt DeVillier 4b9b44696d payloads/tianocore: Clean up build string
Extract the architecture (-a) and package (-p) options into a
new variable (ARCH) to simplify the construction of BUILD_STR.

Test: build/boot various boards w/Tianocore payload

Change-Id: I490d48428ac56d613d0b704700dfcf4ebfb2d245
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48942
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-30 01:27:51 +00:00
Michael Niewöhner fca152cb89 soc/intel/cnl: add Kconfig values for GMA backlight registers
Add the right register values for backlight control to CNL's Kconfig.
To make iasl happy about the reversed register order, split the field.

Change-Id: I05a06cc42397c202df9c9a1ebc72fb10da3b10ec
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-30 01:05:21 +00:00
Michael Niewöhner 6f3c5df55b mb/ocp/deltalake: replace "POST complete" mb code with driver functionality
Replace the mainboard-specific code for "POST complete" signalling with
devicetree entries for using the newly introduced IPMI driver
functionality.

Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.

Tested successfully.

Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Change-Id: I3441c2a971cfb564b34b3a419beceb949fe295b1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30 00:31:56 +00:00
Michael Niewöhner 6c3ba50a44 mb/supermicro/x11ssh-tf: configure "POST complete" gpio for IPMI driver
Configure the "POST complete" gpio in the devicetree for the BMC/IPMI
driver and set the pad's initial value to 0 since the signal is active-
high and shall be set by the IPMI/BMC driver.

Also add the pad to early gpio config, since it is expected to have an
external pull-up like X11SSM-F, which is wrong and would confuse the BMC.

Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.

Tested successfully.

Change-Id: If344b2271bfc8d50b8b64847109818f96f2abbcb
Tested-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30 00:31:47 +00:00
Michael Niewöhner 8281a53766 mb/supermicro/x11ssm-f: configure "POST complete" gpio for IPMI driver
Configure the "POST complete" gpio in the devicetree for the BMC/IPMI
driver.

Also add the pad to early gpio config, since it has an external pull-up,
which is wrong and would confuse the BMC. Set the pad's initial value to
zero since the "POST complete" signal is active-high and shall be set by
the IPMI/BMC driver.

Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.

Tested successfully.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I6409b2aca90585e44ee5d32df0ae73b259443f32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30 00:31:34 +00:00
Michael Niewöhner 961ceffd0d mb/supermicro/x11ssm-f: configure the BMC jumper JPB1
Set `bmc_jumper_gpio` to the JPB1 gpio to enable/disable BMC/IPMI
according to its value.

Test: Boot with jumper set to each enabled and disabled and check debug
log if IPMI gets enabled/disabled accordingly.

Tested successfully.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I8581556d915cbad2c743a79db273479ba55798fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30 00:30:57 +00:00
Michael Niewöhner 548a3dc7a6 drivers/ipmi: implement "POST complete" notification functionality
Some server boards like OCP Tiogapass and X11-LGA1151 boards use a gpio
for signalling "POST complete" to BMC/IPMI. Add a new driver devicetree
option to set the gpio and configure a callback that pulls the gpio low
right before jumping to the payload.

Test: Check that sensor readings appear in BMC web interface when the
payload gets executed.

Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with
CB:48711 and OCP DeltaLake with CB:48672.

Change-Id: I34764858be9c7f7f1110ce885fa056591164f148
Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30 00:30:41 +00:00
Michael Niewöhner 31830d3c2c drivers/ipmi: add code to set BMC/IPMI enablement from jumper
Some boards, like the Supermicro X11SSM-F, have a jumper for enabling or
disabling the BMC and IPMI. Add a new devicetree driver option to set
the GPIO used for the jumper and enable or disable IPMI according to its
value.

This gets used in a follow-up change by Supermicro X11SSM-F.

Test: Boot with jumper set to each enabled and disabled and check debug
log if IPMI gets enabled/disabled accordingly.

Successfully tested on Supermicro X11SSM-F with CB:48095.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Icde3232843a7138797a4b106560f170972edeb9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30 00:30:23 +00:00
Michael Niewöhner 8913b783b9 soc/intel: hook up new gpio device in the soc chips
This change adds the required gpio operations struct to soc/common gpio
code and hooks them up in all socs currently using the gpio block code,
except DNV-NS, which is handled in a separate change.

Also, add the gpio device to existing chipset devicetrees.

Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with
CB:48711 and OCP DeltaLake with CB:48672.

Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6
Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48583
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-30 00:30:04 +00:00
Felix Singer 979a071b0e Revert "mb/google/brya: Initiate peripheral buses"
This reverts commit 5bb5c43b93.

Reason for revert: Build bot fails.

Change-Id: I8f022514351b37be135d10ef8486e4aa5fd6361b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48980
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-29 20:54:18 +00:00
Michael Niewöhner 3054a19279 soc/intel/bdw,nb/intel/hsw: correct mask for panel power cycle delay
Correct the mask for the power cycle delay from 0xff to 0x1f, to
represent the actual maximum value according to Intel graphics PRM for
Haswell, Volume 2c and Intel graphics PRM for Broadwell, Volume 2c.

Change-Id: Ib187f1ca6474325475e5ae4cc1b2ffbce12f10bf
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48957
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-29 20:19:52 +00:00
Eric Lai 4ea47c32b0 soc/intel/alderlake: Update chipset.cb for TCSS and USB
Follow TGL chipset.cb to add alias for TCSS and USB ports.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I803dad0af09b26a55ffb767826ba79cf61de04ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48793
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-29 17:25:27 +00:00
Felix Singer bd0fa62b6b soc/intel/skylake: Add 4 missing root ports to chipset dt
The Kaby Lake PCH can have up to 24 PCIe root ports. Thus, add 4 missing
root ports to the chipset devicetree.

Change-Id: I443fb736873d47f1b6fe7718a10e1bb4ae5df2a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48947
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-29 16:35:57 +00:00
Ricardo Ribalda dcbb87a3ec mb/google/poppy/natutilus: Add missing PR dependency
On commit 64c03e3c ("mb/google/poppy: Fix race condition in acpi"),
we introduced a new Power Resource common to all the camera modules,
in order to resolve a race condition when both modules were in use
(e.g. during startup).

The nautilus variant also used the Power Supply I2C2.PMIC.OVTH, which
requires the new common PR, but the new dependency was not added.

Depend on the new Camera Common Power Resource.

Fixes: 64c03e3c ("mb/google/poppy: Fix race condition in acpi")
BRANCH=poppy
BUG=b:174941580
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Change-Id: Ifa6c70b7c02aec0112189eca573e76e53175d70d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: shkim <sh_.kim@samsung.com>
2020-12-29 16:16:03 +00:00
Eric Lai 5bb5c43b93 mb/google/brya: Initiate peripheral buses
Initiate peripheral buses based on latest schematic.

BUG=b:174266035
TEST=Build Test

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3a828bfb3ba4ee9a9b41cd4e83701672e5ef85bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-29 14:42:12 +00:00
Arthur Heymans 9059a89878 sec/intel/txt/Kconfig: Make TXT HEAP and SINIT size configurable
More recent platforms (Cooperlake) need bigger sizes.

Change-Id: Ia3e81d051a03b54233eef6ccdc4740c1a709be40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-29 14:41:15 +00:00
rnhmjoj 41b5b045dd util/xcompile: fix XGCCPATH handling
This patch fixes the build with an external (coreboot) toolchain. When
the toolchain is not under util/crossgcc/xgcc, setting XGCCPATH to
/path/to/toolchain results in the error:

  toolchain.inc:169: The coreboot toolchain version of iasl '<date>' was
  not found

The reason is that the xcompile script incorrectly assumes XGCCPATH to
have a trailing slash.

Change-Id: Ifcc4bd2b081fa3603420dc0a8cab3b47967ebc65
Signed-off-by: Michele Guerini Rocco <rnhmjoj@inventati.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-29 14:36:16 +00:00
Huayang Duan 8a02d98c5a soc/mediatek/mt8192: Implement dramc base settings for each frequency
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I50d5aebaf249ab7292fad7a0046099239c8b403c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-29 14:35:45 +00:00
Felix Singer 91f74ae16b mb/clevo/n13xwu: Disable GMM PCI device
We don't know exactly for what the GMM PCI device is used for or how it
is used. Thus, remove it to fallback to default-disable.

Change-Id: I4b8b33b16527cbcc21168b995cbfdb54a2fa3cac
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-29 09:10:56 +00:00
Felix Singer c321a81b77 mb/clevo/n130xu: Remove disabled devices from devicetree
All known on-chip PCI devices are documented in chipset devicetree now
and default to disabled. There is no need to keep disabled PCI devices
in the mainboard's devicetree. Thus, remove them.

Change-Id: I7c537bba75d66badf854f9e7b6799303a7af018e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-29 09:10:29 +00:00
Michael Niewöhner 6e016f031f device/pnp: add register PNP_IO4
Add the register PNP_IO4, which will be used by IT5570E in CB:48894.

Change-Id: Ic820295247323f546d4c48ed17cfa4eab3dc5e92
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48924
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-28 21:01:08 +00:00
Michael Niewöhner dbb667ac08 device + util/sconfig: introduce new device `gpio`
Introduce a new device `gpio` that is going to be used for generic
abstraction of gpio operations in the devicetree.

The general idea behind this is that every chip can have gpios that
shall be accessible in a very generic way by any driver through the
devicetree.

The chip that implements the chip-specific gpio operations has to assign
them to the generic device operations struct, which then gets assigned
to the gpio device during device probing. See CB:48583 for how this gets
done for the SoCs using intelblocks/gpio.

The gpio device then can be added to the devicetree with an alias name
like in the following example:

  chip soc/whateverlake
    device gpio 0 alias soc_gpio on end
    ...
  end

Any driver that requires access to this gpio device needs to have a
device pointer (or multiple) and an option for specifying the gpio to be
used in its chip config like this:

  struct drivers_ipmi_config {
    ...
    DEVTREE_CONST struct device *gpio_dev;
    u16 post_complete_gpio;
    ...
  };

The device `soc_gpio` can then be linked to the chip driver's `gpio_dev`
above by using the syntax `use ... as ...`, which was introduced in
commit 8e1ea52:

  chip drivers/ipmi
    use soc_gpio as gpio_dev
    register "bmc_jumper_gpio" = "GPP_D22"
    ...
  end

The IPMI driver can then use the generic gpio operations without any
knowlege of the chip's specifics:

  unsigned int gpio_val;
  const struct gpio_operations *gpio_ops;
  gpio_ops = dev_get_gpio_ops(conf->gpio_dev);
  gpio_val = gpio_ops->get(conf->bmc_jumper_gpio);

For a full example have a look at CB:48096 and CB:48095.

This change adds the new device type to sconfig and adds generic gpio
operations to the `device_operations` struct. Also, a helper for getting
the gpio operations from a device after checking them for NULL pointers
gets added.

Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with
CB:48711 and OCP DeltaLake with CB:48672.

Change-Id: Ic4572ad8b37bd1afd2fb213b2c67fb8aec536786
Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-28 17:47:04 +00:00
Michael Niewöhner 5c2efa1990 drivers/intel/gma: drop unused register to resolve name conflict
The register `ESR` conflicts with the `Exception syndrome register` in
UDK2017. To resolve the conflict, drop the unused `ESR` register from
gma registers. It can be readded and prefixed or renamed if it's
required at a later point.

Change-Id: Icfdd834aea59ae69639a180221f5e97170fbac15
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-28 17:29:37 +00:00
Felix Singer 8c604922eb drivers/libgfxinit: Add Comet Lake to supported platforms
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I002ade555c0544e4ef738c1ad45ee3d8aa38e03e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-28 17:29:19 +00:00
Nico Huber 3394040e79 3rdparty/libgfxinit: Update for Cannon Point support
We missed that Cannon Point, the PCH usually paired with Coffee, Whiskey
and Comet Lake, differs a bit from its predecessors. Hence, libgfxinit
now has a new Kconfig setting for the PCH.

Change-Id: I1c02c0d9abb7340aabe94185ee5e17ef4c2b0d36
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-28 17:27:21 +00:00
Felix Singer 0ba8213d4c mb/kontron/bsl6: Remove disabled devices from devicetrees
All known on-chip PCI devices are documented in chipset devicetree now
and default to disabled. There is no need to keep disabled PCI devices
in the mainboard's devicetree. Thus, remove them.

Change-Id: I0f78dadd9e55a8f002394dc07ab514ca13f4e963
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-28 16:58:08 +00:00
Felix Singer 4925d1c282 soc/intel/apl: Fix indents
Change-Id: Ide10889ad01ec6d31ee83158182876625a68a5da
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48888
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-28 16:58:03 +00:00
Matt DeVillier 61a3c8a005 payloads/tianocore: Add Kconfig to set boot timeout
Add a Kconfig option to set the tianocore boot timeout,
which is passed to the payload via a command line parameter.

Allows boards without an internal display (eg) to set a longer
boot timeout, in order to ensure the boot splash/menu prompt
are visible upon boot.

The associated changes on the tianocore side have already been
merged into MrChromebox's CorebootPayloadPkg and UefiPayloadPkg
branches (coreboot_fb and uefipayloadpkg respectively).

Change-Id: Ifeaadff05f6667d642c05b81f53c1d2dbc450af6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-28 16:47:59 +00:00
Arthur Heymans 1918553190 soc/intel/xeon_sp: Lock PAM and SMRAM registers
The CedarIsland FSP Integration recommends locking down some things.

Change-Id: I72e04b55d69a8da79485e084b39c3bd38504897f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47168
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-28 13:39:51 +00:00
Arthur Heymans 7a36ca5a3a soc/intel/xeon_sp: Lock down IIO DFX Global registers
This is required for CbNT.

Change-Id: I565a95cd2e76cb1c648884be6d1954288f6e4804
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-28 13:39:39 +00:00
Arthur Heymans 42a6f7e417 soc/intel/xeon_sp: Lock down DMI3 PCI registers
This is required for CBnT.

Change-Id: If5637eb8dd7de406b24b92100b68c5fa11c16854
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-28 13:39:23 +00:00
Yuchen Huang b0ab41e027 soc/mediatek/mt8192: add rtc MT6359P driver
Add rtc MT6359P driver for rtc init and rtc eosc calibration. Refactor
mt8173 and mt8183 code by extracting common API. Move rtc_read and
rtc_write to each SoC folder, because mt8173 and mt8183 access rtc via
pmic wrapper, while mt8192 accesses it via pmif.

Reference datasheet:
  Document No: RH-D-2018-0101.

Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Change-Id: I57d6738fdec148c7458b2024a0a8225415ca2f3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-28 13:39:01 +00:00
Nina Wu 87c30a064c soc/mediatek/mt8192: devapc: add basic devapc drivers
Add basic devapc (device access permission control) drivers.

DAPC driver is used to set up bus fabric security and data protection
among hardwares. DAPC driver groups the master hardwares into different
domains and gives secure and non-secure property. The slave hardware can
configure different access permissions for different domains via DAPC
driver.

Change-Id: I2ad47c86b88047c76854a6f8a67b251b6a9d4013
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-28 13:38:38 +00:00
Huayang Duan 3960351141 soc/mediatek/mt8192: Do dramc pre-settings before calibration
Before calibration, dramc resets the delay of each PHY IO, calculates
TX path and sets CKE to be rank independent.

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-28 13:38:20 +00:00
Jack Rosenthal 32ed65611d kconfig: remove non-existent source
src/northbridge/amd/pi/00660F01/Kconfig does not exist.  Remove the
source statement.

Also, no kconfig files under src/soc/intel/common/basecode/.  Clean
that up.

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I10917b76ff6c2a9d5a97d5c7dfa9e8925cd8c8a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-12-28 13:37:56 +00:00
Benjamin Doron d0701c96f2 soc/intel/skylake: Enable CHAP device depending on devicetree
Now that CHAP device is declared in chipset devicetree, hook it up to
devicetree configuration.

Change-Id: Icc51f7b9cda32d5058dce958e386921b6d3d8ffb
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48323
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-28 13:37:47 +00:00
Kyösti Mälkki b8cb142ccd sb/amd/pi/hudson: Enable use of common GPIO API
The code in soc/amd/common has an implementation of
GPIO register space that is compatible with the hardware
sb/amd/pi/hudson supports.

Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-28 13:37:15 +00:00
Felix Singer 219caf8358 mb/siemens/chili/base: Add SMBIOS slot descriptions
Add SMBIOS slot descriptions for M.2 ports and remove duplicate
comments.

Change-Id: Ieff03ad3167aec054cdc6b67ddc20fc64394e347
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-27 15:57:09 +00:00
Nico Huber c00ffef47c vpd: Add vpd_get_int() function
Change-Id: I1c1b5710a5236fe4a3bdda1fc978393e636e9817
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45773
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-27 15:33:24 +00:00
Idwer Vollering bdb37982d6 src/superio: trim and move Makefile.inc, instead use wildcard matches
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: If77d59485451c77dcea752bc4fe0dfadba8fec45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48900
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-27 14:46:07 +00:00
Angel Pons 7e3126dbc5 cpu/intel/model_206ax: Add more CPU steppings
The Sandy Bridge steppings appear in the BWG, and Ivy Bridge steppings
appear in reference code. Add them for the sake of completeness.

Change-Id: I7d17cdd04a771ca319c908fc757f868e95ea7944
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-25 22:01:00 +00:00
Angel Pons 47a80a045d nb/intel/sandybridge: Move steppings to CPU header
The steppings correspond to the CPUID bits 3:0, so move them to the CPU
scope, and include the CPU header from files using the stepping macros.

Change-Id: Idf8fba4911f98953bb909777aea57295774d8400
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48409
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-25 21:41:55 +00:00
Angel Pons 5db1b15147 nb/intel/sandybridge: Rewrite constant values
Rewrite some constants to make their meaning somewhat clearer.

Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.

Change-Id: I321f5e61d7c695ae77e61b84728e34930f69d400
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-25 21:41:28 +00:00
Angel Pons 3170e9c0ef nb/intel/sandybridge: Allow to ignore XMP voltage
Native raminit only supports 1.5V operation, but there are DIMMs which
request 1.65V operation in XMP profiles. Add an option to force XMP to
be used when the requested voltage isn't supported, which will run the
DIMMs at 1.5V with XMP timings. Consider this to be overclocking.

Change-Id: I64bfac8f72dadf662ceadfc7998daf26edf5a710
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-25 21:41:17 +00:00