Commit Graph

23 Commits

Author SHA1 Message Date
Karol Zmyslowski b2f5a22c4a util/inteltool: Add support for Jasper Lake
Tested on: Intel N5105 (Jasperlake Family, Intel Celeron processor)
Based on Intel Pentium Silver and Intel Celeron Processor Datasheet,
        vol. 2 of 2 revision 001 (DOC# 634545)

Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d
Signed-off-by: Karol Zmyslowski <karol.zmyslowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-04-21 15:22:21 +00:00
Christian Walter 1364ac3478 util/inteltool: add support for EBG (Emmitsburg) PCH
EBG (Emmitsburg) PCH is used in Intel SPR-SP chipset.

Its datasheet is Intel doc# 606161.

Add Intel Emmitsburg PCH GPIO pin definitions.

Also common code change is made to support Intel Emmitsburg PCH:
a. Instead of 2 PAD registers per GPIO, it has 4 PAD registers.
b. The register address space may not be contiguous from one GPIO
group to the next GPIO group.

Change-Id: Ia0d9179544020b6abb0be1ecd275a9a46356db8a
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-24 12:47:30 +00:00
Kacper Stojek 76d2b6699d util/inteltool: Add support for Elkhart lake
Document: 614109, 601458
Tested on: Protectli vault_ehl (VP2420)

Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com>
Change-Id: I54948741082ca1072642046f64539a4c15ddb578
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-11-10 16:24:49 +00:00
Kacper Stojek fb9110b9e4 util/inteltool: Add support for Alderlake P in inteltool
TEST=Dump registers on Clevo NS70PU with Intel® Core™ i7-1260P

Document number: 626817, 630094, 655258

Change-Id: I2ba4ef7eee33d4dd762a05dd755de5e4d2e566dd
Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66825
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07 21:18:22 +00:00
Michał Żygowski de91780c30 inteltool/gpio_names/tigerlake.h: Fix HVMOS pad count
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I344fd2db9d53ad5e82240aaa2b766ac0d8a2045d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64464
Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-06-03 20:06:01 +00:00
Michał Kopeć 2d8edebc97 util/inteltool: Add support for Alder Lake chips detection and GPIOs
Add PCI IDs for Alder Lake H devices and their GPIO tables.

PCI IDs as per Intel PCH-H EDS Vol1 (doc #619362).

TEST=dump GPIOs on i5-12600K with Z690 chipset

Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-05-28 14:36:50 +00:00
Sean Rhodes 645dde7794 util/inteltool: Add support for Gemini Lake
Tested on:
* StarLite Mk III (N5000)
* StarLite Mk IV (N5030)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0ef7619c04db66ea0c6e179bdf0a58ed1ab61a48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16 07:04:22 +00:00
Michał Żygowski 8ac40f3ea7 util/inteltool: Add support for Tiger Lake chips detection and GPIOs
Add PCI IDs for Tiger Lake LP and Tiger Lake H devices and their GPIO
tables.

TEST: dump GPIOs on i5-1135G7, Tiger Lake H untested

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6071a999be9e8a372997db0369218f297e579d08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-15 19:44:08 +00:00
Michael Niewöhner 2a5fe1d64b util/inteltool: add missing special function pads for CNL-LP
Add the missing special function gpio pad groups for CNL-LP.

The groups and names are documented in the PCH EDS, in Linux
(linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places.

Also, see soc/intel/tigerlake for reference.

Change-Id: I0509552da6ffad395c2b89df1676e1903c783695
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-11 13:04:00 +00:00
Michael Niewöhner 85c8a51577 util/inteltool: add missing special function pads for CNL-H
Add the missing special function gpio pad groups for CNL-H.

The groups and names are documented in the PCH EDS, in Linux
(linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places.

Also, see soc/intel/tigerlake for reference.

Change-Id: Ib83aeef9f4b6aa174e61ccbd87fb7b6450ed773b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-11 12:30:19 +00:00
Michael Niewöhner 33a047da68 util/inteltool: add missing native functions of special pads for CNL-H
Add the missing native functions for special gpio pads for CNL-H,
which are documented in the PCH EDS and other places.

Also, see soc/intel/tigerlake for reference.

Change-Id: I71339d66362d29806c91375c214e9fb84c989201
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-11 12:30:10 +00:00
Michael Niewöhner 1617521f57 util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-H
The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux
(linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places.

Also, see soc/intel/tigerlake for reference.

Change-Id: Ifd6cabb646000c8dff695c5c4f7196b2779f1430
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-11 12:30:02 +00:00
Michael Niewöhner f0c5d87a0e util/inteltool: add missing native functions of special pads for CNL-LP
Add the missing native functions for special gpio pads for CNL-LP,
which are documented in the PCH EDS and other places.

Also, see soc/intel/tigerlake for reference.

Change-Id: Iedb726aa3afdbbbedafb67f6b7668bf591c2b9b4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-11 12:28:04 +00:00
Michael Niewöhner b0630464d9 util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-LP
The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux
(linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places.

Also, see soc/intel/tigerlake for reference.

Change-Id: I86c7159d9f48560c41efdfe49f162aef00499d13
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-11 12:27:57 +00:00
Benjamin Doron 552ce003a5 util/inteltool/gpio_names: Make group and community titles consistent
Consistency is good for scripting and automation.
The lowercase "group" in Sunrise Point-LP, for example, was
breaking pattern matching used in intelp2m.

Change-Id: Iffa8a8ac9c17c5cbd8d7b838d9c703cae6a858b5
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43068
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:48:48 +00:00
Maxim Polyakov ec0551c6b0 util/inteltool: add missing L0 and L1 pads for Lewisburg
The description for L0 and L1 was missed in the datasheet, however,
configuration registers for these pads are present. In addition, the
chipset contains the "GPP_L0/CSME_INTR_IN" and "GPP_L1/CSME_INTR_OUT"
pads in a circuit diagram. Use all available information to add a
description for the missed pads.

Change-Id: I7a0488c26b3df9de1adc037d94ae290837d65dd8
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40044
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 16:39:14 +00:00
Matt DeVillier 3c78445ad9 inteltool: add support for CannonPoint-LP
Add support for CannonPoint-LP U Premium
(CoffeeLake-U and WhiskeyLake-U)

GPIO info taken from:
- Intel doc #337867-002
- coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs.h

Test: Read GPIOs from out-of-tree WhiskeyLake-U board

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I70f23eec71abb8d7c2a7a109c9e760bb31dee2ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39393
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 15:22:31 +00:00
Johanna Schander 7da602ff47 util/inteltool: Move Denverton definitions into their own header
So far all group and community definitions live in one big c file.
This 2500 line file slowly grows to a size, where readability is lost.
Also the definitions are not reusable in a potential libinteltool.
This commit moved the Denverton definitions into its own header.

Change-Id: I6ce672c24059b9f3a4a984766184066f14df3013
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38630
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 15:20:41 +00:00
Johanna Schander aff7d1f864 util/inteltool: Move Lewisburg definitions into their own header
So far all group and community definitions live in one big c file.
This 2500 line file slowly grows to a size, where readability is lost.
Also the definitions are not reusable in a potential libinteltool.
This commit moves the Lewisburg definitions into its own header.

Change-Id: I7900f1d8b3ca022112874ac2fa7326d538166008
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38629
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 15:20:32 +00:00
Johanna Schander e98af86a2e util/inteltool: Move Sunrise Point (LP) definitions into their own header
So far all group and community definitions live in one big c file.
This 2500 line file slowly grows to a size, where readability is lost.
Also the definitions are not reusable in a potential libinteltool.
This commit moves the Sunrise Point and Sunrise Point LP definitions
into its own header.

Change-Id: I06efbee700f1525770365428fb85ef700ac53b80
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38628
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 15:20:24 +00:00
Johanna Schander f80c5d9133 util/inteltool: Move Apollo Lake definitions into their own header
So far all group and community definitions live in one big c file.
This 2500 line file slowly grows to a size, where readability is lost.
Also the definitions are not reusable in a potential libinteltool.
This commit moves the Apollo Lake definitions into its own header.

Change-Id: I44b21092f5495f758c1f2151a913c074dfc658f5
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38627
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 15:20:11 +00:00
Johanna Schander d5a65304c0 util/inteltool: Move Cannon Lake definitions into their own header
So far all group and community definitions live in one big c file.
This 2500 line file slowly grows to a size, where readability is lost.
Also the definitions are not reusable in a potential libinteltool.
This commit moves the Cannon Lake definitions into its own header.

Change-Id: I5991c3cebba0e05504940ae66fa7bb63bf280ab1
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38626
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 15:19:56 +00:00
Johanna Schander dca20cd77f util/inteltool: Move Ice Lake definitions into their own header
So far all group and community definitions live in one big c file.
This 2500 line file slowly grows to a size, where readability is lost.
Also the definitions are not reusable in a potential libinteltool.
This commit moves the Ice Lake definitions into its own header.

Change-Id: I5735f12480091a9b6c5e5c103a1ca7b7b1f3f997
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38625
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 15:19:42 +00:00