Commit Graph

38243 Commits

Author SHA1 Message Date
Martin Roth d5c3d9ca82 mb/google/zork: Power off fingerprint sensor on shutdown
When the system shuts down, turn the fingerprint sensor off. This sets
the GPIOs correctly for the next boot.  The fingerprint sensor was
previously left on, and was just powering down when the rails went low.

On suspend, the fingerprint sensor stays awake and puts itself in a low
powerstate mode based on the SLP_Sx_L pin states.

BUG=b:171837716
TEST=Fingerprint sensor still works after S3, GPIO state on the boot
following a shutdown is low.
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I3837b58372d8f4a504535e76bd21c667d68f8995
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47311
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-17 16:54:16 +00:00
Elyes HAOUAS 6aaf7db719 src: Add missing 'include <console/console.h>'
"Die()" needs <console/console.h>.

Change-Id: I250988d77b0b0a093a1d116bea44a0cbb84189dd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-17 09:50:24 +00:00
Elyes HAOUAS 27718ac87f src: Add missing 'include <console/console.h>'
"printk()" needs <console/console.h>.

Change-Id: Iac6b7000bcd8b1335fa3a0ba462a63aed2dc85b8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-17 09:01:14 +00:00
James Chao add3a06268 mb/google/reef/variants/: add Naya NT6AN256T32AV-J2
BUG=b:172843935
BRANCH=coral
TEST=emerge-coral coreboot chromeos-bootimage

Signed-off-by: James Chao <james_chao@asus.corp-partner.google.com>
Change-Id: I70195acc33218d3ad4c77acfdbc8f6ed93ab144e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47382
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-17 08:48:54 +00:00
Martin Roth 560c11ec65 mb/google/zork: Assume VBOOT_STARTS_BEFORE_BOOTBLOCK
At this point, the zork platform will only use psp_verstage, so remove
the VBOOT_STARTS_IN_BOOTBLOCK option and set code for VBOOT_STARTS-
BEFORE_BOOTBLOCK to always be used.

TEST=Build & Boot Morphius
BRANCH=Zork
BUG=b:172848137

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I30d90fe82c37966a860b52c07a3550dcecf8d19d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-17 08:38:44 +00:00
Zheng Bao 5014373edd amdfwtool: Move the MP2CFG checking to category of BIOS data
Change-Id: Iaaf9c96dd0ed8c31bb50350d37646ca08a1bbff0
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-17 08:07:12 +00:00
Kyösti Mälkki 123a37ed36 Revert "arch|cpu/x86: Add Kconfig option for x86 reset vector"
This partially reverts commit 67910db907.

The symbol X86_RESET_VECTOR continues to live, for the time being,
under soc/amd/picasso.

Change-Id: Ib6b2cc2b17133b3207758c72a54abe80fc6356b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-17 07:46:34 +00:00
Furquan Shaikh 1eaf64c723 soc/amd/picasso: Drop the inclusion of entry16.ld and reset16.ld
This change drops the inclusion of entry16.ld and reset16.ld and
instead adds the content of those files directly in memlayout_x86.ld
in amd/picasso. This is done to allow the work for top-aligning
bootblock to happen independent of Picasso layout. Once that is
complete, Picasso layout can be re-evaluated to see if it can make use
of the common bootblock linker file includes.

TEST=Verified that coreboot.rom generated using --timeless is the same
with and without this change for trembyle.

Change-Id: Ib1218b24a06d0f69b856fb21458a6183fd21fcbc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-17 07:33:22 +00:00
Johnny Li df3cbddb58 mb/google/volteer/variants/volteer2: Tune Volteer2 I2C2 bus frequency
The current I2C2 bus frequency is 344 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C2 to bring
the bus frequency closer to 400 kHz.

BUG=b:153588771
TEST=Verified that I2C2 frequency is 380 kHz.

Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: I96fa5ed586de41324733ac7537b6bd73f39fc176
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47558
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-17 00:49:37 +00:00
Sheng-Liang Pan 1fe129f321 mb/google/octopus/variants/bobba: Add G2Touch touchscreen support
Add G2Touch touchscreen support for bobba.

BUG=b:171636614, b:169730666
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen
work.

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ia361a56c050d7cbd7325b3c09fc34d8707441cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-17 00:39:30 +00:00
Felix Held c1e8aa2f46 soc/amd/picasso/acpi.h: include missing header files
In the file uintptr_t that is defined in stdint.h and struct device that
is defined in device/device.h are used, so include them directly to
avoid having to rely on them being included in the file that includes
this header file.

Change-Id: I9893619924d45e5690a5cfc65252ace4cb7f1486
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-16 20:40:33 +00:00
Nico Huber 7e3e1ea43f device/pci: Add NULL check for PCI driver's .ops
Add a NULL check and only skip setting the default operations
if `.ops` was set by a driver. It's fairly unlikely that some-
body adds a driver and forgets the `.ops` pointer. So this is
mostly to increase readability: Nobody should have to wonder
if we're missing a NULL-check.

The condition is moved out of the loop to reduce indentation
levels. Alternatively, we could jusk skip drivers that don't
have `.ops` set (i.e. continue the loop).

Change-Id: I5dcc05ebb092fb9c4be929c81ea2b05a10b1311b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46297
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 12:15:38 +00:00
Felix Singer d3d0fd7d5e device: Enable bus mastering on system-class devices conditionally
Devices of class type "system" are arbitrary devices and it's not clear
which of them need bus mastering. Therefore, enable bus mastering
conditionally based on Kconfig option PCI_ALLOW_BUS_MASTER_ANY_DEVICE.

Change-Id: Ia04e83606a0a081c0758ec59e52627aa1dbd2622
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-16 12:14:48 +00:00
Felix Singer 205b53ee77 device: Allow configuring bus mastering for PCI bridges conditionally
Change-Id: Ic7cacce28f473dda76ca203016dbb8e00149a990
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-16 12:14:01 +00:00
Angel Pons 81f5bf3017 lib/gnat/i-c.ads: Add `uintptr_t` type
While Ada makes pointers harder to use, it is still useful to provide a
pointer type for use in C interfaces.

Change-Id: I3a30ef0147a459ba82c79a1f85a3d3fb97b0f3a1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47393
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 12:13:31 +00:00
Arthur Heymans 14ca740719 Makefile.inc: Move adding SeaBIOS cbfs config files
Using the INTERMEDIATE target this can be done in the proper dir.

Change-Id: Ie105231655ef4b49234f0944f638545fe79f07cb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-16 12:13:18 +00:00
Martin Roth 114cf5f136 src/drivers/intel: Correct Kconfig option in Makefile
This Kconfig option was just added incorrectly, so would never add
the verstage.c file.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I4c39dca9d429ed786ea42c0d421d6ee815e8c419
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-16 12:10:18 +00:00
Martin Roth 3e7fced218 drivers/i2c/tpm: Remove ifdef of non-existant Kconfig option
The CONFIG_TPM_I2C_BURST_LIMITATION was never added, so this has never
been turned on.  The Kconfig linter generates three warnings about this
block:
  Warning: Unknown config option CONFIG_TPM_I2C_BURST_LIMITATION

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I53fa8f5b4eac6a1e7efec23f70395058bad26299
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47367
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 12:10:10 +00:00
Martin Roth 0639bff5ba src: Update some incorrect config options in comments
This is a trivial patch to fix some comments that were generating
notes in the kconfig lint test.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I26a95f17e82910f50c62215be5c29780fe98e29a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47366
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 12:09:58 +00:00
Julien Viard de Galbert a0e5046a08 soc/intel/denverton_ns: Generate ACPI DMAR Table
- Write ACPI DMAR Table if VT-d is enabled.
- The entries are defined to follow FSP settings.

Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25446
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 12:09:32 +00:00
Arthur Heymans 81b88a1963 cpu/x86/smm/smm_module_loaderv2: Properly print stack_end
Change-Id: I2b8c54fd3851d1c2a9f4c3c36828922067bec79f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47071
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 12:07:56 +00:00
Arthur Heymans b17f11e19d cpu/x86/smm/smm_module_loaderv2.c: Use more variables
Reusing the 'size' variable for a different purpose later on in the
function makes the code harder to read.

Change-Id: Iceb10aa40ad473b41b7da0310554725585e3c2c2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-16 12:07:50 +00:00
Arthur Heymans fd8619e665 cpu/x86/smm: Check that the stub size is < save state size
If the stub size would be larger than the save state size, the stagger
points would overlap with the stub.

The check is placed in the stub placement code. The stub placement
code is called twice. Once for the initial SMM relocatation and for
the permanent handler in TSEG. So the check is done twice, which is
not really needed.

Change-Id: I253e1a7112cd8f7496cb1a826311f4dd5ccfc73a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47069
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 12:07:41 +00:00
Angel Pons bf13ef0738 nb/intel/sandybridge: Clarify some parts of raminit
Put names and expand comments for some parts of the code.

Change-Id: If1f83bf113ef08469768a9e4dd13819f76633f18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-11-16 12:07:20 +00:00
Angel Pons 3b9d3e92c0 nb/intel/sandybridge: Fix typo in comment
Change-Id: I8271911695f41ef7cac1bb228309af0568e5bb0c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-11-16 12:07:12 +00:00
Angel Pons b50ca574ef nb/intel/sandybridge: Retype constant
There's no need to use size_t to store a boolean.

Change-Id: I0069fa8d75583dc34b402004d753220943406a04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-11-16 12:07:03 +00:00
Angel Pons 71902014e3 nb/intel/sandybridge: Drop write_controller_mr() function
The only reason to write the MR values to the training result registers
is for EV (Electrical Validation) usage. The hardware doesn't need it.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: I808174494729453f4ebcaa13258d735faae68d72
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-16 12:06:53 +00:00
Angel Pons 2f3cc0035d nb/intel/sandybridge: Reduce the scope of get_CWL()
It is only used once, and can thus be moved to the same file.

Change-Id: I4ee0621449da7fa1970a475d5a2f6e66546357ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-11-16 12:06:44 +00:00
Angel Pons 765d465a23 nb/intel/sandybridge: Clarify IOSAV_DATA_CTL_ch usage
It is usually written to right after programming a pattern, because its
lower byte contains the number of cachelines of the programmed pattern.
The other cases merely reset the WDB data write and compare pointers.

Change-Id: I97196d404bf70542db28499e0d2e24b7cdab07b6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-11-16 12:06:34 +00:00
Nico Huber 0748a87455 libpayload/i8042: Increase response timeout to 1.5s
The current timeout of 500ms is too low. For instance self-test
of the KBC integrated into IT8516E took almost 1s in tests. We
already check for presence of the KBC before the self-test. So
the timeout should only trigger on a hardware defect and we can
leave some margin.

Change-Id: I95f01a4e605a9c7deb894a71e102c3a881759bb1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-16 11:08:49 +00:00
Benjamin Doron 1bb640dfc0 util/intelp2m: Clean up SCI, SMI macro generation and update comments
Simplify macro generation and fix up "DEEP,EDGE_SINGLE" bug introduced
by commit 7bb756f (util/intelp2m: Update macros). Also update legacy
macro comments.

Change-Id: Ie49874d4abbdc7d1a18d63a62ccbce970ce78233
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47314
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 11:08:27 +00:00
Ricardo Ribalda f41645c34d mb/google/hatch/dratini: Describe the privacy_gpio
Add information regarding the privacy pin on the overridetree and gpio.

BUG=b:172807539

Change-Id: Ic1bfa63e35a16d71a26adc3ec07b1ba36e6dc168
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47362
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 11:07:50 +00:00
Arthur Heymans a1cc557d61 soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's
Add a soc specific callback for getting the IIO IOAPIC enumeration ID.

Tested on ocp/deltalake.

Change-Id: Id504c2159066e6cddd01d30649921447bef17b12
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-16 11:07:16 +00:00
Angel Pons c8e86de3fe soc/intel/broadwell/systemagent.c: Rename to `northbridge.c`
Change-Id: Id1a0e02174456bb25df0721cfd3865645641a01a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-16 11:06:30 +00:00
Frans Hendriks d42154afc0 arch/x86/car.ld: Do cosmetic fixes
Make the code follow the coding style.

Replace 8 spaces by TAB
Move comment between the corresponding #if #endif

Tested on Facebook FBG1701

Change-Id: I55cb071eb58a24f78e231cd36e6575fd13817e86
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-16 11:06:21 +00:00
Angel Pons 6091e6cbf8 mb/supermicro/x11-lga1151-series: Initialize mem_cfg in one line
Change-Id: I50390f66d9570eb0fd703e3ad8a2735125d76b61
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47566
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 11:06:03 +00:00
Tony Huang c1870394a7 dedede: Create lantis variant
Create the lantis variant of the waddledee reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.2.0).

BUG=b:171546871
BRANCH=dedede
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_LANTIS

Change-Id: Ie3d15a687b870afc7d8bbeb6b5cab0792650da31
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-11-16 11:05:35 +00:00
Yidi Lin 7de8df467a soc/mediatek/mt8192: Reserve 44K SRAM for MCUPM working buffer
Reduce PRERAM_CBMEM_CONSOLE buffer from 63K to 19K and reserve
0x00115000 ~ 0x0011ffff for MCUPM.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ic82a194736eecd7bdc8df80b493290090a2ccba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-11-16 11:04:11 +00:00
Eric Lai 93538c9969 mb/google/zork/: Enable REGULATORY_DOMAIN on Vilboz
WRDD table is needed for Intel WiFi module to enable SAR function.

BUG=b:173066178
BRANCH=zork
TEST=dump ACPI and check WRDD exist with Intel WiFi module.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9fd6fd19ed188f7ab91faab9e2599b9b09ca5b22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2020-11-16 11:03:57 +00:00
Nick Chen b7a55fd804 volteer/variants/eldrid: Goodix touch panel power-on sequence tuning
1. Enable panel stop GPIO in ramstage
2. generic.reset_delay_ms change to 30

BUG=b:171365316
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I90ca39312252c668da6298183e598392bc9f9f28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-16 11:03:50 +00:00
Tim Chu e41f595310 arch/x86/smbios: Update memory_array_handle for SMBIOS type 19
Update memory array handle for SMBIOS type 19.

TEST=Execute "dmidecode -t 19" to check if memory array handle is correct.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I49078b870bac3c6162913b91651ec09632800f1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-16 11:03:37 +00:00
Martin Roth 726504a61a mb/google/zork: Init fingerprint GPIOs for boot vs resume
Add a function that initializes GPIOs based on the sleep type that
the system is coming back from.  This allows initialization of the
fingerprint GPIOs which need to be handled differently between wake
from S3 and boot from S5.

On initial boot, the state of the FP sensor could be either
enabled or disabled.  Because of this, on boot, we power off
the sensor for >200ms, to reset its state, then power it back on.

In suspend/resume, the fingerprint sensor should remain powered
the entire time.

If fingerprint is disabled on the trembyle-based board, set the pins
to no-connect.  Dalboz doesn't have fingerprint and the GPIOS are
configured differently due to the FT5 chip having fewer GPIOS than
FP5, so nothing needs to be initialized there.

There were also a couple of trivial comment clean ups regarding the
FPMCU GPIOS.

BUG=b:171837716
TEST=Boot & Check GPIO states.
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I16a2e621145782e0a908bb3e49478586c09a0e0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-16 11:03:25 +00:00
Martin Roth fc2047b1f7 src: Change bare 'unsigned' to 'unsigned int'
This fixes all of the current code in coreboot/src where a bare
unsigned is used incorrectly. A follow-on will fix the comments
so that we can enable the unsigned lint checker for src/coreboot.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I37f34a95bb1894e70cd9e076d4b81ebac665eaeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-16 11:03:16 +00:00
Johnny Lin c6b77d5bf6 vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW45 FSP Memory map HOB mismatch
Tested=On OCP Delta Lake, verify the memory map hob data are correct.

Change-Id: I86bd809e21270395c4115788e5521606e9dcc2fb
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-16 11:03:00 +00:00
Martin Roth 863b3ad45b commonlib: Add timestamp values for forced delays
Add a timestamp entry to allow forced delays to to be seen and accounted
for in the timestamp data.

BUG=None
TEST=Build only

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I26c9fa5c8599a349de2631ac24b9ea8858d8d6c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-16 11:01:37 +00:00
David Wu df9901eacb mb/google/volteer/var/voema: Add memory parts and generate DRAM IDs
This change adds memory parts used by variant voema to
mem_parts_used.txt and generates DRAM IDs allocated to these parts.

Added memory
1. H9HCNNNCRMBLPR-NEE
2. H9HCNNNFBMBLPR-NEE
3. MT53D1G64D4NW-046 WT:A

BUG=b:172751925,b:172781673,b:172782100,b:172781562
TEST=emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ic832155448fb07152b906aa04ca49d384ec47b34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47351
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 11:01:12 +00:00
David Wu ed993f5faf lp4x: Add new memory parts and generate SPDs
This change adds the following memory parts to LP4x global list of
available LP4x parts and to the global JSON file containing LP4x parts
and their characteristics.
1. H9HCNNNCRMBLPR-NEE
2. H9HCNNNFBMBLPR-NEE
3. MT53D1G64D4NW-046 WT:A

BUG=b:172751925,b:172781673,b:172782100,b:172781562
TEST=cd <path_to_coreboot_src>/util/spd_tools/lp4x &&
./gen_spd <path_to_coreboot_src>/src/soc/intel/tigerlake/spd \
global_lp4x_mem_parts.json.txt "TGL"

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I37702770f707fe078920694468552c5db59c478f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47350
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 11:01:02 +00:00
Kangheui Won b2c39b563a drivers/i2c/dw: Check for TX_ABORT in transfer
When the host sends data in i2c bus, device might not send ACK. It means
that data is not processed on the device side, but for now we don't
check for that condition thus wait for the response which will not come.

Designware i2c detect such situation and set TX_ABORT bit. Checking for
the bit will enable other layers to immediately retry rather than
wait-timeout-retry cycle.

BUG=b:168838505
BRANCH=zork
TEST=test on zork devices, now we see "Tx abort detected" instead of I2C
timeout for tpm initializtion.

Change-Id: Ib0163fbce55ccc99f677dbb096f67a58d2ef2bda
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-16 11:00:57 +00:00
Felix Held 93231b45e4 MAINTAINERS: add maintainers of soc/amd/picassso
Change-Id: Id39bd55a9a05b062892defadeb652980213b1e9c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47577
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 08:14:04 +00:00
Felix Held 14e3432148 soc/amd/common/block: drop double underscores from include guards
Since coreboot is written in C and not C++, having the double
underscores as a prefix is not an issue, but it also doesn't add much
information, so drop them and the trailing ones as well.

Change-Id: I1028fb9097efab8ffae5ffa9fe85a97feebc78a9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47583
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 08:12:56 +00:00