Commit Graph

98 Commits

Author SHA1 Message Date
Patrick Rudolph b461865577 Documentation: Add Rotundu
Add information about flash and programming header.

Change-Id: If34016e20dd580f92695bef5b67dd0c282b0b421
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-21 14:23:34 +00:00
Bluemax b4951c92a1 Documentation: Add MSI MS-7707
Change-Id: Iba38bda9becba9fcffb51afc4756023659f092ef
Signed-off-by: Max Blau <tripleshiftone@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-06 10:37:04 +00:00
Philipp Hug 6b6dc6eddd hifive-unleashed: update documentation to match current state
Signed-off-by: Philipp Hug <philipp@hug.cx>
Change-Id: I3f1b7dd4ef52a64c9a222f2d5cffe2b73806fe4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23 09:34:09 +00:00
Patrick Rudolph d18a0cbfc1 Documentation: Make lenovo codenames human readable
Use rst parser to convert the csv to markdown tables.

Change-Id: I7fd61bd7a4e8818901520311332ae4027e7a7d02
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-11 11:21:10 +00:00
Maxim Polyakov bcd23b05c1 Doc/mb/asrock/h110m: update info about PEG
- Now there is no need to additionally configure the FSP
   before building;
 - PEG works with high link speed 8 GT/s (Gen 3);
 - external GPU supported, but dynamic switching between iGPU and PEG
   is not yet supported.

Change-Id: Ie0f9db47c0b88052b090cba139f0ae821758935d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31949
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-10 13:56:54 +00:00
Maxim Polyakov 2452c8414d Doc/mb/asrock/h110m: Fix the links
Change-Id: I7b925518416a4268037efac9060ef911e4ae74cd
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-06 13:47:29 +00:00
Maxim Polyakov 1217af5e1a mainboard: Add ASRock H110M-DVS
This board is compatible with Intel Skylake and Kaby Lake generation
processors. This patch contains the minimum configuration for booting
and stable operation of the Ubuntu OS (18.04.1, Linux kernel 4.15).
It is based on Intel RVP8 mainboard.

Intel Kaby Lake FSP 3.6.0 is used to initialize CPU and PCH.
Graphics init with libgfxinit.

Works:
  - Integrated graphics (only DVI port, tested with 1920x1080);
  - PEG x16 (FSP must be configured with BCT to enable PEG);
  - all PCIe x1 slots;
  - all USB and SATA ports;
  - SuperIO COM port for console;
  - onboard audio.

TODO:
  - other SuperIO functions;
  - onboard network chip;
  - suspend and resume;
  - documentation.

Tested on Intel Core i5-6600 processor with Seabios (rel-1.12.0-10-
g171fc89) and Tianocore/edk2 (vUDK2018-8-ge6eccfc) as a payload.

Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-19 21:36:49 +00:00
Balazs Vinarz bc07224da5 Documentation: Add Asus F2A85-M
Change-Id: I4d195f4833ba71fdc559815cafb0f5d0d254e897
Signed-off-by: Balazs Vinarz <vinibali1@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-14 11:24:24 +00:00
Philipp Hug 2ef569a405 mb/qemu-riscv: update to match current qemu version
Boots again to payload not found on qemu.

Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/30554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-26 13:40:51 +00:00
Bill XIE 9cb2da45d8 mb/lenovo/x220: Add x1 as a variant
ThinkPad X1 ( https://www.thinkwiki.org/wiki/Category:X1 ) is nearly a
clone of X220, with additional USB3 controller on pci-e (as i7 variant
of x220), and a powered ESATA port wired to ata4 (Linux' annotation).

Documentation added.

Tested:
- CPU i5-2520M
- Slotted DIMM 8GiB
- Camera
- Mini pci-e on wlan slot
- Msata on wwan slot
- On board SDHCI connected to pci-e
- USB3 controller connected to pci-e
- NVRAM options for North and South bridges
- S3
- TPM1 on LPC
- Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from
  SeaBIOS, or Linux payload (Heads)

Not tested:
- Fingerprint reader on USB2
- Onboard USB2 interfaces (wlan slot, wwan slot)

Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-17 17:09:53 +00:00
Tristan Corrick 907bd5d44e Doc/mb/asrock/h81m-hds: Link to the Haswell documentation
Change-Id: I50da6da6c1321f8d9d94b11d19187a8c22709705
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-09 09:53:57 +00:00
Tristan Corrick 9747f886db Doc/mb/supermicro/x10slm-f: Remove PCIe issue that has been fixed
The issue in question was resolved with commit 334be3289d
("nb/intel/haswell: Add support for PEG").

Also add a link to the known issues for Haswell, which has some
information on PCIe.

Change-Id: Icc3061b60893394e3d537d3b86f4ac748cec2eb4
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-09 09:53:41 +00:00
Tristan Corrick b03e994233 Doc/mb/asrock/h81m-hds: Remove PCIe issue that has been fixed
PCIe graphics for display output still doesn't work, but that is now
listed in the Haswell-specific documentation.

Change-Id: I28c50db353b2b965eb847b379d9e1944cb720c77
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-03 20:07:48 +00:00
Tristan Corrick a6fe456cb5 Doc/nb/intel/haswell: Add a list of known issues
Change-Id: If0339831550f6c70e8056f78633e9a402f35a793
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30455
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03 20:07:41 +00:00
Tristan Corrick 44095c1edc mainboard: Add Supermicro X10SLM+-F
This board runs well with coreboot. The documentation part of this
commit lists what works and what doesn't.

Tested with GRUB 2.02 as a payload, loading SeaBIOS 1.12.0 which then
boots FreeBSD 11.2. It has also been tested with GRUB directly booting
Debian GNU/Linux 9.6 (kernel 4.9).

Change-Id: I291573d4651bdffe24eb841033ea6189fcbf8502
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-29 18:26:46 +00:00
Tristan Corrick cbc561f64a Documentation/nb/intel: Add Haswell documentation
At the moment, this just gives some details on the MRC.

Change-Id: I84e8ca2543b2e19b84a24f7d7032a4aedb6e9272
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-24 08:16:06 +00:00
Jonathan Neuschäfer a2faaa9a27 Documentation/mb/intel/kblrvp11: Fix table formatting
Without this patch, Sphinx 1.7.9 prints the following warning, and
doesn't emit the table as HTML:

  /.../Documentation/mainboard/intel/kblrvp11.md:1: WARNING: Malformed table.

  +------------------+---------------------------------------------------+
  | CPU              | Kaby lake H (i7-7820EQ)                          |
  +------------------+---------------------------------------------------+
  | PCH              | Skylake PCH-H (called SPT-H)                      |
  +------------------+---------------------------------------------------+
  | Coprocessor      | Intel ME                                          |
  +------------------+---------------------------------------------------+

Change-Id: I17920398126d57eb8815c45e4a0d4b100f46004a
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-20 14:20:49 +00:00
Michael Bacarella 54e80cec9f Documentation/mainboard/lenovo/t420.md: fix typo
Picture of mainboard wasn't displaying.

Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com>
Change-Id: Ia70f5d5ad2fdf4c0e811ab92a817375a89694122
Reviewed-on: https://review.coreboot.org/c/30170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19 10:28:46 +00:00
Praveen hodagatta pranesh a86c198cd5 Documentation/../../kblrvp11: Add RVP11 documentation
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: I01509c2fa2c127b77ae72b8b0aaac0f826b0bedd
Reviewed-on: https://review.coreboot.org/c/29859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
2018-12-19 05:51:18 +00:00
Jonathan Neuschäfer dca74c16a3 Documentation/soc/intel/icelake: Fix references between documents
Change-Id: Ifbdab15b1183998712f92d1f2f5340d2ad1451dc
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-19 05:17:58 +00:00
Bill XIE 012ef7735d mainboard/lenovo/t430s: Add ThinkPad T431s as a variant
The code is based on autoport and that for T430s

Tested:
- CPU i5-3337U
- Slotted DIMM 2GiB
- Soldered RAM 4GiB from samsung (There may be more models here)
- Camera
- pci-e and usb2 on M.2 slot with A key for wlan
- sata and usb2  (no superspeed components) on M.2 slot with B key for wwan
- On board SDHCI connected to pci-e
- USB3 ports
- libgfxinit-based graphic init
- NVRAM options for North and South bridges
- Sound
- Thinkpad EC
- S3
- TPM1 on LPC
- EHCI debug on SSP2 (USB3 port on the left)
- Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from
  Linux payload (Heads), Seabios may also work.

Not tested:
- Fingerprint reader on USB2 (not present on mine)
- Keyboard backlight (not present on mine)
- "sticky_fn" flag in nvram

Not implemented yet:
- Fn locking in nvram (may not be identical to "sticky_fn")
- C-based native graphic init (since T431s has eDP instead of LVDS)
- Detecting the model of Soldered RAM at runtime, and loading the
  corresponding SPD datum (3 observed) from CBFS (the mechanism may be
  similar to that on x1_carbon_gen1 and s230u, but I do not know how
  to find gpio ports for that, and SPD data stored in vendor firmware.)

Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-07 11:20:53 +00:00
Michael Bacarella 134c30761e Documentation/mainboard/lenovo/t420.md: add pic of chip
Provide pic of the flash IC with pinouts labeled, as well
as additional text about the chip.

Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com>
Change-Id: I9046fa63dcd4d192836417efac68ca7587ac1c91
Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-05 07:02:32 +00:00
Subrata Banik 13415333fe Documentation/../../dragonegg: Add dragonegg coreboot development documentation
Change-Id: Ia15e317557a0893d9f80cc9e87c6b90c85b93dcf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-27 08:57:07 +00:00
Subrata Banik 0c273ae208 Documentation/../../icelake_rvp: Add RVP coreboot development documentation
Change-Id: If063cbd3436d9ee107945f425a31ba0009039a1d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-27 08:56:49 +00:00
Patrick Rudolph 0b8aefc656 Documentation: Add W530 / T530
Change-Id: Ib253308737f8c7a497c6ca13eab88220b1ac27ad
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-19 09:34:38 +00:00
Arthur Heymans 0115606286 mb/intel/dg43gt: Add documentation
Change-Id: I4e9dc67e66f719d440679b11332e2c8a764024f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-17 16:51:43 +00:00
Tristan Corrick 3693294112 mainboard: Add ASRock H81M-HDS
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with
kernel 4.9.

This board works quite well under coreboot. A list of what works and
what doesn't can be found in the documentation part of this commit.

The file `data.vbt` matches the VBT in the latest stable version of the
vendor firmware (version 2.20).

Change-Id: I53483bb9fa335e86e85dfc487fef03fce4b85e2a
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-16 10:05:26 +00:00
Patrick Rudolph c0a1625df1 mb/lenovo/t400: Improve docking code
* Remove dead code
* Add support for types 2504 and 2505
* Print dock info at romstage entry
* Improve dock disconnect for type 2505
* Move defines into dock.h for future ACPI code
* Reduce timeouts according to spec to decrease boot time on error
* Fix no docking detection (reduces boot time by 1 second)
* Configure GPIO LDN before reading GPIOs
* Use Kconfig values instead of fixed defines
* Add documentation

Tested on Lenovo T500 with docking 2504 and 2505.

Change-Id: Ic4510ffadc67da95961cecd51a6d8ed856b3ac99
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-10 11:51:27 +00:00
Jonathan Neuschäfer 84bf089f6a Documentation/mainboard: Add emulation/spike-riscv.md
Move the usage instructions from their ad-hoc place in Kconfig.name to
the Documentation directory, and expand them a bit.

Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-10-29 11:19:34 +00:00
Patrick Rudolph 6f027ff28a Documentation: Improve elgon documentation
* Convert PNG to JPG and reduce image quality.
* Mark flash IC and USB serial connector.
* Mark SPI programming header.
* Add programming header pinout.

Change-Id: Ica5958545ed23573a0d48dfa422ad1a822d06b47
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-08 08:45:17 +00:00
Jonathan Neuschäfer fd29ff3555 Documentation/mb/sifive: Fix dead links
SiFive's website was reorganized, which broke our links to PDF files.
Update these links to the current ones, obtained by browsing
https://sifive.com/documentation/.

Change-Id: I312de84bf12abb0789bdd971c40033f1e4ea0dd1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-10-06 21:32:11 +00:00
Angel Pons 3b6bddafe7 Documentation/mainboard/gigabyte/ga-h61m-s2pv: Expand page
Uniformize the Yes/No in the tables, expand the internal programming
section and explain how to patch a defective flash descriptor.

Change-Id: I972bb8948c29ce0eba46daa92ce6b6052db7b063
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-05 21:14:54 +00:00
Jonathan Neuschäfer 2fd4907a4d Documentation: Spell "blob" in lowercase
It's not an acronym (outside of database software).

Change-Id: I529561e4fc9889be7f9d6bd6d5f9a876e2007671
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04 09:39:32 +00:00
Jonathan Neuschäfer c831fb8b89 Documentation/mb/lenovo/t4xx_series: Change "Steps to access the flash IC" to sub-heading
This heading should not be a top-level heading, because it's not at the
top of the file.

Also remove the trailing colon, because it's unnecessary in a heading.

Change-Id: I0685bb8734ad899c29618d24c0497e4fb8c0d01c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-10-03 13:29:17 +00:00
Patrick Rudolph 15d8405584 Documentation: Add basic flashing tutorial for Lenovo
* Add basic flashing tutorial
** Describe internal and external flashing
** Describe flash supply diode protection
** Gives general advices on flashing
** Describe how to use flashrom --ifd
*  Describe basic flashing on Lenovo T4xx devices
** Describe how to disassemble and access the flash IC on T4xx
** Describe flash layout on Sandy Bridge and Ivy Bridge series.

Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-30 03:20:36 +00:00
Philipp Deppenwiese 8c678cf46a mainboard/opencellular/elgon: Add mainboard support
Tested on Elgon EVT board and boots into GNU/Linux.

TODO:
* Add hard reset function for VBOOT.
* Add EC code
* Add SPI flash write protection

Change-Id: I9b809306cc48facbade5dc63846c4532b397e0b5
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/28024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-30 03:08:22 +00:00
Philipp Hug 2326a284ac riscv: add trampoline in MBR block to support boot mode 1
Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock.

Tested on hardware:
boot mode 15: works as before
boot mode 1: jump to bootblock works, but bootblock needs to be modified to
move the stack to L2LIM. This will be in a separate commit.

Further changes are needed in the bootblock

Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-14 14:33:09 +00:00
Philipp Hug ea81928e94 soc/sifive/fu540: Add driver for OTP memory
Provides minimal functionality to read the SOC s/n from the NeoFuse
one time programmable memory.

Change-Id: I14b010ad9958931e0a98a76f76090fd7c66f19a0
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-10 15:05:11 +00:00
Arthur Heymans eb2fc04c97 mb/foxconn/d41s: Add mainboard
This supports the Foxconn d41s, d42s, d51s, d52s.

The following is tested (SeaBIOS 1.12 + Linux 4.9) and works:
- COM1
- S3 resume (with SeaBIOS needs sercon disabled)
- Native graphic init on VGA output
- SATA
- USB
- Ethernet
- PS2 keyboard

The base for this mainboard port was the Intel D510MO port.

Change-Id: Ie4ec9cbf70adcdddbc2e5d805e4806825c320072
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28227
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-23 15:51:47 +00:00
Tristan Corrick 921a4cfa3f mainboard: Add ASUS P8H61-M LX
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with
kernel 4.9. This code is based on the output of autoport.

The file `data.vbt` matches the VBT in the latest version of the vendor
firmware (version 4601).

This board works well under coreboot. A list of what works and what
doesn't can be found in the documentation part of this commit. To
summarise: the only known issues are that S3 suspend/resume doesn't
work, and that there is no automatic fan control via the super I/O.

Change-Id: I2a0579f486d3a44de2dd927fa1e76b90c3b48f62
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-03 15:18:07 +00:00
Jonathan Neuschäfer e73e81d029 Documentation/mb/sifive: Update TODO list; UART driver has been merged
See 894e3a9ec8 ("drivers/uart: Add a driver for SiFive's UART").

Change-Id: I035c238beba28ecafd296f18c0ccda167126ab94
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/27398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-17 11:53:32 +00:00
Angel Pons 210b351df3 Documentation: Add Gigabyte to list of mainboards
Gigabyte was not in the list of vendors in the mainboard-specific
documentation. This made a newly added mainboard page difficult to
locate. This commit adds Gigabyte and links said mainboard in the
mainboard-specific documentation main page.

Change-Id: I8839e1c1176fbdc3dd9da616f68c58e8e1cf1b16
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-28 06:02:35 +00:00
Patrick Rudolph 8c986ab263 Documentation: Add cavium SoC and mainboard
* Add documentation for CN81XX SoC
* Add documentation for CN81XX EVB SFF mainboard
* Add documentation for BDK
* Add documentation for BOOTROM and BOOTBLOCK behaviour
* Alphabetically sort vendors

Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-19 18:09:04 +00:00
Angel Pons e9147bdf11 Documentation: Add Gigabyte GA-H61M-S2PV
Change-Id: I0064710362a1c7882d5a40b469d6aacad5c60218
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/26964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-12 07:47:13 +00:00
Philipp Deppenwiese 438b463a8f Documentation: Update index.md and move files
* Add more subdirectories and index.mds.
* Move "getting started" and "lessons" into sub-directories.
* Move "NativeRaminit" into northbridge/intel/sandybridge folder.
* Move "MultiProcessorInit" into soc/intel/icelake folder.
* Reference new files

Change-Id: I78c3ec0e8bcc342686277ae141a88d0486680978
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26262
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-30 09:14:48 +00:00
Patrick Rudolph facc08c47a Documentation: Add HP Compaq 8200 and NPCD378
Change-Id: I56db0cc11cfa5a1a537091553393542312d4f212
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26543
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-28 13:46:30 +00:00
Jonathan Neuschäfer c4b614ca15 Documentation: Add mainboard section to index
Change-Id: Ib00bd6cdd13f164ca7eb07c9092e8d8fe17d23b1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/26266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-19 17:00:06 +00:00
Jonathan Neuschäfer 7a11c900b6 Documentation: Add HiFive Unleashed documentation
Change-Id: Ic97955e36feeaa18b5a0dbd502c722c06dcc1b31
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-05-08 03:07:36 +00:00