Commit Graph

2 Commits

Author SHA1 Message Date
Caveh Jalali c762e231da util/spd_tools: Update LP5X support for ADL/RPL/MTL
This updates the SPD utility and generated SPDs for LP5X to use memory
type code 0x15 (LPDDR5X) instead of 0x13 (LPDDR5). This is done based on
Intel Tech Advisory Doc ID #616599 dated May 2022, page 15.

SPDs were regenerated with:
  "util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5"

This only affects the SPDs for 2 memory parts for Intel SoCs and the
only board referencing these is rex.

BUG=b:242765117
TEST=inspected SPD hex dump

Change-Id: Iadb4688f1cb4265dab1dc7c242f0c301d5498b83
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-07 22:19:21 +00:00
Jack Rosenthal e9b2d0478f spd/lp5: Add support for MT62F1G32D2DS-026 WT:B
Datasheet is available in the bug.

BUG=b:238674174
BRANCH=firmware-brya-14505.B
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: Iadd4bf07d38dbd2e1f47df5024282b04dec3c805
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65795
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-14 21:27:33 +00:00