Commit Graph

3 Commits

Author SHA1 Message Date
Bruce Griffith b266c6b544 AMD Steppe Eagle: Add binary PI vendorcode files
Add all of the PI source that will remain part of coreboot to
build with a binary AGESA PI BLOB.  This includes the gcc
makefiles, some Kconfig, and the AGESA standard library
functions.

Change vendorcode Makefile and Kconfig so that they can compile
AMD library files and use headers from outside the coreboot/src
tree.

The AGESA dispatcher is built using its own rules rather than
generic library generation rules in coreboot/Makefile and
coreboot/Makefile.inc.  The AGESA source files are initially
copied from whereever they live into coreboot/build/agesa.
They are compiled from there.  The binary PI directory has a
mandatory structure that places the AGESA BLOB into the same
directory as the support headers.  These will nominally be
placed in the 3rdparty directory in coreboot.org.

The copy commands that were added to the the vendorcode
Makefile.inc ensure that only one thread will operate on each
source file by using a macro to generate the copy targets.
After the change, each copy target will operate on exactly one
source file.

Due to API issues, coreboot has no way to control the IMC to set up
fan control.  Set a Kconfig flag that removes the ability to install
an IMC BLOB into CBFS.

Change-Id: I050b72a19086aaeba6cb65ce165297b10e3cfc45
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/6595
Tested-by: build bot (Jenkins)
Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2014-08-30 19:13:45 +02:00
Marc Jones 54b8e7a0bb Add Intel FSP northbridge support Sandybridge and Ivybridge
Add support for Sandybridge and Ivybridge using the Intel FSP.
The FSP is different enough to warrant its own source files.
This source handle the majority of FSP interaction.

"Intel® Firmware Support Package (Intel® FSP) provides key
programming information for initializing Intel® silicon and can be
easily integrated into a boot loader of the developer’s choice.
It is easy to adopt, scalable to design, reduces time-to-market, and
is economical to build."
http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html

Change-Id: Ib879c6b0fbf2eb1cbf929a87f592df29ac48bcc5
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4015
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-04 18:45:13 +01:00
Stefan Reinauer b89a761a63 Add Google ChromeOS vendorcode directory
... and hook it up in Kconfig. More code to come.

Change-Id: I24542d8ef97e2bce112c3aface681ceeb1a7c061
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/813
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30 01:59:38 +02:00