We have found a non-compliant USB hub (RealTek RTS 5413) that does not
set a port's Connect Status Change bit on its USB 3.0 half if the port
had already been connected while the hub was being reset. To work around
this bug, this patch adds code to initially request the status of every
port after a hub was enumerated, clear the Connect Status Change bit if
set, and then enumerate the port iff it is currently connected,
regardless of whether the change bit was set. A similar behavior can
also be found in the Linux kernel.
BRANCH=oak
BUG=b:35929438
TEST=Booted Elm with this change, my USB 3.0 sticks enumerate now even
if they had been plugged in since boot.
Change-Id: I8a28252eb94f005f04866d06e4fc61ea265cee89
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18729
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Currently we just disabled ohci interrupts when calling ohci_shutdown,
Which would not actually shutdown the ohci controller, for example it
may still written the increased HccaFrameNumber to Hcca buffer.
Perform a soft reset to ohci controller as the linux kernel ohci-hcd
driver does.
BUG=chrome-os-partner:60996
BRANCH=None
TEST=Checked on gru, no more "BUG: Bad page state" error in kernel.
Change-Id: I128ab6ba455ac5383a4d48be0bc12b8bb4533464
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4749fc82fdd1b74ca3f2ed3fdf0ef53a5e161087
Original-Change-Id: I3f192aea627ba2fa69533bc0a4270466ca18f2a7
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/426338
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/18125
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Chrome OS builds always have some inherent differences to "standard"
libpayload configurations: they don't want to use curses or things like
storage drivers, they always use the coreboot framebuffer and USB, etc.
This patch reintroduces CONFIG_LP_CHROMEOS as an option that only
affects Kconfig defaults. This allows Chrome OS builds to select most of
what they need in one go and reduces board-specific .config files to
only the options that are really specific to that board.
Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on
x86 boards, which probably makes sense for all of libpayload (some but
far from all ARM boards use 8250-compatible UARTs, and we should
probably not default a platform option unless it's going to be correct
with very high probability).
BRANCH=None
BUG=None
TEST=Built and booted Jerry and Oak.
Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864914
Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Id: e558f59
Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/347970
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17024
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
All but ga-g41m-es2l/cmos.default had multiple final newlines.
ga-g41m-es2l/cmos.default had no final newline.
Change-Id: Id350b513d5833bb14a2564eb789ab23b6278dcb5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16361
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Antonello Dettori <dev@dettori.io>
Move the configuration of the timer, storage and USB drivers from the
main Kconfig to three separate ones stored in the respective
directories.
This reduces the LOC of Kconfig and makes it more manageable.
Change-Id: I0786dbc1d5d8317c8ccb600f5de9ef4a8243d035
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/15914
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
1. Make the xHCI driver to support xHCI controller v1.1
2. And a new function xhci_ring_doorbell(), it aims to
add a memory barrier before ringing the doorbell, to ensure
all TRB changes are written to memory.
BRANCH=none
BUG=chrome-os-partner:52684
TEST=boot from USB on Kevin rk3399 platform
Change-Id: Ife1070d1265476d0f5b88e2acf3299fc84af5832
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0c21e92
Original-Change-Id: I4e38e04dc3c7d32ee4bb424a473c70956a3c3ea9
Original-Signed-off-by: Liangfeng Wu <wulf@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/346831
Original-Commit-Ready: Brian Norris <briannorris@chromium.org>
Original-Tested-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15111
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
BUG=chrome-os-partner:49249
TEST=Compiles and boots and detect USB storage
BRANCH=none
Change-Id: I9007399e1f785e6f1d2258225e3f7cc602053aed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1db43f53973d2124e41186777caa829aa346ace3
Original-Change-Id: I943d19a3a7d785bd075073b57ba6388662d7df90
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333311
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14659
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Existing Intel xHCI controllers require a delay of 1 ms,
after setting the CMD_RESET bit in command register, before
accessing any HC registers. This allows the HC to complete
the reset operation and be ready for HC register access.
Without this delay, the subsequent HC register access,
may result in a system hang, very rarely.
Verified CherryView / Braswell platforms go through over
1000 warm reboot cycles (which was not possible without
this patch), without any xHCI reset hang in depthcharge.
BRANCH=None
BUG=None
TEST=Verified CherryView / Braswell platforms go through
over 1000 warm reboot cycles, without any xHCI reset hang
in depthcharge.
Change-Id: I8eff5115ca52738bdcf8bc65fbfb2a5f60a0abe1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3e7ea70df36e3bf35a6ee1297640900ee76bfdac
Original-Change-Id: Id681a19d0eedb0e2c29e259c5467bcde577e3460
Original-Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310022
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12325
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
We found that some SanDisk Cruizer Glide CZ60 sticks (confirmed on 16GB
and 64GB versions) have a problem responding to our first GET_MAX_LUNS
request right after they received their SET_CONFIGURATION. They will
continually return a NAK until the host gives up (which is 2
user-noticable seconds for us). Adding a small delay of about 15us seems
to be enough to fix the issue, but let's do 50 to be save.
Confirmed with both MT8173 and Intel LynxPoint XHCI controllers.
BRANCH=None
BUG=chrome-os-partner:45473
TEST=No notable delay before detecting stick on Oak and Falco.
Change-Id: Ib03944d6484de0ccecbb9922d22666f54c9d53dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 589f19a901275fb8b00de4595763a7d577bed524
Original-Change-Id: I95c79fe40d3ad79f37ce2eb586836e5de55be454
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/308980
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12229
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Certain Lexar USB disks may fail during the first calls to
get_descriptor(..., DT_CFG, ...) for unknown reasons. Therefore, make
several attempts before giving up.
BUG=chromium:466758
TEST=Manual on Samus. Go to recovery mode, verify that Lexar LJDS70 USB
stick is bootable.
BRANCH=None
Change-Id: I476ac22f9c4f844c60ebc6e53af8c144d70bb9d4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93a0570b343479dd22506ad4d7961f0ea4251f8c
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Change-Id: Ie581c7c71c53816065c7f59202581888a79e445e
Original-Reviewed-on: https://chromium-review.googlesource.com/302403
Original-Commit-Ready: Shawn N <shawnn@chromium.org>
Original-Tested-by: Shawn N <shawnn@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12133
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
If the device has already been disconnected then we shouldn't enable
host channel to start any transfer, otherwise this channel goes into
an odd state the channel is enabled but can not be disabled by set
hcchar.chdis=1. So we need check the device connect status before
enable channel.
BRANCH=None
BUG=chrome-os-partner:44534
TEST=None
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ae3e690b2cd4a9ea8b5766ac873b0e00bf3a23de
Original-Change-Id: Ib3ecf486649ca11b302144f9c00a5e88424e90fa
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/298402
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-(cherry picked from commit ea96f947b5304fdde2e0991d23febaeba209dde1)
Original-Reviewed-on: https://chromium-review.googlesource.com/299398
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Idf48ffbc4c2794900e09dec6b2e34e33b21f87b4
Reviewed-on: http://review.coreboot.org/11662
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
When disconnect is detected in dwc2_split_transfer() the split
configuration registers should be cleared before return.
BRANCH=None
BUG=chrome-os-partner:44534
TEST=On Jerry, usb hot plug works with devices behind hubs
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 37594d8b4490b6d393d19d17d8e497db7de8817d
Original-Change-Id: Ie1eecec067305874513c6ceb95df4240dc393cd6
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295625
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-(cherry picked from commit d543e14cdc73bd549dd553c8d1d07672a1307981)
Original-Reviewed-on: https://chromium-review.googlesource.com/299700
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ib4604097743f2f9d763b29ee27f3bc1788a85a62
Reviewed-on: http://review.coreboot.org/11661
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Seems like our transferred bytes calculation for OUT transfers that span
more than one packet had been wrong, and we just got lucky that we never
noticed it before. The HCTSIZ.xfersize register field we're reading only
counts bytes transferred by the last packet we sent.
OUT endpoints cannot have short transfers -- every transfer should
either finish all bytes we wanted to send or end in a proper error
condition. Therefore, in the absence of an error we can just conclude
that all input bytes have been transferred.
BRANCH=veyron
BUG=chrome-os-partner:35525
TEST=SMSC95xx netboot on Jerry now works.
Change-Id: I57349e697c428df6b56e2f6f62e87652ef1e7a94
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 0abee13b6d89dec12c6fff581ece1836393c7703
Original-Change-Id: Id0a127e6919f5786ba05218277705dda1067b8c3
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293956
Original-Reviewed-by: yunzhi li <lyz@rock-chips.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/11404
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Check device connect status while waiting for usb transfer complete
Avoid coreboot get stuck when usb device unplugged
BUG=chrome-os-partner:35525
TEST=None
BRANCH=None
Original-Change-Id: Id103501aa0d8b31b0b81bef773679c0fad79f689
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292630
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292966
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Change-Id: I49396b74131dbfda505d9d3de5adbdc87eb92ce1
Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Reviewed-on: http://review.coreboot.org/11236
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The xhci_rh_port_status_changed() function tries to always clear all
port status bits, even though most of them don't interest us. This is
generally a smart thing to do since not clearing a status bit may cause
the controller to not generate any more Port Status Change Events.
However, the bitmask we currently use doesn't cover bit 23 (Port Config
Error Change) and instead covers bit 16 (Port Link State Write Strobe)
which is not really related to this and not a W1C bit. Probably a typo,
so let's fix that.
BRANCH=None
BUG=None
TEST=Plugged/unplugged a bunch of USB devices on an XHCI Falco.
Original-Change-Id: Ia83f5b72cce094859c0f0e730752d7b5cfa6e1c6
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291842
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I11f5fe38cb70055daf6e866a8ee84ca80488e3bf
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11194
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The 1.1 revision of the XHCI specification added an extra 5 bits to the
Max Scratchpad Bufs field of HCSPARAMS2 that newer controllers make use
of. Not honoring these bits means we're not allocating as many
scratchpad buffers as the controller expects, which means it will
interpret some uninitialized values from the end of the pointer array as
scratchpad buffer pointers, which obviously doesn't end well. Let's fix
that.
BRANCH=none
BUG=chrome-os-partner:42279
TEST=Makes a USB-related memory corruption issue disappear.
Original-Change-Id: I7c907492339262bda31cdd2b5c0b588de7df8544
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291681
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Iba1007bfebffe1f564f78bb875fff9ba0fe11a38
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11189
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
If short packet detected, stop this transfer and return the actual
transferred size
BUG=chrome-os-partner:42817
TEST=Netboot could run well
BRANCH=None
Original-Change-Id: Icb4317f48aa04ac15bb1886b81d2e3c472d123d0
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/288215
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-(cherry picked from commit d372343b4e3d664ce2d76dbf55a5061b5d496bba)
Original-Reviewed-on: https://chromium-review.googlesource.com/291064
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Change-Id: I43d9edffe2074c037f2df203621863e54d2597fa
Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Reviewed-on: http://review.coreboot.org/11187
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch re-adds a few fixes that originally went into the
chromeos-2013.04 tree. I kinda seem to have slipped them into the
backport of Nico's original XHCI patch (crosreview.com/168097) instead
of making a new change, which was not very clever and caused them to be
forgotten in the later upstreaming wave.
Changing internal XHCI error numbers is just a cosmetic change to make
them uniquely identifyable in debug output. Bumping the timeout to 3
seconds is an actually important fix since we have seen mass storage
devices needing that much in the past.
BRANCH=None
BUG=None
TEST=Diffed payloads/libpayload/drivers/usb between chromeos-2013.04 and
chromeos-2015.07, confirmed that no serious differences remain.
Original-Change-Id: I03d865dbe536072d23374a49a0136e9f28568f8e
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290423
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I5d773d3a23683fb2164916cc046f4a711b8d259e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11178
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Before the controller's destroy_device() could interrogate
the usbdev_t object usb_detach_device() was freeing and
NULLing out the pointer. That results in all callers who
needed that object to start accessing random bits of memory.
This eventually led into free()ing memory it shouldn't which
corrupted the allocator's state. Eventually, all forward
progress was lost by way of a single ended linked list
turning into a circular list.
The culprit seems to be a bad merge in commit e00ba21.
BUG=chrome-os-partner:43419
BRANCH=None
TEST=Can boot into OS now w/o "hanging" on glados.
Original-Change-Id: I86dcaa1dbaf112ac6782e90dad40f0932f273a1f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290048
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Change-Id: I9135eb0f798bf7dbeccc7a033c3f8471720a0de5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11173
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch adds support for the SuperSpeed half of USB 3.0 hubs, which
previously prevented SuperSpeed devices behind those hubs from working.
BRANCH=None
BUG=chrome-os-partner:39877
TEST=Played around with multiple hubs and devices on Oak and Falco, can
no longer find a combination that doesn't work.
Change-Id: I20815be95769e33d399b7ad91c3020687234e059
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3db96ece20d2304e7f6f6aa333cf114037c48a3e
Original-Change-Id: I2dd6c9c3607a24a7d78c308911e3d254d5f8d91d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/284577
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: chunfeng yun <chunfeng.yun@mediatek.com>
Reviewed-on: http://review.coreboot.org/10958
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We have been trying to avoid reassigning previously used USB addresses
to different devices since CL:197420, because some devices seem to take
issue with that. Unfortunately, that patch doesn't affect XHCI: those
controllers insist on chosing addresses on their own. The only way to
prevent them from reusing a previously assigned address is to not
disable that slot at all.
This patch implements address reuse avoidance on XHCI by not disabling
slots when a device is detatched (which may occur both on physical
detachment or if we simply couldn't find a driver for that device).
Instead, we just release as many resources as we can for detached
devices (by dropping all endpoint contexts) and defer the final cleanup
until the point where the controller actually runs out of resources (a
point that we probably don't often reach in most firmware scenarios).
BRANCH=none
BUG=chrome-os-partner:42181
TEST=Booted an Oak plugged into a Servo without having a driver for the
SMSC network chip, observed that it could still enumerate the next
device afterwards. Kept unplugging/replugging stuff until the cleanup
triggered and made sure the controller still worked after that. Also
played around a bit on a Falco without issues.
Change-Id: Idfbab39abbc5bc5eff822bedf9c8d5bd4cad8cd2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 88c6bcbc41156729c3c38937c8a4adebc66f1ccb
Original-Change-Id: I0653a4f6a02c02498210a70ffdda9d986592813b
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/284175
Original-Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10957
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
With split transaction, dwc2 host controller can handle full- and
low-speed devices on hub in high-speed mode. This commit adds support
for split control and interrupt transfers
BUG=None
TEST=Connect usb keyboard through hub, usb keyboard can work
BRANCH=None
Change-Id: If7a00db21c8ad4c635f39581382b877603075d1a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fb514b7f7f7e414fa94bfce05420957b1c57019
Original-Change-Id: I07e64064c6182d33905ae4efb13712645de7cf93
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/283282
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10956
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
dwc2 host core do not have a periodic schedule list, so try to send
an interrupt packet in poll_intr_queue() function and use frame
number read from usb core register to calculate time and schedule
transfers.
BUG=None
TEST=Tested on RK3288 with two USB keyboards(connect to SoC without
USB hub), both work correctly.
BRANCH=None
Change-Id: I16f7977c45a84b37c32b7c495ca78ad76be9f0ce
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3d0206b86634bcfdbe03da3e2c8adf186470e157
Original-Change-Id: Ie54699162ef799f4d3d2a0abf850dbeb62417777
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/280750
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: http://review.coreboot.org/10774
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This will make the code work with the different styles
of Kconfig (emit unset bools vs don't emit unset bools)
Roughly, the patch does this, and a little bit of fixing up:
perl -pi -e 's,ifdef (CONFIG_LP_.+?)\b,if IS_ENABLED\($1\),g' `find . -name *.[ch]`
perl -pi -e 's,ifndef (CONFIG_LP_.+?)\b,if !IS_ENABLED\($1\),g' `find . -name *.[ch]`
Change-Id: Ib8a839b056a1f806a8597052e1b571ea3d18a79f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10711
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Found in rockchips rk3288 as used in google/veyron.
BUG=None
TEST=None
BRANCH=None
Change-Id: I2f2c36c5bea3986a8a37f84c75608b838a8782ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 59a0bcd97e8d0f5ce5ac1301910e11b01e2d24b1
Original-Change-Id: Ic89ed54c48d6f9ce125a93caf96471abc6e8cd9d
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/272108
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: http://review.coreboot.org/10689
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Used command line to remove empty lines at end of file:
find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \;
Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/10446
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
1. There is a mis-understanding to calculate the value of TD Size
in Normal TRB. For MTK's xHCI controller it defines a number of
packets that remain to be transferred for a TD after processing
all Max packets in all previous TRBs, that means don't include the
current TRB's.
2. To minimize the scheduling effort for synchronous endpoints in xHC,
the MTK architecture defines some extra SW scheduling parameters for
HW. According to these parameters provided by SW, the xHC can easily
decide whether a synchronous endpoint should be scheduled in a specific
uFrame. The extra SW scheduling parameters are put into reserved DWs
in Slot and Endpoint Context. But in coreboot synchronous transfer can
be ignored, so only two fields are set to a default value 1 to support
bulk and interrupt transfers, and others are set to zero.
3. For control transfer, it is better to read back doorbell register or add
a memory barrier after ringing the doorbell to flush posted write.
Otherwise the first command will be aborted on MTK's xHCI controller.
4. Before send commands to a port, the Port Power in PORTSC register should
be set to 1 on MTK's xHCI so a hook function of enable_port in
generic_hub_ops_t struct is provided.
Change-Id: Ie8878b50c048907ebf939b3f6657535a54877fde
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 738609c11f16264c6e6429d478b2040cb391fe41
Original-Change-Id: Id9156892699e2e42a166c77fbf6690049abe953b
Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/265362
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: http://review.coreboot.org/10389
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
BRANCH=none
BUG=none
TEST=none
Change-Id: I563ef65db900d7675aeb5b9123dfb5a8980bf964
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9764115d7bcce1d6423464bd81b58211ac728409
Original-Change-Id: Ibac8d3b9e28b4a563079f288901abcfbff6913ee
Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/269863
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: http://review.coreboot.org/10388
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
The EHCI driver never looked for the base address handed to
it but instead used an uninitialized field for that information.
Change-Id: I89fe0cc212092672b36e978083e3de78419b1eb5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/10179
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make the XHCI driver compile on ARM again. The Panther Point
specific shutdown handler is certainly _not_ necessary there.
Change-Id: I470afd4d82d101902b119b3ead4381e2b36a94b0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10091
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Since CL:170664, all SC_SPEED_XXX renamed to SC_SPEED1_XXX.
There is one missing in xhci_dump_slotctx() function which makes
compilation error.
BUG=none
TEST=enable USB_DEBUG and XHCI_DUMPS macros in xhci_private.h;
then emerge-auron libpayload
Change-Id: Ib96805cb7fc1cad17b205277539fb2120632f6f4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3ca0174e93ad131309ad07187c95c1e84c7d4fc5
Original-Change-Id: Id056b4684831a5717e87969e95ab17f11db29696
Original-Reviewed-on: https://chromium-review.googlesource.com/261414
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Harry Pan <harry.pan@intel.com>
Original-Tested-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: http://review.coreboot.org/9877
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The address of the output buffer sent to the device should be
the bus address and not the virtual address.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA and bring up board;
USB works properly after this change
BRANCH=none
Change-Id: I5c9d199e17c3f4303095ad73f4980d32d04c6118
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 942c385c112c2a4e409da806548081d3e2f8f438
Original-Change-Id: I0c06196501a968a72cb3f2c7dd1027bb22cdaada
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/245387
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9455
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Total FIFO length is split into 512 byte blocks.
Allocate these blocks to GRXFSIZ and GNPTXFSZ evenly.
This method avoids hardcoding and makes the FIFO size value
work for dwc2 controllers that have a different FIFO ram size.
BUG=chrome-os-partner:32634
BRANCH=None
TEST=Boot kernel from USB
Change-Id: I78ce0fa4c4600fb56c991874a93bdd6674e648c2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5645a25e95f84359cd10fc9fcf56e1f73fd6ce87
Original-Change-Id: Ib50a08c193f7f65392810ca3528a97554f2c3999
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/233119
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9454
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
BUG=chrome-os-partner:29778
TEST=emerge-veyron libpayload
Change-Id: I33f312a939e600b8f4e50a092bb61c5d6bc6d741
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 39ffe53336a2a3b2baa067cdd3dccca5ae93f68e
Original-Change-Id: Idad1ad165fd44df635a0cb13bfec6fada1378bc8
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211053
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9453
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Don't attempt to scan the PCI bus if the bridge is disabled. When
the PCI bridge is not setup and enabled, it is possible for the
secondary bus register to contain the value zero (0). In this case
the usb_scan_pci_bus routine gets into an infinite recursive loop
which ends only when the heap or stack is exhausted. This patch
verifies that the PCI bridge is enabled by verifying that it is
enabled for either memory or I/O operations. When enabled, the
secondary bus is scanned.
BRANCH=none
BUG=None
TEST=Build and run on Samus
Change-Id: I6826dc1d73b7c24729de5ac7c4d3534922ca73c5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 63d04b47934761351b54c847a2692bdef81ce54f
Original-Change-Id: I855240c52fa3eba841e6754816ebbcb824abc4cd
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/236382
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/8734
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If a TD is comprised of one or more Normal TRBs and terminated with an
Event Data TRB, then the transition to the Idle state (and associated
Stream state save) could occur after all the data for the TD has been
moved (e.g. after Transfer Event TRBs have been executed), but before the
Event Data TRB is executed. Under these conditions, the execution of the
Event Data TRB is necessary to complete the TD, otherwise it does not
occur until the next time the Stream is scheduled. This could lead to the
lock up.
The Evaluate Next TRB(ENT) flag provides a means of forcing the execution
of a terminating Event Data TRB. Setting ENT flag in last Normal TRB makes
the xHC to evaluate the Even Data TRB.
BUG=chrome-os-partner:29375
TEST=Verified kernel boot-up on storm from previously failing USB stick.
USB stick model: Sandisk Ultra USB 3.0 Pen Drive 32 GB
Strontium Jet USB 3.0 Pen Drive 32 GB
Change-Id: I092e2109c55c2274239c493cb67b47d730304ed2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7eefb3b2858c841165ae839d349d2a0be50fbcc8
Original-Change-Id: I4e123577ec5a5996d87d2fc52cb6cf5c571c9fae
Original-Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220123
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/8736
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
If EHCI controller has TT (Transaction Translator) support in
root-hub, then we need to keep control over this controller when
USB keyboard (low-speed device) is connected to root-hub port.
Need to add "CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT=y" to config file
(e.g. payloads/libpayload/configs/config.nyan_big) to support this
feature.
BUG=chrome-os-partner:32355
TEST=Tested on nyan_big platform.
Press ESC+REFRESH+POWER keys on internal keyboard to power up.
Press Left Arrow or Right Arrow on USB keyboard to switch between
"English" and "Default Locale" in coreboot UI. Or unplug and plug
in device and try again.
Root hub <- low-speed USB keyboard
Root hub <- full-speed hub <- low-speed USB keyboard
Root hub <- high-speed hub <- low-speed USB keyboard
Change-Id: Iaa2823f64c8769fc808ee7a316c378f18f004e63
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4ad57fd673d6dc8814fe99a4ac420566bb17e77b
Original-Change-Id: Id86a289bc587653b85227c1d50f7a4f476f37983
Original-Signed-off-by: Jim Lin <jilin@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/220125
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8737
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Chapter 3.1 "Periodic Frame List" of EHCI 1.0 specification says
"Frame List Link pointers always reference memory objects that are
32-byte aligned."
jwerner@chromium.org suggests setting it to be 64-byte aligned for
consistency with other EHCI queue structures.
BUG=chrome-os-partner:31993
TEST=Tested on nyan platform. Before adding patch, USB keyboard behind
an external hub is not working to switch between "Default Locale" and
"English" (after pressing ESC+REFRESH+POWER on embedded keyboard and
later Left/Right-Arrow key on USB keyboard).
Change-Id: Ie6259f2df20ae2618c2074e831fad087f227091d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 23fc02e6ba3b17be4eaf18810ec6fc0d9c0e0b9a
Original-Change-Id: If52ddc43ebd5d509c19f104928dced5bd09b1706
Original-Signed-off-by: Jim Lin <jilin@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/218403
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8738
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Data toggle should be running like 0, 1, 0, 1, ...
In the failed case (where a low-speed USB keyboard or km232 device
is installed), data toggle will be running as 0, 1, 0, 1, ..., 1, 1.
Therefore causing Halted or Transaction Error bit to be set in qTD
Status field.
BUG=None
BRANCH=None
TEST=Tested on nyan_kitty platform, firmware-kitty-5771.61.B branch.
Attached USB keyboard or km232 device to root-hub port (same side as
SD card slot).
Made sure no transaction error after doing interrupt transfer.
Change-Id: I576f3c583dae4c279a6e0e8ffdfce5abe463277d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64b0428aaab869e20f6720669e953acf82ecb846
Original-Change-Id: Ic2c0f95cff2ae6e314967b0b82231a962255f1a7
Original-Signed-off-by: Jim Lin <jilin@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/233857
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8747
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Some USB sticks seem to send a NAK at a place where they mustn't
by spec, leading to a controller side error condition.
To avoid it, wait a millisecond which is enough to get past the
NAK condition. That delay only happens on device discovery so it
won't affect boot time by more than 1ms per device.
BUG=chromium:414959
BRANCH=none
TEST=depthcharge recognizes a Lexar 16GB USB stick after applying
this change.
Change-Id: I0e385702a5259b16fda0a253fc121d8f66e6705c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 10bbfda8395af009e7f910cc503f50c2ad969ae8
Original-Change-Id: I6dd5ca34e9f3767003ccb0ca9daaf16116f4a2df
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228791
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Reviewed-on: http://review.coreboot.org/8735
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
EHCI driver accesses mmio space using regular struct pointers. In order to avoid
any CPU re-ordering, memory barrier is required in async_set_schedule,
especially for arm64. Without the memory barrier, there seems to be re-ordering
taking place which leads to USB errors with some flash drives as well as
transfer errors in netboot.
BUG=chrome-os-partner:31533
BRANCH=None
TEST=With the memory barrier introduced, netboot for ryu completes transfer
without any error and finishes within 6-7 seconds.
Change-Id: Ib6d29dc79fd5722c27284478e8da316929e86bff
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 561bdd746c4d4446ce0a6d21337d354625d85ddc
Original-Change-Id: Ic05d47422312a1cddbebe3180f4f159853604440
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/213917
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8732
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
`di` points to a single item in xhci->dev[], which is malloc'd
collectively. Trying to free() leads to pain.
Change-Id: Ibd99eda905d43cbf2d2c111dfd0186ed6b119329
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8515
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Elyes HAOUAS