Our current cbfstool has always added a compression attribute to the
CBFS file header for all files that used the cbfstool_convert_raw()
function (basically anything other than a stage or payload), even if the
compression type was NONE. This was likely some sort of oversight, since
coreboot CBFS reading code has always accepted the absence of a
compression attribute to mean "no compression". This patch fixes the
behavior to avoid adding the attribute in these cases.
Change-Id: Ic4a41152db9df66376fa26096d6f3a53baea51de
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some LPC debug boards hard strap SIO address to be at
0x164e/0x164d vs 0x4e/0x4d. Add support for configurable
SIO address to support these cards.
BUG=b:159933344
TEST=boot with LPC debug card, verify serial output
Change-Id: I103c61f21f13970dfa3b9a788b29964e478fb84c
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Save for the IO_APIC2_ADDR definition, they are equivalent.
Change-Id: I14da3d9aeefcc725428957ce0c9ac164eabacec6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47408
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only two definitions are actually used somewhere, the rest is unused.
Change-Id: Iec52d0d47fce6a1ec5455b670824b995a7a34a4c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47407
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the mainboard_ops driver and configure the GPIOs using .init,
since mainboard_silicon_init_params() is meant for the configuration of
the FSP, not the GPIOs.
Change-Id: I82f1eaf6693d9b117fb211776047058cdc787288
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This option only applies to boards using the Lenovo H8 EC code.
Change-Id: I3b16a61a0aa9f51a4061b1b5e58fc276e7383415
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47150
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only Sandy Bridge MRC stores scrambler seeds in CMOS. Non-Sandybridge
boards ended up with these entries because of copy-paste programming.
Change-Id: I5a5bda6ea4e63ba03a4219bb2a6aa546bb6ecd7a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47149
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
update the DPTF parameters received from the thermal team.
BUG=b:167523658
TEST=emerge-volteer coreboot
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Iafc3fb389ade5cfec79a816a28880262bdce7c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47858
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SMI handler was not installed for Xeon_sp platforms. This enables SMM
relocation and SMI handling.
TESTED:
- SMRR are correctly set
- The save state revision is correct (0x00030101)
- SMI's are properly generated and handled
- SMM MSR save state are not supported, so relocate SMM on all cores
in series
- Verified on OCP/Deltalake mainboard.
NOTE:
- Code for accessing a CPU save state is not working for SMMLOADERV2,
so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS
pointer are not supported.
- This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS
is broken and needs to be fixed separately. It is unknown if TCO is
supported. This might require a cleanup in the future.
Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46231
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TCO is configured by FSP. This mostly makes it possible to report TCO
events in SMM if enabled.
Change-Id: I4f81c7888e45ed01ee68b1d6e6a9986a4d735467
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47764
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The soc code was already there but it was never linked.
Change-Id: I75ee08dab524bc40f1630612f93cbd42025b6d4e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47763
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allows advertising support for a 1ch array DMIC in the NHLT table.
Boards use the NHLT if a microphone is connected to the DSP.
Tested on an Acer Aspire VN7-572G (Skylake-U) on Windows 10.
A custom ALSA topology will be required for Linux.
Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
According to the NHLT specification[1], PDM_DEV is defined as "1" on
Kabylake based platforms. coreboot currently sets it to "0" on
all platforms. Add an entry to the enum and use it to define
NHLT_PDM_DEV for Kabylake.
"Device Type" will resume from "2" on all platforms, but entries are
currently reserved.
Tested on an Acer Aspire VN7-572G (Skylake-U), which has a 1ch array
DMIC, on Windows 10.
1. https://01.org/sites/default/files/595976_intel_sst_nhlt.pdf
Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45010
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow the example of newer AMD code for Stoneyridge and Picasso.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I9c17d4cb4953b28a47483f5d7db308ccc89e9281
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Following the example of CB:7630 done for family16kb boards
(git commit 3ff4f85ccd).
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ic48c7475ceadb60f825ca9e3c3427c8a7525a266
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0".
correct rx_vref_tune -> tx_vref_tune
BUG=None
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I27003a952d8f8bdd8fe52af8a37010e23ee9cdfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Code was copy-pasted from older chips and has no effect on Lynxpoint.
Change-Id: I2c789ba48f175b3c9c9643118fc2209c94f24c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
TEST=Boot with an i3-9100F and see no vr_config errors.
Change-Id: Ic62ef038ad11d147a38804f694d3e056611b96db
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47445
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Split up gpio.h into two seperate compilation units, gpio.c and
gpio_early.c, containing the complete configuration and a minimal
configuration used in early stages.
Tested on clevo/l140cu and it still boots.
Change-Id: I5b056e8faac0c426a37501dbc175373c22dde339
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Get rid of cnl_configure_pads() since it is a hack for the FSP. Instead,
hook up to the mainboard_ops driver and configure the GPIOs using .init.
Tested on clevo/l140cu and it still boots.
Change-Id: I75dd15ab6d2b3b72b3ad0398df87b349fd00bc3c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Move hda_verb.c from the variant's Makefile to the mainboard's Makefile,
because every variant needs one.
Change-Id: Ia94813f68620abcff48de4fdb117466c91f6863c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47820
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Nico Huber and Felix Singer as maintainers for the mainboards
siemens/chili and kontron/bsl6.
Change-Id: Ic70004d6f4c87b308246031429794312cc37107a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Time has shown that using spaces never converges into proper alignment.
Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Most of these comments have been copy-pasted or serve no purpose other
than to eventually turn into misleading info. While the description of
the first 120 bits of CMOS could be useful, it should instead be added
to the documentation for the CMOS option infrastructure, or /dev/null.
Moreover, trim down newlines to no more than two consecutive newlines.
Change-Id: I119b248821221e68c4e31edba71ba83b7d2e14e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
List of changes:
1. Configure CTRLCLK and CTRLDATA for HDMI
2. Enable Ddc and HPD for Port-B
3. Disable dual eDP configuration for Port-A and B
TEST=Able to see depthcharge pre-boot screens over HDMI-B port.
Change-Id: I7509b981f35fc60a7885b2b07067cb0d35ec625f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
According to the latest Alderlake Platform FSP Integration Guide, the
minimum amount of stack needed for FSP-M is 512KiB. Change
DCACHE_RAM_SIZE and DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB
previously determined empirically).
TEST=Able to pass FSP-M MRC training on LPDDR5 SKU without any hang.
Change-Id: Ic831ca9110a15fdb48ad31a7db396740811bf0f2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This turns on the compiler's printf style format string checker.
BUG=b:167517417
TEST=enabled all USB controllers on volteer and fixed resulting
compiler errors when USB_DEBUG is enabled.
Change-Id: Ic94ebcbafdde8a5f79278b5635111b99af40f892
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45025
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This fixes format string mismatch errors in the USB subsystem found by
the compiler's format string checker.
BUG=b:167517417
TEST=enabled all USB controllers on volteer and fixed resulting
compiler errors when USB_DEBUG is enabled.
Change-Id: I4dc70baefb3cd82fcc915cc2e7f68719cf6870cc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
BAR address used during early initilization of GPSI 2 is overlapping with UART bar.
//For GSPI2 this is the address calculated
GSPI_BUS_BASE(0xFE030000,2)=0xFE032000
GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB)
//overlaps with
CONSOLE_UART_BASE_ADDRESS -> 0xfe032000
TEST=none
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3249a91df8a2e319aff6303ef9400e74163afe93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
BAR address used during early initilization of GPSI 2 is overlapping with UART bar.
//For GSPI2 this is the address calculated
GSPI_BUS_BASE(0xFE030000,2)=0xFE032000
GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB)
//overlaps with
CONSOLE_UART_BASE_ADDRESS -> 0xfe032000
Change-Id: Id9f2140a6dd21c2cb8d75823cc83cced0c660179
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add test case executed twice, once for ROMSTAGE and once RAMSTAGE.
Each test is named and visible in cmocka output with stage in its name.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I464eee61f538188427bec730d2e004c7b76cca67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Implements the monotonic timer using the am335x dmtimer peripheral.
Change-Id: I4736b6d3b6e26370be9e8f369fc02285ad519223
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44383
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enables the MMU primarily to allow the unaligned word reads that the
FMAP code requires. Without enabling this, the chip gets data access
exceptions.
Enabling the MMU also gives some advantages in allowing the icache and
dcache to be enabled, so is probably worth doing regardless.
Change-Id: Ic571570cc44b0696ea61cc76e3bce7167a3256cf
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Julius Werner