The printk has no effect as console_init() hasn't been called.
Also drop unused variables and headers.
Change-Id: I5bf5a8822c69bbcc3de1de460d19585b8330649f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
This string is printed in dump_te_table() so we should make sure it's
properly null-terminated.
This fixes Coverity issue 1401305.
Change-Id: I45827f552c2d8a4e01b50a699ac88ee457043282
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
UART RX needs to be re-initialized in libpayload
as it is getting reset at the end of coreboot.
Change-Id: I7820bd7afd2e5f81e21a43f330ed42d3a732d577
Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
By default, the LPC SIRQ mode is set to Quiet mode. Therefore, COM-port
from the SurerIO chip don't work correctly after the LPC controller (PCI
0:1f.0) initialization. Console output is broken. The patch fixes this
bug by overriding the serirq_mode option in the devicetree.cb to set
Continuous SIRQ mode
Change-Id: I37e26b271fb61f6c0343d6bf65c029924df82caf
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33801
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add files to introduce a memory clearing framework.
Introduce Kconfig PLATFORM_HAS_DRAM_CLEAR that is to be selected by
platforms, that are able to clear all DRAM.
Introduce Kconfig SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT that is user
selectable to always clear DRAM on non S3 boot.
The function security_clear_dram_request tells the calling platform when
to wipe all DRAM. Will be extended by TEE frameworks.
Add Documentation for the new security API.
Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Depthcharge no longer reads this data structure, and uses
the vboot workbuf in vboot_working_data instead.
Since vboot2 downstream migration is not yet completed, the
vboot2 -> vboot1 migration code is still required, but has
been relocated to depthcharge.
BUG=b:124141368, b:124192753
TEST=make clean && make runtests
BRANCH=none
Change-Id: I769abbff79695b38d11fb6a93c2b42f64d4bafde
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33535
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A FPMCU power-control pin (GPP_C11) is added to the latest
hatch reference schematic.
Even though this is not implemented in hatch rev1 board, the future
hatch family boards with FPMCU should all have this control pin.
On the old boards without this control pin, GPP_C11 is a floating TP,
and thus this patch should be backward-compatible.
BUG=b:130307667, b:135216932
TEST=build
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: I6a84eeb6aab562258e749a8a5d09dadfa0e43587
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is no need to add internal termination (PU/PD) on the
not-connected pads. This change gets rid of the terminations on the NC
pads.
Change-Id: I3df538d7127e5ef75e6e6ff9db3524e26f0450ed
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This allows to use Kconfig options to differentiate between SOC
variants.
Change-Id: Ica11c68377e3d0dc8a8f48198e01a74d7bebe642
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33559
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is causing coreboot build in Chromium OS to fail.
BUG=None
TEST=emerge-eve coreboot
BRANCH=none
Change-Id: I4faa140b3046651b4ed0a9aeefe437048c6ef0da
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The value for that macro should be 1<<19. This is confirmed by the
Intel doc and also by N_PCH_GPIO_RX_SCI_ROUTE.
See Intel Atom® Processor C3000 Product Family Datasheet
(February 2018) :
https://www.intel.com/content/www/us/en/products/docs/processors/atom/c-series/c3000-family-datasheet.html
Signed-off-by: Patrick Havelange <patrick.havelange@essensium.com>
Change-Id: I808d9131032a9796d837e00ad6fb3369b792e597
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33573
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CBFS_SIZE equals size of whole SPI device.
The descriptor and ME need to be placed in bottom part.
Reduce the CBFS_SIZE to maximum avalaible size.
BUG=N/A
TEST=Boot Embedded Linux 4.20 on Facebook FBG-1701
Change-Id: Iecfae4573100c6787b6e8b1c4f2583a7fb3d95a3
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
tc348860_table contains the eDP to MIPI Bridge controller type.
b101uan08_table used the LCD Panel type.
Use LCD Panel type for name of tables.
Remove the incomplete resolution comments and specify the resolution at
the start of the table to 1200x1920.
BUG=N/A
TEST=Config eDP and verify LCD panels are working on Facebook FBG-1701
Change-Id: Ic152ea1f95f155ab76638b57a259d37ce6f43037
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33736
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It seems that the EC on t60/x60/z61t doesn't support it. This wasn't
even introduced in z61t so let's remove the remaining bits.
This commit follows up on commit a5fcc2e4 with Change-Id
Id2964002406a5fcf992f0ffc3627e3f66a2bb13f ("mb/lenovo/x60/t60: Remove
`fn_ctrl_swap` option").
Tested on a real hardware.
Change-Id: Ifd5e7823af305cc4a0194ee2097a749e43680c55
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Andrey Korolyov <andrey@xdel.ru>
Sometimes coreboot needs to compile external code (e.g.
vboot_reference) using its own set of system header files. When
these headers don't line up with C Standard Library, it causes
problems.
Create ctype.h header file. Relocate ctype.h functions from
string.h into ctype.h. Update source files which call ctype.h
functions accordingly.
Note that ctype.h still lacks five functions which are not used
in coreboot source:
isalnum, isalpha, iscntrl, isgraph, ispunct
BUG=b:124141368
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I31b5e8af49956ec024a392a73c3c9024b9a9c194
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Describe how to run coreboot on the PC Engines apu2 mainboard.
Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581
Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Describe how to run coreboot on the PC Engines apu1 mainboard.
Change-Id: If79693e893c4afe52bf1c9aa8017ac6f650a96e4
Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested with SeaBIOS as a payload, booting Arch Linux with
a Linux kernel. The new code is based on autoport and the
existing GA-H61M-S2PV code.
The GA-H61M-S2PV has been boot-tested too, it still boots.
Working:
- S3 suspend/resume
- USB ports and headers (Intel USB2 and EtronTech USB3)
- Gigabit Ethernet
- Integrated DVI/VGA graphics (libgfxinit)
- PCIe x16 graphics
- PCIe x1 ports
- PS/2 port with a keyboard
- SATA controllers (Intel SATA2 and Marvell SATA3)
- User-space fan control (fancontrol on Linux)
- Native raminit (4+4GB DDR3-1333)
- flashrom, using the internal programmer. Tested with coreboot,
as well as with the vendor firmware. Backup chip is untested.
Untested:
- VGA BIOS for integrated graphics init
- Audio: Only front/read outputs has been tested.
- Non-Linux OSes
- ACPI thermal zone and OS-independent fan control
Not working:
- Default IFD defines the BIOS region as the entire flash chip.
Using 'flashrom --ifd -i bios' is asking for a failed flash!
Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The ifittool is used instead. Drop old code.
Change-Id: I70fec5fef9ffd1ba3049badb398783f31aefb02f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Depend on ifittool and use it to update FIT instead cbfstool FIT code.
Move the TOPSWAP / microcode handling out of cbfstool and implement it
in the Makefile.
The new FIT looks like the old one and has been tested on Broadwell-DE.
The TOPSWAP / microcode code path needs test on real hardware.
Change-Id: I687469d62557f81e9d88398cfc93182164fdac95
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Add the IntelFirmwareInterfaceTable-tool to modify the FIT.
As cbfstool is overloaded with arguments, introduce a new tool
to only modify FIT, which brings it's own command line syntax.
Provide clean interface to:
* Clear FIT
* Add entry to CBFS file
* Add entry to REGION
* Delete entries
* Add support for types other than 1
* Add support to dump current table
* Add support for top-swap
* Sort entries by type
Most code is reused from existing cbfstool and functionality of cbfstool
is kept. It will be removed once the make system uses only ifittool.
Based on "Intel Trusted Execution Technology (Intel TXT) LAB Handout"
and https://github.com/slimbootloader/slimbootloader .
Change-Id: I0fe8cd70611d58823aca1147d5b830722ed72bd5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This patch relying on new rule, ENV_PAYLOAD_LOADER which is set
to ENV_RAMSTAGE.
This approach will help to add future optimization (rampayload) in
coreboot flow if required.
Change-Id: Ib54ece7b9e5f281f8a092dc6f38c07406edfa5fa
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
On RISC-V the argument to a payload is always the hartid and a pointer to a FDT.
selfboot sets the coreboot tables as an argument, work around this here.
Change-Id: If6929897c7f12d8acb079eeebaef512ae506ca8b
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31477
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fixes a logic error that sets MPIE, but didn't use mret to return to the payload.
This left MIE set to an undefined value.
Now all modes are handled the same way:
- Trap vector base address point to the payload
- Disable Interrupt
- Return to payload using mret
TEST=Run an M-mode payload
Change-Id: Iaab595f916949c57104ec00f8b06ea047fe76bba
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33462
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FBG1701 contains a TC358860 eDP to MIPI Bridge controller which needs
to be configured.
Add mainboard_configure_edp_bridge() to program the controller.
CPLD version is used to determine which table must be programmed.
The eDP is an i2c slave which expects the next i2c bus data for block
write:
<Slave Addr> <Reg Addr[15:8]> <Reg Addr[7:0]> followed by data with LSB
first.
BUG=N/A
TEST=Config eDP and verify LCD panels are working on Facebook FBG-1701
Change-Id: I262cb4376b86db94e3bb9522c556b5cc3ff38335
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The SUPERIO_NUVOTON_NCT6776_COM_A symbol should only be visible if
SUPERIO_NUVOTON_NCT6776 is selected as well.
Change-Id: I9c52d596080360bf3fc25265749ced66ec44f5dc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33440
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The asrock/h110m has a NCT6791D, but is selecting the NCT6776-specific
SUPERIO_NUVOTON_NCT6776_COM_A symbol. Use the NCT6791D symbol instead.
Change-Id: I9f3fde161844f919b070f2b6ce7e106411439a9a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <m.poliakov@yahoo.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Like the NCT6776, the NCT6791D has muxed COMA/GPIO8 functions. Since it
requires setting different bits, add a new Kconfig symbol to do it.
Change-Id: I62dc18810026f9b1550da19950f66af605600ec8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <m.poliakov@yahoo.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
ALIGN((a), b) and ALIGN_UP(a, b) needs 'helpers.h'
Change-Id: I029c7c5cbb19c7e69997b3d84f929cb61e8e2b23
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Enable decoding the IPMI KCS to LPC
* Select the IPMI driver
* Add the PNP device that holds the IPMI KCS base address
Tested on Wedge100s.
Change-Id: I35634bbcbe6893bd72ec7e41f6ca7bba09d819a2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Add chips ops for IPMI KCS.
* Get IPMI version over KCS.
* Generates ACPI SPMI table for IPMI KCS.
* Generates SMBIOS type 38 for IPMI KCS.
* Generates ACPI SPMI device for IPMI KCS on LPC device.
* Add documentation
To use this driver on BMC that support KCS on I/O:
1. Add an entry to the devicetree.cb:
chip drivers/ipmi
device pnp ca2.0 on end # IPMI KCS
end
2. Select IPMI_KCS in Kconfig.
3. (Optional) enable LPC I/O decode for the given address.
Tested on Wedge100s.
Change-Id: I73cbd2058ccdc5395baf244f31345a85eb0047d7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The ALIGN_UP macro is basically an alias of the ALIGN macro; with this change
it's more obvious in which direction the alignment happens.
Change-Id: I6f1b9f9bbcafeb85a6ef5c10ce4b57edc0740e72
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Patrick Rudolph