Commit Graph

49558 Commits

Author SHA1 Message Date
Subrata Banik 4e85ec705e soc/intel/alderlake: Create helper header file for UFS
This patch creates helper header file (ufs.h) for UFS to keep
required registers details and ACPI device id for UFS.

BUG=none
TEST=Able to build and boot Google/Kano.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If08c54eb706876a4255542a708aa5fcd8bf43c55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68299
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-14 16:04:15 +00:00
Subrata Banik 9fb58575d6 soc/intel/alderlake: Add UFS PCR ID
Add UFS PID (`PID_UFSX2`) value 0x50.

BUG=none
TEST=Able to build and boot Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I229469475cd116bf911b6530c3c819d00c808aa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68298
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 16:03:28 +00:00
Tinghan Shen 2caa2fc56e soc/mediatek/mt8186: Add DEVAPC settings for ADSP
Add DEVAPC permission settings for ADSP and set its domain number to 6.

TEST=SOF driver is functional.
BUG=b:204229221

Change-Id: I37bfea70386af953e89f3c38ac51e41af6aafa6e
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68290
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 16:03:06 +00:00
Tinghan Shen a9e595770f soc/mediatek/mt8186: Inititalize ADSP
To use SOF correctly, we need to initialize ADSP in coreboot stage.

TEST=SOF driver is functional.
BUG=b:204229221

Change-Id: I45db587252ccdcdf75e0be2029743034a79925c5
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68289
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 16:02:29 +00:00
Mandy Liu 55a1ba3043 soc/mediatek/mt8186: Add mtcmos power-on control for ADSP
To use SOF correctly, we need to enable power domain of ADSP.

TEST=SOF driver is functional.
BUG=b:204229221

Signed-off-by: Mandy Liu <mandyjh.liu@mediatek.com>
Change-Id: I39d1357af5f901a91379fdf7e595f16952b962de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68288
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 16:01:56 +00:00
Mandy Liu f32d1e3acb soc/mediatek/mt8186: Enable ADSP clock
To use SOF correctly, we need to enable ADSP clock.

TEST=SOF driver is functional.
BUG=b:204229221

Signed-off-by: Mandy Liu <mandyjh.liu@mediatek.com>
Change-Id: Ia17db889829df2668cf2af1b71c6468230de68e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68287
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 16:01:23 +00:00
Kapil Porwal bd3d197723 mb/google/rex: Add initial fw config
Add initial fw config as per config.star.

BUG=b:253199788, b:245158908, b:244113761, b:244012065
TEST=emerge-rex coreboot. Make sure that ACPI tables are equivalent
before and after this change with CBI.FW_CONFIG set to 0x1561.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I66f8b3e4ab414c03b8d63fdd31e0f3f424619340
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68220
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 16:01:04 +00:00
Eran Mitrani ef9cde146b mb/google/rex: Add FW_CONFIG* to Kconfig
BUG=b:253199788
TEST=Build and boot to Google/Rex.

Change-Id: Ib729c98a4d67aa46992fdccf592010b0313605a6
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66817
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 16:00:50 +00:00
Reka Norman ff207d7874 mb/google/nissa/var/yaviks: Remove fw_config probe for storage devices
When fw_config is unprovisioned, devicetree will disable all probed
devices. However, boot-critical devices such as storage devices need to
be enabled.

As a temporary workaround while adding devicetree support for this,
remove the fw_config probe for storage devices so that all storage
devices are always enabled. On eMMC SKUs, UFS and ISH will be disabled
by the PCI scan anyway. On UFS SKUs, eMMC is not disabled by the PCI
scan, but keeping it enabled should have no functional impact, only a
possible power impact.

BUG=b:251055188
TEST=On yaviks eMMC and UFS SKUs, boot to OS and
`suspend_stress_test -c 10`

Change-Id: I6b3a20f3c14d5e9aa8d71f6ca436b5a682310797
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68365
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 16:00:03 +00:00
Yidi Lin 677d4ebdd2 Update arm-trusted-firmware submodule to upstream master
Updating from commit id 7805999e6:
2022-09-05 16:42:34 +0200 - (Merge changes from topic "st-nand-updates" into integration)

to commit id c45d2febb:
2022-10-12 15:56:24 +0200 - (Merge "fix(ufs): retry commands on unit attention" into integration)

This brings in 288 new commits.

Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: I4137cab0a1a352e94e21f105717ae0b6c515b75b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68386
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-10-14 15:59:27 +00:00
Ian Feng 9ace946c23 mb/google/nissa/var/xivu: Config I2C frequency
1.Change the TPM I2C freqeuncy to 1 MHz for xivu.
2.Config same settings as the baseboard for I2C buses 1-5.

BUG=b:249953477
TEST=On xivu, all timing requirements in the spec are met.
Frequencies:
1. I2C0 (TPM): 974.3 Khz
2. I2C1 (TouchScreen); 375.5 Khz
3. I2C3 (Audio): 389.0 Khz
4. I2C5 (Touchpad): 388.5 Khz

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I33f712c14978b95f3a4da82d6f1f5fbae1283b17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-10-14 15:59:14 +00:00
Zhixing Ma 30e8fc1f4e soc/intel/alderlake: Fix unknown voltage in SMBIOS
The current SMBIOS for coreboot is missing processor info for Alder Lake and Raptor Lake SoC, specifically, voltage, max speed,
and upgrade (socket type). This patch implements voltage function.
Refer to SMBIOS spec sheet for documentation:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf

BUG=NONE
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that SMBIOS processor voltage value is correct.

Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I77712b72fa47bdcb56ffddeff15cff9f3b3bbe86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68023
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 15:58:46 +00:00
Zhixing Ma eb35327681 soc/intel/alderlake: Fix unknown max speed in SMBIOS
The current SMBIOS for coreboot is missing processor info for Alder Lake
and Raptor Lake SoC, specifically, voltage, max speed,
and upgrade (socket type). This patch implements max speed function.
Refer to SMBIOS spec sheet for documentation:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf

BUG=NONE
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that SMBIOS max speed value is correct.

Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I09bcccc6f97238f7328224af8b852751114896fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67913
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 15:58:33 +00:00
Felix Held e109a6a47f mb/amd/padmelon/bootblock/OemCustomize: add TODO for Prairie Falcon
The PCIe port descriptor list seems to be specific to Merlin Falcon and
Prairie Falcon has a different PCIe root port configuration. Since I
neither have the board nor the different APUs, I just add a comment
about this instead of trying to come up with a PCIe port descriptor list
that may or may not work properly on Prairie Falcon APUs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8e1eb67a8f684297bbefc6e2593250d7bd45593f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-14 15:38:30 +00:00
Felix Held 2595946bcd soc/amd/stoneyridge: move northbridge ops to northbridge device
The northbridge ops should be added to the actual northbridge and not
the first HT device. Neither of the devices has BARs on it, so
read_resources implementation will still work correctly.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2e5f21bfe5fff043d7d9afafa360764203dd61f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68409
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 15:36:40 +00:00
Felix Held 26651c85a0 soc/amd/stoneyridge: use devicetree ops over pci driver
Stoneyridge is a SoC so it makes sense to statically use ops instead of
matching them to PCI DID/VID at runtime. In contrast to the other AMD
SoCs in the coreboot tree the PC driver used the PCI ID of the first HT
PCI device function, so add the ops to the device 0x18 function 0
devicetree entry in this patch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I500521701479aa271ebd61e22a1494c8bfaf87fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68408
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 15:36:21 +00:00
Felix Held a11b472fd3 soc/amd/stoneyridge: Hook up device_operations in chipset.cb
This removes the need for a lot of boilerplate code in the soc code to
hook up device_operations to devices.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id668587e1b747c28207b213b985204b7a961a631
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68410
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 15:35:25 +00:00
Maximilian Brune 97a86734d2 mb/prodrive/atlas: Print HSID
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ibb7aac1204bc297d16797cac5b32b119d0a9204b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68224
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-14 11:55:35 +00:00
Subrata Banik 8d70cf71a4 mb/google/rex: Implement WIFI SAR related changes
1. Add CHROMEOS_WIFI_SAR to include the SAR configs.
2. Add get_wifi_sar_cbfs_file_name() that return the wifi SAR
   filename.

BUG=none
TEST=emerge-rex coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia863eaa53c9456ae0e9f0e8914e0de497a32b53b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68393
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-14 08:50:19 +00:00
Felix Held 6dbded495e mb/google/kahlee/*/devicetree: disable unused PCIe root ports
Disable the unused PCIe root ports that are disabled in the PCIe port
corresponding descriptor list passed to AGESA/binaryPI. This descriptor
list is in src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
and it only has B0D2F2 (gpp_bridge_1) and B0D2F4 (gpp_bridge_3) enabled.
Since the PCIe engines marked as unused in the port descriptor list
won't show up as PCI devices, don't enable those PCI devices in the
devicetree so that coreboot won't complain about static PCI devices not
being found on the PCI bus.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If8378e343a2eb13de66171cf4f38d77ae3401016
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68382
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-10-14 00:07:53 +00:00
Felix Held 2c341c1fea mb/google/kahlee/*/devicetree: use device aliases
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I63b1053d36b284ed95b015c0b4b26bdf8e162e67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68381
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 00:07:01 +00:00
Felix Held f19677aee8 mb/amd/padmelon/devicetree: use device aliases
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I509daac75c80bdca808706f783b04843209cc313
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68380
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 00:01:46 +00:00
Felix Held 61b50a64bf mb/amd/gardenia/devicetree: disable unused gpp_bridge_2
The board's PCIe port descriptors have the PCIe engine disabled, so
update the devicetree accordingly.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic97a54c3cc762a36752d6b9f21467428912a9edd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68379
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 00:00:48 +00:00
Felix Held 4c1a389828 mb/amd/gardenia/devicetree: use device aliases
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9a429c0fd23eb3b52a19a974b22079d675e3506a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68318
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 00:00:06 +00:00
Felix Held a5f11ebdd7 mb/amd,google/*/devicetree: drop CPU cluster device for Stoneyridge
Since commit 60e9114c62 ("include/device: ensure valid link/bus is
passed to mp_cpu_bus_init"), no dummy LAPIC device is required under the
CPU cluster device. Since the CPU cluster device is already present in
the Stoneyridge chipset devicetree, drop the whole CPU cluster part from
the mainboard's devicetrees.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8918c14be25ac9756926a9c6a2806a3dceced42a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68317
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13 23:59:15 +00:00
Felix Held b68e22409d soc/amd/stoneyridge: add chipset devicetrees
Add chipset devicetrees for Stoneyridge and Carrizo, which is also
supported by the Stoneyridge code, but has more external PCIe ports and
devices. The mainboard's devicetrees will be changed to use the aliases
defined in the chipset devicetree in follow-up patches. This is a
preparation to statically assign the ops for the internal devices
statically in the SoC devicetree instead of dynamically adding them in
ramstage.

BKDG #55072 Rev 3.04 was used to check the PCI devices and functions and
the MMIO addresses.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia45260b1168ed1d99993adfb98475da5b5c90d11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68316
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13 23:58:22 +00:00
Felix Held b16a87d16a mb/amd/padmelon: enable PCI device 3.1 for Merlinfalcon
When using a Merlin Falcon APU, explicitly enable the PCIe root port at
B0D3F1. B0D3F0 is only a dummy PCI device function, but needs to also be
enabled in order for the actually used function to be usable. Prairie
Falcon doesn't have and PCI device 3 on bus 0, so remove D3F0 from the
common mainboard devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I01f9b9ac2a9ebd5899a093d97eb5b2d76d309f66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68315
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13 23:57:53 +00:00
Felix Held 6e94623a24 mb/amd/padmelon/devicetree: fix PCIe port device numbers
Enable the correct PCIe root ports in the devicetree so that the
configuration matches the PCIe port descriptors in
src/mainboard/amd/padmelon/bootblock/OemCustomize.c.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idb00a65adcf2059d7432a8df08654bb0ba965e24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68314
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13 23:57:31 +00:00
Felix Held f2812dfe53 mb/amd/gardenia,padmelon/devicetree: explicitly enable IOMMU device
PCI devices that aren't present in the devicetree will be treated as
enabled. Since the chipset devicetree that will be added in a follow-up
patch disables this device by default, explicitly enable the IOMMU
device on the Stoneyridge mainboards that don't disable it to keep the
same behavior.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4a2cdd00abe8309244829dc633dd8a9ca0038dfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68313
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13 23:57:14 +00:00
Felix Held 30b3660956 mb/amd/padmelon: use override devicetrees for the different APUs
Since the devicetree files are passed to util/sconfig without being
processed by the C preprocessor, using #if in the devicetree won't give
the behavior that might be expected. Instead sconfig treats the #if as a
comment, but still processes all other lines. To get the intended
behavior, replace the C preprocessor usage in the devicetree by moving
the APU-specific parts to override devicetrees that get selected
according to the selected APU type.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iddd317b27a838849fa40c0fb77d942609104cf04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68312
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13 23:56:57 +00:00
Sean Rhodes 39f2aa0904 mb/starlabs/starbook/tgl: Remove PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is no longer needed so remove it.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I82841c2114ceb5e7a46ce228fce63d24822098d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68084
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13 21:16:40 +00:00
Arthur Heymans 796a8f3dd3 soc/amd/*: Hook up GPU ops in devicetree
This removes the need for a PCI driver.

Change-Id: I4b499013a80f5c1bd6ac265a5ae8e635598d9e6c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13 19:43:53 +00:00
Arthur Heymans b171f76812 soc/amd/*: Hook up GPP bridges ops to devicetree
This removes the need for a PCI driver.

Change-Id: I8e235d25622d0bd3f1bb3f18ec0400a02f674a6d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13 19:43:10 +00:00
Arthur Heymans 987ec8837a soc/amd/acp: Hook up ops in devicetree
This removes the need for a PCI driver.

Change-Id: Id25016703d1716930d9b6c6d1dab5481b10aca17
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13 19:42:36 +00:00
Felix Held 6e1fb6ae9f soc/amd/morgana: Use devicetree ops over pci driver
Morgana is a SoC so it makes sense to statically use ops instead of
matching them to PCI DID/VID at runtime.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67362ae4a32bc9b1dd19ee5e4caf42db8f5dd1bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68311
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13 19:41:46 +00:00
Arthur Heymans 6a5d770536 soc/amd/mendocino: Use devicetree ops over pci driver
Mendocino is a SoC so it makes sense to statically use ops instead of
matching them to PCI DID/VID at runtime.

Change-Id: I5619c8ad42cdeb019cb7294da884909df64a2211
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13 19:41:11 +00:00
Arthur Heymans b65f609bfd soc/amd/cezanne: Use devicetree ops over pci driver
Cezanne is a SoC so it makes sense to statically use ops instead of
matching them to PCI DID/VID at runtime.

Change-Id: If535221335217cee53bca956747e7f17f0a5fd8d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13 19:40:36 +00:00
Arthur Heymans 826955d365 soc/amd/picasso: Use devicetree ops over pci driver
Picasso is a SoC so it makes sense to statically use ops instead of
matching them to PCI DID/VID at runtime.

Change-Id: Ide747c9d386731af89b27630b200676c6e439910
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67743
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13 19:40:28 +00:00
Arthur Heymans 7f3807728b soc/amd/*: Hook up device_operations in chipset.cb
This removes the need for a lot of boilerplate code in the soc code to
hook up device_operations to devices.

Change-Id: I2afc1855407910f1faa9bdd4e9416dd46474658e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13 19:40:01 +00:00
Arthur Heymans bd15ece78a soc/amd/*: Move emmc disabling to device ops
This allows for reduced use of chip_operations in the followup patch and
allows the allocator to skip over the used mmio.

Change-Id: I4052438185e7861792733b96a1298201c73fc3ff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13 19:39:20 +00:00
Elyes Haouas d6b6b22616 payloads,src: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarity
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I80f3d2c90c58daa62651f6fd635c043b1ce38b84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-13 19:14:57 +00:00
Matt DeVillier 5f69b867f0 mb/google/skyrim: Allow variants to override romstage GPIO table
Switch from gpio_configure_pads() to gpio_configure_pads_with_override()
so variants can override romstage GPIO defaults. Rename baseboard
function and add an weak empty override function to be used by variants.
Will be used for touchscreen power sequencing in a follow-on commit.

Change-Id: I45586237919cd07a171beac57f3510e26338f67f
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-13 19:07:39 +00:00
Maulik Vaghela ffa79073d3 mb/google/herobrine: Create zombie variant
Create the zombie variant of the herobrine reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:249180463
BRANCH=None
TEST=util/abuild/abuild -p none -t google/herobrine -x -a
make sure the build includes GOOGLE_ZOMBIE

Signed-off-by: Maulik Vaghela <maulikvaghela@google.com>
Change-Id: Ifecf0a6323b20012defbf14bd16ce2f1f41f4714
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
2022-10-13 18:31:58 +00:00
Fred Reitberger 9049dfdb68 util/cbfstool: Wrap logging macros in do - while
Wrap the console logging macros with do { ... } while (0) so they act
more like functions.

Add missing semicolons to calls of these macros.

TEST=compile only

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I721a4a93636201fa2394ec62cbe4e743cd3ad9d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-13 17:07:02 +00:00
EricKY Cheng a261502de5 spd/lp5: Add new memory configuration of H58G66BK7BX067 and H58G56BK7BX068
Add Hynix H58G66BK7BX067 and H58G56BK7BX068 in the
memory_parts.json and re-generate the SPD.

BUG=b:243337816
BRANCH=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I8d6aac3ecec36b126e7e41d6c9475695aa7a26b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-10-13 17:06:20 +00:00
Fred Reitberger b9dd2561f8 soc/amd/*/psp_verstage/svc: Make svc.h macros common
The psp_verstage/svc.h SVC_CALLx macros are virtually
identical between picasso/cezanne/mendocino, so move
to common.

TEST=timeless builds are identical

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I86a8d9b043f68c01ee487f2cdbf7f61934b4a520
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-13 15:44:15 +00:00
John Su 73d7f3e837 mb/google/brya/var/felwinter: adjust I2C5 times for TP
This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C5.

BUG=b:249031186
BRANCH=brya
TEST=TP function is normal from EE check.

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I5e756b7d7e14cace24ef2dfbb323c840c867ae1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-10-13 14:51:25 +00:00
Jeremy Soller e14e66bc0c soc/amd/cezanne: enable LPC decodes if platform uses LPC
Change-Id: I2473fe61b299d1c6221844cd744791b8012c5c67
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-13 14:50:16 +00:00
Bill XIE fa963fd203 mb/hp/z220_series: Add missing PCI Interrupt Routing Table
HP Z220 series has PCI slot(s) but Interrupt Routing Table in ACPI
used to be missing, so one is added.

Note that the values within the added one are obtained from my own SFF
variant. If other variants have different values, please add them in a
manner similar to mb/gigabyte/ga-b75m-d3h/acpi/pci.asl.

Test result:
Log lines like

     pci 0000:00:1e.0: can't derive routing for PCI INT A
     ath9k 0000:04:00.0: PCI INT A: no GSI

disappeared from dmesg.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I8522b25ac46db2054302c8f2418927c722b157e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68334
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13 13:19:59 +00:00
Bill XIE fc2dc0b117 mb/hp/z220_series: Fix the indentation of dsdt.asl
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I66f99a5afbdd2b847a916a470a5def9a6d3999bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68335
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13 13:19:21 +00:00