Most people use USB keyboards.
Change-Id: Ia7cf513059565db7b86190c4aae62d7a35392408
Signed-off-by: Marcel Meißner <mm-meissner@gmx.de>
Reviewed-on: https://review.coreboot.org/7540
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
cat /sys/power/state should show supported sleep states as freeze and
mem where freeze is "Suspend to Idle" and mem is "Suspend to RAM"
Change-Id: Ia72aaf6642dcdc9106c1992af3cf6cb21a8fff4a
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/14285
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Do not disable warnings about unused but set variables to further
improve the code quality.
Change-Id: I25fa29ac42c9d09596d03f11fb01f31635a62a11
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/3981
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Changes in visible behaviour:
- The default make target doesn't run the tests anymore
- All generated files are stored under util/romcc/build/
(or $BUILD_DIR)
Change-Id: If003240742eb1902a6e9b337cdee299d7d66ee06
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14341
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Initial files to support Broadwell-DE SoC. This is FSP 1.0 based
project and is based on Broadwell-DE Gold release. Change has been
verified on Intel Camelback Mountain CRB.
Change-Id: I20ce8ee8dd1113a7a20a96910292697421f1ca57
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: https://review.coreboot.org/14014
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Add all currently clean directories.
Change-Id: Ibfb6432b485adb7fdc930f57ea0af4ff35921d37
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14332
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: Ia78cf5a4b283b846346e5e50c6b2b36299a6a892
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14363
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: Iea1a4b8f7df08d2ae694401211b0b664f5980b02
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14327
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14321
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The way this was implemented before was causing ACPI failures. There
was also a basic misunderstanding of what the AddressMax field was used
for. In this case, because it's a fixed address, it should be the same
as the AddressMin field.
Getting rid of the addition in the field solves the ACPI output problem.
Change-Id: Idec2bf0ed27ae694e98f141087cdf22401937178
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14343
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
The driver interface function derives the driver specific pointer from
the API provided handle, no need to use the handle in the local
functions.
BRANCH=none
BUG=none
TEST=SPI interface with the flash ROM is still working properly.
Change-Id: I7725b658365473c733698ca050e780d1dd5072d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a2b42779785623bd1234ab2dfb0b4db76c890fc7
Original-Change-Id: I9d657dc23540e9eac52d2dbfc551ed32b7fa98f0
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/338090
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14318
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
3288 and 3399 use the same pwm controller.
With this patch in place it is easy to add support for 3399.
BRANCH=none
BUG=none
TEST=booted veyron_jerry to kernel login prompt
Change-Id: If8f5697b4003d078b46de3fa3cebad6c8310a688
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: acf6132619167743c0c991b75f0f49c8d0e51ca7
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Change-Id: I79428f9ec71017ad8f3ad67dac1468178ccc3a1e
Original-Reviewed-on: https://chromium-review.googlesource.com/338019
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14336
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Both SOCs use the same base i2c controller, the difference mostly
being the number of interfaces and distribution of the interfaces'
registers between register files.
Upload check was complaining about misspelled labels, fixed them to
pacify the check.
With this patch in place it is easy to add support for 3399.
BUG=none
BRANCH=none
TEST=brought up veyron_mickey all the way to booting the kernel. It
properly recognized the TPM and the edid of the panel, proving
that i2c interface is operational.
Change-Id: I656640feabd0fc01d2c3b98bc5bd1e5f76f063f6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 82832dfd4948ce9a5034ea8ec0463ab82f0f5754
Original-Change-Id: I4829ea53e5f4cb055793d9a7c9957d6438138956
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/337971
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14335
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Most things still need to be filled in, but this will allow
us to build boards which use this SOC.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied Kevin board can be booted to
Linux login propmt.
Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840
Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/332385
Reviewed-on: https://review.coreboot.org/13915
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Trivial; Use tab over space for indent. Clean up some ASCII art
while here.
Change-Id: Id2478d140a98596c5eeefdf5b047c1ca23203909
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: https://review.coreboot.org/8016
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is based on t420s. Tested on a T420 without discrete GPU.
There is no support for nvidia gpu and optimus.
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: Iru Cai <mytbk920423@gmail.com>
Change-Id: Ie9405966e56180ac1c43a3c5b83181ee500177c8
Reviewed-on: https://review.coreboot.org/11765
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
We already have the ability to add a pxe rom to cbfs, but it needs to be
configured and built separately.
This moves the existing Kconfig options for PXE from device/Kconfig and
the top level Makefile.inc to payloads, and adds the option to download
and build iPXE as part of the coreboot build process.
This configures the serial output of iPXE to match coreboot's serial
port configuration by editing the .h files. iPXE doesn't give any
real build-time method of setting these configuration options.
Change-Id: I3d77b2c6845b7f5f644440f6910c3b4533a0d415
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14085
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Add some additional filters for files that do not require
license headers.
- Add an alternative wording for the BSD license that is used
in several files.
- Add string for dummy files
- Stop checking if there are no files left.
- Remove 'local' keyword which is not posix compliant.
Change-Id: I2ed1b0572b5fbe84ea86173b7ec2106454399547
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14324
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Differences:
- The test logic is now only implemented in one place (pending the
deletion of the old parts), whereas it previously was implemented
both as make rules and as a pair of shell scripts.
- Tests don't need to be registered anymore. Just adding a new file
with the correct name is enough to have it tested.
- The code is hopefully more readable and maintainable.
- The new test script supports colors (if the standard output is a
terminal and --nocolor was not passed on the command line).
Things to do in follow-up patches:
- Remove the old test code
- Test or remove fail_test*.c, hello_world*.c and raminit_test*.c
- Fix regressions that have built up over the years, while making sure
not to introduce new ones
- Makefile integration
- Jenkins integration
There are tests in the makefile that specify -fno-always-inline, but
this option doesn't exist anymore, so I didn't port them over.
Change-Id: Idd6b89368c1e36555cb880c37bbe07035c938cd7
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
This makes it easier to check the output against a reference output.
Change-Id: I9c7ae538b708399a5cadd18e498618d7480d240f
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14276
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Newer versions of Linux implement a sysctl variable called vm.mmap_min_addr
that controls the minimum address a virtual memory mapping may have[1]. It is
usually set to 64KiB.
Map the start of the segment specified in util/romcc/tests/ldscript.ld to
128KiB, just to be sure.
[1]: https://www.kernel.org/doc/Documentation/sysctl/vm.txt
Change-Id: I72a5c65ca5e7d3a77d6ec897ae3287e3ea05cc2f
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14277
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: Id6d11d1cea3ebde4adf63e3d98ac603d85591d5b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14331
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: I61938b42c5aa75d1c7706a1c5ae45dace6704c86
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14330
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: I9689bf4ccc5f639bd98d6277bdd27afe4bb4295b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14329
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: I7a19ed8cf16b9424190800940d2b8ec1a96c5ce9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14328
Reviewed-by: Myles Watson <mylesgw@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: I4572eec52bf834e4fac7bc5b54ceb591a0173a69
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14326
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: I5e5180ec4303a121609b4acffb284daea6b08379
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14325
Reviewed-by: Myles Watson <mylesgw@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: Ied67c5079a7f49594edb39caf61fe7f386c3f80d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14323
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: I260c1ae8d0f7306dd0c72c9ca05f0789cd915a61
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14322
Tested-by: build bot (Jenkins)
Reviewed-by: Damien Zammit <damien@zamaudio.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The following series always needs to access the functions
provided pci_rom.c.
Remove the dependency to CONFIG_VGA_ROM_RUN and depend on
CONFIG_PCI instead.
Change-Id: I6ed7ff5380edc7cd88dc1c71b43b1129a3de0f52
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14219
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Previously, on systems that are supposed to have ME but
are librebooted, there was no message printed to tell the user
that no MEI was detected. Fixed this bug.
Change-Id: I59681c194ae5e76533dd777374e26d1aea727337
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/14334
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
This updates FSP UPD headers that adds new fields. Importantly
there are new FSPS UPD fields that allow to specify some BARs.
They are needed by FSP SiliconInit API to work properly.
Change-Id: Ie268c57c66b4d8fd6e00835916004058ff05762e
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14217
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Certain security features on the platform use IMRs. Unfortunately
this memory is unusable for OS or firware. This patch marks IMR
regions as unusable.
Change-Id: I4803c41c699a9cb3349de2b7e0910a0a37cf8e59
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14245
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The ACPI base address was being programmed sepearately from
the other BARs in the PMC device. Group all the programming
together so there isn't separate paths for programming the
relevant BARs.
Change-Id: Ib17684397fc19c42b39d066f981c01a886d65235
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14320
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Restructure the nvm_is_write_protected routine to eliminate the dead
code error.
TEST=Build and run on Kunimitsu
Change-Id: Ia9170e27d4be3a34760555c48c1635c16f06e6a3
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14337
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
- Look at entire tree instead of just the current commit. This was
causing the test to overlook some issues that were already in the tree.
- If git is on the system, and the code is in a git repo, use the
'git ls-files' command to find the files to examine. If those
conditions aren't met, fall back to using the find command.
- Wrap the command so it's easier to read.
Change-Id: I3dce219a29ffb1ae56a31318b995e3ba8ea43e70
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14194
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Many of the tools and libraries don't use a target architecture, but
they were still getting put in one. This change separates out the
builds that need the target architecture from the ones that don't,
and sets the build directory accordingly.
This will help keep from rebuilding the libraries when building all
of the tools if you keep the temporary files around (-t option).
Change-Id: Id6c17719332f2244657f103f5f07ca7812d51af1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14229
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
ACPI aware OS will need _PRT table to get desired interrupt
resource assigned and make device driver working. The logical
device within SOC gets fixed interrupt line.
Change-Id: I75141bd62ca2594b74983dff54912e0b20458b9a
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/14243
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
A dedicated pci device driver required for LPC devices as the legacy
IO range need to be included to avoid IO resource confilict. Blindly
set to 0~0x1000 to also avoid the IO resource of COMA/COMB/LPT/FDD
and LPC.Without this driver system will have assertion on load
RTC DXE driver in UEFI payloads.
Change-Id: Icc462c159c2cf39cc1030d55acee79e73a6bfb35
Signed-off-by: Lance Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/13356
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
ACPI MADT tables required to describe the multiprocessor interrupt
routing. Apollolake SOC also have the interrupt override table like
other x86 silicons.
Change-Id: I85976e227963c950aad4476d68581b96e1090559
Signed-off-by: Lance Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/13373
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Two of the MCT data structures passed as substructures to ramstage were
not packed, and additionally no alignment was specified. On at least
SP5100-based platforms, specifying packed with no alignment caused boot
failure dependent on the exact compiled binary layout (LPC hang).
Specifying the alignment and packing the remaining structures appears to
have resolved the remaining LPC hang issues on the KGPE-D16. Note that
packing the remaining structures alone was not sufficient to eliminate
the hang, however removing the packed attribute entirely (during debugging)
did resolve the hang at the expense of potential problems in ramstage.
Change-Id: If3a7509ed438870d4d05caaaaa091e1c47bf9b97
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14303
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Marcel Meißner