Commit Graph

34622 Commits

Author SHA1 Message Date
Elyes HAOUAS 04e0712f46 Treewide: Add some gcc's warning options
Change-Id: I789c8906542c59477b0037d39e7aa4fb2dcf22c0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-03-11 14:36:24 +00:00
Wonkyu Kim 66815114cf mb/intel/tglrvp: sync up variant folders with latest up3
During intial UP4 patch, below UP3 patches merged which should be
applied for UP4.
https://review.coreboot.org/c/coreboot/+/39201
https://review.coreboot.org/c/coreboot/+/39229
Merge these patches to UP4

BUG=none
BRANCH=none
TEST=Build TGL UP4

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I7b24cb2b0d03309cf67c6c21ddc2031a054f6110
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
2020-03-11 14:33:16 +00:00
Michael Niewöhner 2bd2be545f soc/intel/common/block: tco: enable intruder SMI if selected
Set TCO to issue an SMI when the case instrusion switch gets pressed.

The SMI is controlled along with the general TCO SMI Kconfig.

Tested on X11SSM-F.

Change-Id: I3bc62c79ca3dc9e8896d9e2b9abdc14cfa46a9e7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-03-11 14:28:53 +00:00
Evgeny Zinoviev fc59f0860b Documentation: Fix a typo
filse -> files

Change-Id: Iaf0c3a064b42dde70b1e01cfc15ad3187bf8bfcc
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-03-11 14:28:34 +00:00
Elyes HAOUAS 9006df98c7 mb/biostar/am1ml: Remove old reference to olivehillplus
Change-Id: I219fb2c12bb865288364f6e48b1e3d64c14bc036
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-11 14:27:07 +00:00
Elyes HAOUAS e3a1386694 mb/asus/am1i-a: Remove old reference to olivehillplus
Change-Id: Idfb8c834ae63226546a4e2860d9b206ba0288718
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-11 14:27:02 +00:00
Elyes HAOUAS 149620fdfd mb/amd/olivehillplus: Drop unmaintained ROMCC board
Remove unmaintained and unsupported old ROMCC board.
This board wasn't hooked up for build.

Change-Id: Ie79637c992874bd06009ed9b3e9f470b44e749b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39064
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-11 14:26:38 +00:00
Elyes HAOUAS 3002eb42ed mb/amd/bettong: Drop unmaintained ROMCC board
Remove unmaintained and unsupported old ROMCC board.
This board wasn't hooked up for build.

Change-Id: I1bce09ba5041a6636f900de611846467653f35a9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-11 14:26:35 +00:00
Elyes HAOUAS f4cfefe788 mb/amd/db-ft3b-lc: Drop unmaintained ROMCC board
Remove unmaintained and unsupported old ROMCC board.
This board wasn't hooked up for build.

Change-Id: Ib4a95c650cc4d1cddc2ba530c12ce448a1943b34
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-11 14:26:12 +00:00
Elyes HAOUAS e13bc1c12c mb/amd/lamar: Drop unmaintained ROMCC board
Remove unmaintained and unsupported old ROMCC board.
This board wasn't hooked up for build.

Change-Id: Iaa812dc66ddc14c24263a68e73115502ba5e2417
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-11 14:26:06 +00:00
Elyes HAOUAS 8273e13a11 intel/i945: Call fixup_i945_errata() only for mobile version
Per Mobile Intel ® 945 Express Chipset Family - Specification Update
Document Number: 309220-013 (page 15), the power saving optimization
Erratum is for Mobile Intel ® 945 Express Chipset family.

So rename 'fixup_i945_errata()' to 'fixup_i945gm_errata()' and apply
that function only for I945GM.

Change-Id: I2656021b791061b4c22c0b252656a340de76ae5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-11 14:25:46 +00:00
Julius Werner 8355aa4de2 prog_loaders: Remove CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING
This option is not used on any platform and is not user-visible. It
seems that it has not been used by anyone for a long time (maybe ever).
Let's get rid of it to make future CBFS / program loader development
simpler.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2fa4d6d6f7c1d7a5ba552177b45e890b70008f36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-03-11 12:32:24 +00:00
Julius Werner 1645ecc8f6 cbfs: Remove unused functions
cbfs_boot_load_stage_by_name() and cbfs_prog_stage_section() are no
longer used. Remove them to make refactoring the rest of the CBFS API
easier.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ie44a9507c4a03499b06cdf82d9bf9c02a8292d5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-03-11 12:31:28 +00:00
Kangheui Won 5674bf15f9 mb/google/puff: Enable cros_ec_keyb device
This is required to transmit button information from EC to kernel.

BUG=b:150830342
BRANCH=None
TEST=firmware_ECPowerButton test passes on puff

Change-Id: I10ba9d55e8997ce2412deb0613cfcaa8f24f271d
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-03-11 06:29:31 +00:00
Bartek Pastudzki 69a88ddb5d util/scripts/ucode_h_to_bin.sh: Accept microcode in INC format
Intel supplies microcode (at least for MinnowBoard) in Intel Assembly
*.inc format rather than C header. This change allow to pass in
configuration directory with *.inc files rather than list of *.h
files.

Change-Id: I3c716e5ad42e55ab3a3a67de1e9bf10e58855540
Signed-off-by: Bartek Pastudzki <Bartek.Pastudzki@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:50:12 +00:00
Nico Huber 47ac6355b3 soc/intel/common: Add more GPIO definition macros
Make i/o-standby state and termination configurable for GPIs.

Change-Id: Id1a3c00aa8a857afa08e745b0b6a578b01fa6d47
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:47:10 +00:00
Stephen Douthit 56a74bca69 soc/intel/dnv: Set INT_LINE accouting for PIRQ routing & swizzling
This code also sets unused interrupt lines to the recommended safe
value of 0xff instead of ignoring such devices.

Change-Id: I7582b41eb3288c400a949e20402e9820f6b72434
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:45:53 +00:00
Stephen Douthit ecb0e409a4 soc/intel/dnv: Add ACPI _PRT methods for virtual root ports
This eliminates Linux kernel warnings that look like:
    pcieport 0000:00:17.0: can't derive routing for PCI INT B
    ixgbe 0000:07:00.1: PCI INT B: no GSI - using ISA IRQ 10

Change-Id: I2029e7a8252b9e48c1df457d8da5adce7d1ac21d
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:45:40 +00:00
Stephen Douthit a51f490870 soc/intel/dnv: Fix ACPI reporting of root port interrupt routing
pcie_port.asl defines an IRQM method that looks up legacy interrupt
swizzling based on incoming interrupt "pin" A-D and root port number.

Unfortunately the 8-bit root port number stored at offset 0x4F in the
config space matches the device number, not the 1-8 scheme used in
the LUT reported to the OS.

Fix the case values to match the hardware.

Change-Id: I103d632a4bc99461f02e05aa0f9a9eb7376770d9
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:45:34 +00:00
Praveen Hodagatta Pranesh aa6a8fb919 mb/intel/{saddlebrook,kunimitsu}: Add macro for SaGv config
Change-Id: Ia31da9997ba46c15cd385bf55e009cf299848b64
Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36423
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10 20:42:14 +00:00
Elyes HAOUAS b7731574f4 src: Remove unneeded 'include <arch/cache.h>'
Change-Id: I6374bc2d397800d574c7a0cc44079c09394a0673
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37984
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10 20:39:50 +00:00
Paul Menzel 2d65608733 winbond/w83667hg-a: Disable mouse controller also during resume
There is no reason to not disable the controller during resume. That
way, no ASL is needed.

Change-Id: I282a03647ee0958abb118fafe306abe5782db71c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/22286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:37:25 +00:00
Stephen Douthit 2c18ba5bd7 soc/intel/dnv: Don't clobber SATA_MAP while trying to set mode
SATA Mode Select is bit 16 of the SATA General Configuration
register.  This code currently incorrectly pokes at the Port Clock
Disable bits in the Port Mapping Register, and without clock the
affected ports can't link.

Change-Id: I37104f520a869bd45a32cfd271d0b893aec3c8ed
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
Reviewed-by: David Guckian
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:31:33 +00:00
Matt Delco 54e9894353 soc/intel: fix eist enabling
There was a bug like this for skylake that seems to have been copied to
other SoCs.

Signed-off-by: Matt Delco <delco@chromium.org>
Change-Id: Ib4651eda46a064dfb59797ac8e1cb8c38bb8e38c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-03-10 20:29:10 +00:00
Sebastian 'Swift Geek' Grzywna 49fb39b783 Documentation: Update codenames
austin-3 was a devel board, retracting
t60 comes in variants with discrete gpu and only intel gpu one

Change-Id: Ic1f7397b8676bdcc15f63d59d87518d35bba5b4d
Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:26:32 +00:00
Evgeny Zinoviev 79f7fcc927 util/nvramtool: fix building on OpenBSD
OpenBSD's gcc 4.2.1 doesn't know about _Noreturn

Change-Id: Ie9e1885c483941d3d0ce8c8948af53f1ef8bb5db
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:23:39 +00:00
Evgeny Zinoviev b863468533 util/board_status: Add support of CMOS values dump
Change-Id: I89f9a0e9622557b01dda52378f8f1323777bce39
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:20:27 +00:00
Nico Huber 549a33091a abuild: Always build the default config
Abuild allows us to add config files below `configs/` for each
mainboard. So far, these were built instead of the default config.
However, that allows to hide errors in the default config. Hence,
we should build that too in any case.

Change-Id: I94075dbaa6fabeb75bdbc92e56f237df80c15cef
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39382
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10 13:29:38 +00:00
Nico Huber 0266be0d2b soc/intel/xeon-sp,mb/ocp/tiogapass: Don't fake binaries
If we don't pretend to have binaries, there is no need to add fake ones.
This also fixes building the default config.

Change-Id: I8f933f24a734a9ce3d82ef57f7f234ee4dfa86e9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39383
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10 11:52:45 +00:00
Eric Lai 8fb7cd4123 lib/spd_bin: Correct LPDDR3 SPD information
Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on
JEDEC 21-C, LPDDR3 has the same definition with LPDDR4.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39366
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10 10:05:48 +00:00
Michał Żygowski b9f9f6c12b mb/libretrend/lt1000: Add Libretrend LT1000 mainboard
Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-10 10:04:05 +00:00
Michał Żygowski 48be6b276a mb/protectli/vault_kbl: Add FW6 support
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-10 10:03:17 +00:00
Srinidhi N Kaushik dcd3d072d4 mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation
This change uses drivers/intel/wifi chip for CNVi device and
adds dynamic SSDT entires for CNVi also export wake gpio for CNVi

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board and check for SSDT entries
for CNVi

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39315
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10 10:02:19 +00:00
Wonkyu Kim 2b4ded0be8 soc/intel/tigerlake: Enable Hybrid storage mode
To use Optane memory, we need to set 2x2 PCIe lane mode while we need
to set 1x4 PCIe lane mode for NVMe. The mode can be selected using
the FIT tool at build time.

By enabling hybrid storage mode in FSP, FSP will set 2x2 PCIe lane mode
if Optane memory is detected and the mode is not 2x2 and set 1x4 PCIe
lane mode if Optane memory is not detected and the mode is not 1x4
during boot up. The mode is saved in SPI NOR for next boot.

BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP from NVMe and Optane
Check PCIe lane configuration.

Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39232
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10 09:57:41 +00:00
Brandon Breitenstein 01ec713c26 mb/google/volteer: set TcssXhciEn to 1
BUG=144874778
TEST=Built with Volteer recipe and verified USB functionality

Change-Id: I6cbdbd8a4f65a0fe19e3fb8d7b60b8b849f104e7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-10 09:56:36 +00:00
Nico Huber f6f54dd3fa libpayload/corebootfb: Replace obsolete macros FI and CHARS
These macros serve no purpose anymore, let's do the substitution
manually once and for all. Also update the comment on the macros
and fix whitespace on the touched lines.

TEST=Checked that there are no changes in compiled code.

Change-Id: Ib60f9ab157e2e7d44b551dd4f695a6c25ebeb405
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-10 09:00:35 +00:00
Michał Żygowski cd0a5fcafc MAINTAINERS: Add 3mdeb as Protectli mainboards maintainers
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I03301441bb07e64aeb59e659ab1b22442b73ca1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39418
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10 06:46:49 +00:00
T Michael Turney 45473dd370 libpayload: Add uart/serial driver support for trogdor
Change-Id: I5be3904298cd88c60dbc6d8d662beeede2abe442
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35960
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09 22:58:56 +00:00
Elyes HAOUAS 0afd3f41d6 arch/arm: Use 'print("%s...", __func__)'
Change-Id: I83fb453344c31f2cfa97bdaf1b8791a7bef97fd7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-09 21:31:07 +00:00
Karthikeyan Ramasubramanian 4ebe6dff1a mb/google/dedede: Add PCIe Root Port Configuration
Add configuration for all the PCIe Root ports and Clock Source.
Configure the Root Ports as disabled and clock sources as not used.

BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0a1ad7e056907e454a93f51c84e1d99f08b7bdef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39166
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09 21:28:56 +00:00
Karthikeyan Ramasubramanian c83c5af3ae mb/google/dedede: Configure EDP_HPD GPIO
This enables display for use by payload.

TEST=Build and boot the mainboard. Ensure that the screens displayed by
payload are visible.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5fcd70623b15ae39954242605e75b2c5ce02ff14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-09 21:28:40 +00:00
Karthikeyan Ramasubramanian 2c208bddc9 mb/google/dedede: Configure EC <-> AP GPIOs
BUG=b:150869661
TEST=Build and boot the mainboard. Trigger apreset from EC console.
Trigger reboot from AP console.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0d6dd0b4264c11f7ee0ef436cc819b0bb92974f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39325
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09 21:28:23 +00:00
Karthikeyan Ramasubramanian 8499f7fb1b mb/google/dedede: Add GPIO list
Leave all the GPIOs in not connected state so that they can be
configured depending on the use-case. This is done to park the GPIOs in
a known safe state. This will also help to ensure that the required
GPIOs are configured when the concerned use-cases are enabled.

Below GPIOs are configured in Native Function 1 and are required for
boot-up.
* VCCIN_AUX_VID0
* VCCIN_AUX_VID1
* AP_SLP_S0_L
* PLT_RST_L
* CPU_C10_GATE_L
* GPDs

BUG=None
TEST=Build and boot the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5293536f66a6b08c9c2d2a6281684755a0c0b1b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39114
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09 21:28:08 +00:00
Alex Levin 3bc41cf7b4 mb/google/volteer: Enable FPMCU on volteer
BUG=b:147500717
TEST=none

Change-Id: I32fa27b399127dbf8608e0556c77431d2dad652d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-09 21:26:48 +00:00
Nick Vaccaro fa0bdd9ee0 mb/google/volteer: change two gpio settings
- declare the FPMCU interrupt to be level-triggered
 - change EC_PCH_WAKE_ODL gpio to native function mode
 - corrected spelling of a signal name in a comment

BUG=b:144933687, b:148179954
BRANCH=none
TEST=none

Change-Id: I62da900d0b71139e55b52d06ec09ca25106f73cd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-09 21:26:32 +00:00
Michał Żygowski 83565dea86 mb/protectli/vault: Add FW2B and FW4B Braswell based boards support
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I553fd3a89299314a855f055014ca7645100e12e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-09 21:26:20 +00:00
Angel Pons 9d422ef381 mb/asus/p5g41t-m_lx: Do not set BSEL GPIOs in devicetree
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are
set up in romstage, so it makes no sense to clobber the registers with
garbage in ramstage.

Tested, my Asus P5G41T-M LX still boots and it does not need a full
reset on almost every reboot.

Change-Id: I6ea498119df44243ec42e3cb5c2903de32a17373
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39384
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09 21:25:45 +00:00
Angel Pons d903fffbc9 mb/asus/p5g41t-m_lx: Correct GPIO direction
Not all GPIO4 pins on the SuperIO are configured as outputs.

Change-Id: Idf6350551a91c4c1a25a83e3fb9b1a6722a81c36
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-09 21:25:22 +00:00
Angel Pons acabbce229 mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetree
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are
set up in romstage, so it makes no sense to rewrite their values in
ramstage.

Tested, my Asus P5QPL-AM still boots.

Change-Id: Ic47f96d12420ebcc70ab5cea940c4c09620c03ca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-09 21:23:27 +00:00
Michał Żygowski 915d1eaeae soc/intel/braswell/chip.h: Include smbios.h for Type9 Entries
In order to add the smbios_slot_desc for the SMBIOS Type9 entries into
the devicetree, and not use numbers but strings like
"SlotTypePciExpressGen3X4", smbios.h needs to be included in the
static.c.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Id15fe4101d14479b02e536fdf63748a241c02bd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-09 11:03:41 +00:00