Simplifies our C interface function gma_gfxinit(), due to the following
changes:
* *libgfxinit* knows about the underlying PCI device now and can
probe MMIO addresses by itself.
* The framebuffer mapping is now completely handled inside the
library where we validate that we neither overflow
- the stolen memory,
- the GTT address space, the GTT itself nor
- the aperture window (i.e. resource2 of the PCI device)
that we use to access the framebuffer.
Other changes:
* Fixes and a quirk for DP training.
* Fix for DP-VGA adapters that report an analog display in EDID.
* Fixes for Skylake support with coreboot.
* DDI Buffer drive-strength configuration for Haswell, Broadwell and
Skylake.
* `gfx_test` can now be run from X windows (with glitches).
* Compatibility with GCC 7 and SPARK GPL 2017.
TEST=Booted lenovo/t420 and verified that everything works as usual.
Change-Id: I001ba973d864811503410579fd7ad55ab8612759
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Updating from commit id 3f3a496a 2017-09-01 09:20:19
(image_signing: Fix loem.ini pattern for unibuilds)
to commit id 753e34e9 2017-08-31 10:12:40
(futility: Make rwsig sign command produce EC_RW image)
This brings in 5 new commits.
This also updates Depthcharge stable commit ID.
Updating from a843f262 2016-08-16 08:41:04
(kahlee: select emmc boot first if available)
to commit id f3bb31fe 2017-08-15 17:15:33
(vboot: Support EC early firmware selection)
This brings in 14 new commits.
Change-Id: I17d034e87fa642c5e30e933eb98bcfe5ceaaa3a8
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Besides some internal changes that won't have much effect on coreboot,
the newer version also supports building host tools on systems that
self-designate as i686.
Change-Id: I823bad862805cdec1dfecc8ba046f73ac206d3e8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Updating from commit id 8b714252 - 2017-07-18 02:36:16
(crossystem: Remove defunct sw_wpsw_bootfield)
to commit id 8c4b8285 - 2017-08-14 20:37:45 -0700
(detachables: Skip "Enable Developer Mode" in DEV mode)
This brings in 6 new commits.
Change-Id: I7769035453796a162c6313cd0c87661ef1e64f89
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Updating from commit id 04b3835b:
2017-06-12 06:47:41 -0700 - (Add a script to generate a keypair for signing Rose RW firmware.)
to commit id 8b714252:
2017-07-18 02:36:16 -0700 - (crossystem: Remove defunct sw_wpsw_boot field)
This brings in 19 new commits.
Change-Id: Ib68068b1afc5a264623021325e19644e8b63f8f3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Updating from commit id 3944adca:
2017-03-18 12:16:27 +0000 - (Merge pull request #861 from soby-mathew/sm/aarch32_fixes)
to commit id b1187232:
2017-06-20 15:34:54 +0100 - (Merge pull request #992 from davidcunado-arm/dc/fix-signed-comparisons)
This brings in 373 new commits.
Change-Id: I653007f664921305d22645f7904bb2d8eb85fe67
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update from commit bcffec7fd - reef: Cleanup battery code
to commit 9fb10386a - Poppy: Configure camera PMIC to low power mode.
Brings in 794 new commits from Jan 2, 2017 to Jun 21, 2017
Change-Id: I864679360bd3b211b6883a662e20812b49aefbba
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update blobs pointer to bring in the AGESA.bin changes for
amd/00670F00/FP4 and amd/00670F00/FT4.
Change-Id: I739124090e41edaf76210cda6189b2c7545cdf58
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update from commit a1c5f7c0
vboot_reference: Add support for 3072-bit exponent 3 keys
to commit 04b3835b
Add a script to generate a keypair for signing Rose RW firmware
This brings in 34 new commits.
Change-Id: Ifa304af5c2cf0bcc466dfc4878dd9d08436eec75
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Update libgfxinit to the latest master. Changes:
* Remove trailing whitespace in debug output.
* Change some types to make it verify with SPARK Pro.
* Add Broxton (Apollo Lake) support for eDP/DP/HDMI.
* Add Linux user-space test tool `gfx_test`.
* Add a README describing libgfxinit and the build process.
TEST=Booted lenovo/t420 and verified that internal and
external displays are working.
Change-Id: I4d0e23b8a254234173461b831585eae58d3af58e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Update libhwbase to the current master. Some noteworthy changes:
* Add prerequisites for upcoming Apollo Lake support in libgfxinit.
* Add some support for Linux user-space for libgfxinit's `gfx_test`.
* Fix compilation with GCC 7.
Change-Id: If3c65065ef9a2ff6fce221939fda43c9e30c1eb8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Submodule 3rdparty/arm-trusted-firmware 236c27d21f..3944adca59
This brings in 241 new commits from the upstream arm-trusted-firmware
repository, merged to the upstream tree between December 30, 2016 and
March 18, 2017.
3944adca Merge pull request #861 from soby-mathew/sm/aarch32_fixes
..
e0f083a0 fiptool: Prepare ground for expanding the set of images at
runtime
Also setup ATF builds so that unused functions don't break the build.
They're harmless and they don't filter for these like we do.
Change-Id: Ibf5bede79126bcbb62243808a2624d9517015920
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Some renamings force us to update our code:
* Scan_Ports() moved into a new package Display_Probing.
* Ports Digital[123] are called HDMI[123] now (finally!).
* `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`.
Other noteworthy changes in libgfxinit:
* libgfxinit now knows about ports that share pins (e.g. HDMI1 and
DP1) and refuses to enable any of them if both are connected
(which is physically possible on certain ThinkPad docks).
* Major refactoring of the high-level GMA code.
Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/18770
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Add the binaryPI file for the FT4 package and add SMU firmware to
be consumed by fanless OPNs.
Change-Id: I1c9b5ded6b494fac1553cc2ec7756a7a47386ecf
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18988
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This brings in 70 new commits from the upstream vboot repository,
dated October 31, 2016 to March 2, 2017
Change-Id: Iac9c2b0389afbfa02c1cccc38d39a12dac4a5ac4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18953
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Updated to arm-trusted-firmware TOT:
236c27d2 (Merge pull request #805 from Xilinx/zynqmp/addr_space_size)
183 commits between Sep 20, 2016 and January 10, 2017
- Also add associated change to src/soc/rockship/rk3399 Makefile.inc
that is required to build the M0 Firmware.
Change-Id: I49695f3287a742cd1fb603b890d124f60788f88f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18024
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update to Chromium TOT with bcffec7f (reef: Cleanup battery code)
292 commits between Oct 28, 2016 and Jan 2, 2017
Change-Id: I6bc356b9e458bebaa5839375ff40dd7e0d6ccff1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18023
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Changes:
o Verification that the framebuffer matches the display mode
o Automatic upscaling if the framebuffer resolution is lower
than the display mode's
o VGA-plane support
o HDMI pixel rate is limited to hardware constraints
o Error tolerant handling of EDID header-pattern
Change-Id: Icbfdf5f37caf99f66847a71f784730aced0826ab
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17775
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update the blobs submodule to bring in the binaries for 00670F00.
This also corrects some formatting in the various license.txt files.
Change-Id: I7a70d1168734d06ef6919d83dd73bc8f2bc4173c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17872
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins)
Add `libgfxinit` as another option for native graphics initialization.
For that, the function gma_gfxinit() (see drivers/intel/gma/i915.h) has
to be called by the respective northbridge/soc code.
A mainboard port needs to select `CONFIG_MAINBOARD_HAS_LIBGFXINIT` and
implement the Ada package `GMA.Mainboard` with a single function `ports`
that returns a list of ports to be probed for displays.
v2: Update 3rdparty/libgfxinit to its latest master commit to make
things buildable within coreboot.
v3: Another update to 3rdparty/libgfxinit. Including support to select
the I2C port for VGA.
Change-Id: I4c7be3745f32853797d3f3689396dde07d4ca950
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16952
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
It's hidden behind a configuration option `CONFIG_RAMSTAGE_LIBHWBASE`.
This also adds some glue code to use the coreboot console for debug
output and our monotonic timer framework as timer backend.
v2: Also update 3rdparty/libhwbase to the latest master commit.
Change-Id: I8e8d50271b46aac1141f95ab55ad323ac0889a8d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16951
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
`libhwbase` is a SPARK library that contains some basic support for i/o
access, debugging, timers. Just what I put around `libgfxinit`, to make
it build standalone.
Change-Id: I1918680c14696215522e1c5dae072235bb4e71a3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16948
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This pulls in the bdb support for futility so that rotor can build.
Change-Id: Icfa432fb840bea3e1616933ed02cf34a681fa3ce
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17061
Tested-by: build bot (Jenkins)
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
We need to disable some regulators when the device goes into suspend.
This means that we need to pass some gpios to bl31, and disable these
gpios when bl31 runs the suspend function.
BRANCH=None
BUG=chrome-os-partner:56423
TEST=enter suspend, measure suspend gpio go to low
[pg: also update arm-trusted-firmware to match]
Change-Id: Ia0835e16f7e65de6dd24a892241f0af542ec5b4b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0f3332ef2136fd93f7faad579386ba5af003cf70
Original-Change-Id: I03d0407e0ef035823519a997534dcfea078a7ccd
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/374046
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16719
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The AGESA binary for PC Engines' APU2 board was just added to the blobs
directory. Update the submodule pointer to allow access.
Change-Id: Ic2995f253d12d17e229526cb71dea5bf65fa36f9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16253
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Half a year has passed. Fixes went in. Probably bugs, too.
However, nobody really supports our local vboot version anymore.
Change-Id: I5042f23686dfe98e540c482f744e9df2d7df3b19
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16055
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
It includes support for rk3399.
Change-Id: I326ef3dc3021313ee852395c302c076b3e3c8c5e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14732
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is used in coreboot-side vboot code now, to keep booting from
the same RW section after wakeup - necessary when romstage is in RW
and its use of the RAM init configuration cache may differ between
versions.
Change-Id: Ie531cf3ddc980154f48772b3ff87e23473010721
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/13844
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update ATF codebase to a version that supports passing a timestamp and
fix the format to what it accepts now (including quotes).
This provides reproducible builds.
Change-Id: I12a0a2ba1ee7921ad93a3a877ea50309136ab1ab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13726
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Move submodule forward to a newer upstream master to fix the build on
paths containing "@", as can happen on jenkins.
Change-Id: Ie74012725c379909d5bf631f9cc9969106ca52b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13673
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Note that this is a manually added commit id (to get the CrEC fixes in
that are necessary for building outside cros_sdk), so it will probably
fail.
Change-Id: Idc15cf268c663ae49b209b92b198c9a4d122c7e3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13546
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It provides a few extensions to the API that are required, such as
vb2api_check_hash_get_digest()
Change-Id: Ib4d8bdc29751f51f0f7532376175490a0ffd84b3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13590
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update the 3rdparty/blobs submodule to bring in the latest
CarrizoPI binaries.
Change-Id: I65769ebe7b2aa6508d0d6ab2df34a092751e1078
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12425
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update to commit 832bc6f1 (Remove microcode stored in C-array format),
which is the latest commit in the BLOBs repository.
Building the Lenovo X60 currently fails as the microcode file cannot be
found.
CREATE build/mainboard/lenovo/x60/cbfs-file.wkWhPK.out (from src/mainboard/lenovo/x60/cmos.default)
make: *** No rule to make target '3rdparty/blobs/cpu/intel/model_69x/microcode.bin', needed by 'build/cpu_microcode_blob.bin'. Schluss.
Change-Id: I40ebceec299f46c19fd60861d872adcd91df3610
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11865
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
b4ade40 via/nano: Move CPU microcode to 3rdparty/blobs
8921cc4 amd/model_fxx: Move CPU microcode to 3rdparty/blobs
1099605 amd/model_10xxx: Move CPU microcode to 3rdparty/blobs
5f5604e Convert microcode to binary
Change-Id: I276537281a01f8497ed87108e66574ec45265f3a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11129
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This can be a problem with freshly updated devices that are periodically
powered on while closed (as explained in the bug report).
In this case, just don't count down. In case of actual errors (where we
want the system to fall back to the old code), this now means that the
retries have to happen with the lid open.
Bump vboot's submodule revision for the vboot-side support of this.
BUG=chromium:446945
TEST=to test the OS update side, follow the test protocol in
https://code.google.com/p/chromium/issues/detail?id=446945#c43
With a servo, it can be sped up using the EC console interface to start
the closed system - no need to wait 60min and plugging in power to get
to that state.
Change-Id: I0e39aadc52195fe53ee4a29a828ed9a40d28f5e6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10851
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I080c0a5954d3e4b2d6debdf2a77f32df7329841c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10565
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
New marker includes:
3d5af98 microcode: Update Broadwell to MC0306D4_0000001F
349fd55 microcode: Update Baytrail to M0C30678_000082D
9077293 Add BLOBs to support AMD Embedded "Merlin Falcon" processor
Change-Id: I53f8f95079c6436ad316a11d432fcf92c03332b5
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10506
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Move the 3rdparty/blobs marker to include the following:
a710941 amd/pi: Move AGESA cbfs access function to coreboot
63f1db5 AMD avalon: add PSP firmwares
Change-Id: Ie12b273ab9d22ab440b477919e70419b21cb833b
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10202
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This allows providing a verified boot mechanism in the
default distribution, as well as reusing vboot code like
its crypto primitives for reasonably secure checksums over
CBFS files.
Change-Id: I729b249776b2bf7aa4b2f69bb18ec655b9b08d90
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10107
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There's now room for other repositories under 3rdparty.
Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10109
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
To move 3rdparty to 3rdparty/blobs (ie. below itself
from git's broken perspective), we need to work around
it - since some git implementations don't like the direct
approach.
Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10108
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Move the 3rdparty marker to blobs.git commit 892a697
Change-Id: I8a51f301e08e49970b4747f004e0752617de8005
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9625
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
This pulls in the Intel microcode from blobs, and allows us to move
forward with relocating microcode updates in blobs.
Change-Id: Iaa046cc20c7825aac168a6ed97c87be548634df3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8356
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
'blobs' now contains the update for the BaldEagle binaryPI.
Change-Id: I7ed423b17cee926205792223d6355277bedad552
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8232
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
'blobs' now contains the update for the Mullins binaryPI.
Change-Id: Ife5dc73a856697c23a6d6b27fd5280f972992631
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8230
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
Commit bb932c56 (nyan*: I2C: Implement bus clear when 'ARB_LOST' error
occurs) unintentionally reverted commit 16472743 (3dparty: Update to
latest commit in blobs repository).
Apply that commit again:
'blobs' now contains updates which allow binary AGESA to build with
Clang. Pull those in, in anticipation of re-enabling -Werror on Clang
builds.
Change-Id: I2530b6c58d369f1741b1a77bdfd7bcdb64ac9feb
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7963
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This is a fix for the 'Lost arb' we're seeing on Nyan* during
reboot stress testing. It occurs when we are slamming the
default PMIC registers with pmic_write_reg().
Currently, I've only captured this a few times, and the bus
clear seemed to work, as the PMIC writes continued (where
they'd hang the system before bus clear) for a couple of regs,
then it hangs hard, no messages, no 2nd lost arb, etc. So
I've added code to the PMIC write function that will reset the
SoC if any I2C error occurs. That seems to recover OK, i.e. on
the next reboot the PMIC writes all go thru, boot is OK, kernel
loads, etc.
BUG=chrome-os-partner:28323
BRANCH=nyan
TEST=Tested on nyan. Built for nyan and nyan_big.
Original-Change-Id: I1ac5e3023ae22c015105b7f0fb7849663b4aa982
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197732
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
(cherry picked from commit f445127e2d9e223a5ef9117008a7ac7631a7980c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I584d55b99d65f1e278961db6bdde1845cb01f3bc
Reviewed-on: http://review.coreboot.org/7897
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
'blobs' now contains updates which allow binary AGESA to build with clang.
Pull those in, in anticipation of re-enabling -Werror on clang builds.
Change-Id: I734de0b93ebc1e78781f1d5f48e280badc3cf8b3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7884
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Update to commit 9f68e20e (AMD KaveriPI: Add PI header files to support
binary AGESA release), which is the latest commit in the blobs
repository.
Change-Id: I3d643f7565700272c22b59ed764c3269801f4413
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7595
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Update the 3rdparty repo to the IPQ binary commit
This got updated in error by commit:39bbc8cb97e2de2423cc31bee014ef56884d9f3c
Original-Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f
Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Original-Reviewed-on: http://review.coreboot.org/7354
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
(cherry picked from commit cfa06c7460)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ibfa243d057f9a2d27e9e02e3e8d4fc6e1da61df0
Reviewed-on: http://review.coreboot.org/7437
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Only one setting actually works (exact value depends on board). So
no need to show it.
Change-Id: I2a85719264bbac07791ef6a9279590ba768c309e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7359
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Update the 3rdparty repo to the IPQ binary commit
Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7354
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The BLOBs repo has been updated with AMD PI header files, peripheral
BLOBs for the new Avalon southbridge, the AGESA binary PI BLOB for
Steppe Eagle, the Steppe Eagle video BIOS, and platform security
processor firmware.
Change-Id: I8bb58a5cc572d2d75de33b14843d7d1893fff532
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/6770
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
It includes a sandybridge fix.
Change-Id: I84ff1ac1622b10a4a4aa42517bac0c024c386998
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4642
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Ice28114e5f53f510d305cd85d095044e2f4bd7b2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3740
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
For new systemagent v6 binaries.
Change-Id: I550533fd19c7c5592f3e3c9b514efe2750619c8f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3567
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
For google/stout binaries
Apparently the actual marker got lost in the rebase / change of the
commit message.
Change-Id: I4f18b9ddba326988b58f2595c0025a113feb0d68
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2734
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change the OSC method to actually grant control of
PCIe capabilities to the OS instead of granting no
control. I believe the logic was backwards in the
original commit. Bits should be set when granting
control and cleared when not granting control. By
setting the return value to 0x00, we effectively
tell the OS that it cannot control any PCIe
capability. See section 6.2.9 of the ACPI spec
version 3.0 for more information.
This edit is a duplication of the OSC method that
is in the src/southbridge/intel/bd82x6x/pch.asl
file.
Change-Id: Id2462ab12203afceb9033f24d06b4dfbf2236d2e
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2714
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
For google/stout binaries
Change-Id: I4ef3f9cc35dfb6d27e1c9f074759f0e3ddee73c4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2635
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The build system will make sure only to fetch this if
desired by the user.
Change-Id: Ie3c1b44f67ba2595cae001234e29e36cf855a3e4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/956
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This binary is required for anyone who wishes to build a
sandybridge mainboard.
Change-Id: I779ef5e2b77166b81cb05eada37291368e74fbb6
Signed-off-by: Ron Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/897
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Nico Huber