Commit Graph

38520 Commits

Author SHA1 Message Date
Furquan Shaikh 2736c82956 drivers/wifi/generic: Move ACPI functions to a separate file
This change reorganizes the WiFi generic driver to move the ACPI
functions to a separate file. This change is done to reduce the noise
in generic.c file and improve readability of the file.

Change-Id: If5fafb5452fb5bad327be730fcfc43d8a5d3b8ec
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-11-02 06:13:10 +00:00
Furquan Shaikh 507a98b689 drivers/wifi/generic: Move SMBIOS functions to a separate file
This change reorganizes the WiFi generic driver to move the SMBIOS
functions to a separate file. This change is done to reduce the noise
in generic.c file and improve readability of the file.

Change-Id: I38ed46f5ae1594945d2078b00e8315d9234f36d7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-11-02 06:12:57 +00:00
Furquan Shaikh 2b5be8857b drivers/wifi/generic: Use acpigen_write_ADR_pci_device
This change uses the helper function `acpigen_write_ADR_pci_device()`
to write _ADR object for the WiFi device.

Change-Id: I3ba38f3ec4d8024209840e93bebf2d39bbef7685
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-11-02 06:12:42 +00:00
Martin Roth 89815c96a6 soc/amd/picasso: Put transfer buffer into common ld file
Instead of having the same linker layout for the transfer buffer between
the x86 & PSP linker layout scripts, put the common layout into a file
shared between the other linker scripts.

BUG=None
TEST=Boot zork board, verify the buffers are aligned.
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ib9d9d8b046bc9e9e7a4ee939324960bfc44c3508
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-11-02 06:12:11 +00:00
David Wu 0d76194a1b mb/google/volteer: Disable DPTF active policy for terrador and todor
Terrador and Todor are fanless design, so disable DPTF active policy.

BUG=b:171019363,b:170699797
BRANCH=volteer
TEST=build and verify by thermal team

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I53a33b8706d7a7d4013a2a5627a620223fcffc3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46874
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:11:21 +00:00
Iru Cai a568d605e9 ec/hp/kbc1126: Support using a different GPE
HP EliteBook Folio 9480m uses the HP KBC1126 EC ACPI interface, but
with a different GPE, so add a Kconfig option to support using a
different GPE.

Change-Id: I3b78567e1387c96bf173e4370aa3c836bbddac0b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45576
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:08:54 +00:00
Srinidhi N Kaushik b57f22fc5b vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425
Update FSP headers for Tiger Lake platform generated based on FSP
version 3425. Previous version was 3373.

BUG=b:172045149
BRANCH=none
TEST=build and boot delbin

Cq-Depend:chrome-internal:3373431
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I58d165d452c8c6ae2eec92524109a568f7e581a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47041
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 04:43:39 +00:00
Matt DeVillier 184c794086 docs/librem_mini: update CPU, known issues section
Both 8565U and 8665U CPUs are used in the Librem Mini.

SATA issue updated based on addition of HSIO PHY tuning params
and resulting changes.

Change-Id: I33a093ccfea077402e1b3651f9ca5d6d8a2818f8
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-31 21:46:06 +00:00
Patrick Georgi 8aa087ece6 .gitignore: Ignore .test/.dependencies globally
These were originally ignored only inside util/ but these files
shouldn't be tracked anywhere.

Change-Id: Ie0846bd8bdd6e52f420f9dd2e72a8a922102ff90
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-31 18:21:36 +00:00
Martin Roth 09e032e59f Makefile: Remove possibly illegal characters from doxyplatform
The CONFIG_MAINBOARD_PART_NUMBER string can have characters in it that
don't work in the doxyplatform make script under sh, so change any
non-alphanumeric characters to an underscore.

Also strip all the quotes - they aren't needed.

The spaces in the "QEMU x86 i440fx/piix4" platform are one example of
this.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I10bc6a8a245a34e89c859ff46835bde35aaa4286
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-10-31 18:21:06 +00:00
Felix Held 215ac3bc40 cpu/x86/lapic: rename virtual wire mode initialization function
Clarify what the function does by renaming it from do_lapic_init() to
lapic_virtual_wire_mode_init().

Change-Id: Ie4430bf0f6c6bf0081b6aaeace351092bcf7f4ac
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-31 18:01:38 +00:00
Angel Pons f5dd7b6eb9 {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix
Tested with BUILD_TIMELESS=1, Google Wolf does not change.

Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46720
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-31 10:08:59 +00:00
Angel Pons 8963f7d40b sb/intel/lynxpoint: Drop unnecessary `UL` suffix
With BUILD_TIMELESS=1, Asrock B85M Pro4 and Google Wolf do not change.

Change-Id: I9ba4097cd82c4ff68315a40e1e955e4ed9a43862
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46719
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-31 10:08:35 +00:00
Angel Pons 2d35cf8689 sb/intel/lynxpoint: Use common code to generate HPET table
There's no need to reinvent the wheel.

Change-Id: If6b90c9a7a00af0322c6dd15d2c4ecf2c513d0cc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46977
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-31 10:07:52 +00:00
Michael Niewöhner cbd4ee73d7 cpu/intel/common: correct MSR for the Nominal Performance in CPPC
The "Nominal Performance" is not the same as the "Guaranteed
Performance", but is defined as the performance a processor can deliver
continously under ideal environmental conditions.

According to edk2, this is the "Maximum Non-Turbo Ratio", which needs to
be read from MSR_PLATFORM_INFO instead of IA32_HWP_CAPABILITIES.

Correct the entry in the CPPC package.

Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled
version

Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46464
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-31 00:04:45 +00:00
Daniel Kang 1b940d17a8 mb/google/volteer: Remove RIPTO support for camera
GPIO D4 was used for camera reset for both front and rear cameras
(RCAM_RST_L/FCAM_RST_L) in RIPTO. For later volteer versions,
GPIO F15 is dedicated to the rear camera reset (RCAM_RST_L).

Before, BOARD_GOOGLE_VOLTEER flag was used for setting the right
RCAM_RST_L per volteer version. However, we don't support RIPTO
anymore. Also using flags for different volteer version support can
be error-prone. Removing RIPTO support.

BUG=b:171726823
BRANCH=none
TEST=Build and boot volteer proto2 or later version. Camera should
work without an issue.

Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: I961fc17092887b4807c12c95f7139bb7e7b33e91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46826
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 22:36:46 +00:00
Jacob Garber 1627e2f158 cpu/x86/sipi_vector.S: Use correct suffix for bts
The assembler is warning that the bts instruction is ambiguous, so use
the correct suffix btsl.  See also commit 693315160e
(cpu/x86/sipi_vector.S: Use correct op suffix)

Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I2eded0af1258e90926009544683b23961d99887b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-30 21:40:01 +00:00
Nico Huber 1fa72d5fe1 x86: Add a minimal example SoC along with a board
The min86 example SoC code along with the example mainboard
should serve as a minimal example how a buildable x86 SoC code
base can look like.

This can serve, for instance, as a basis to add new SoCs to
coreboot. Starting with a buildable commit should help with
the review of the actual code, and also avoid any regressions
when common coreboot code changes.

As the example code itself is build-tested, it should advance
with coreboot and can't rot like documentation might. It also
serves as a check what APIs need to be implemented with the
default Kconfig settings.

Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45710
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 21:34:18 +00:00
Daniel Kang 8661fe220d mb/google/volteer: Separate power resource for VCM
The camera privacy LED blinks during the boot and this gives a wrong
impression to the users that the camera is being used during the power
up. The blink happens when the camera module is probed and a series of
kernel patches and coreboot patches are being submitted to resolve the
issue.

The kernel patches are submitted to the chromium gerrit.

https://chromium-review.googlesource.com/2403386
https://chromium-review.googlesource.com/2403387
https://chromium-review.googlesource.com/2403385
https://chromium-review.googlesource.com/2403384
https://chromium-review.googlesource.com/2403383
https://chromium-review.googlesource.com/2403382
https://chromium-review.googlesource.com/2403381
https://chromium-review.googlesource.com/2403380

This is to separate the power resource for the VCM so that it can be
controlled by the driver and suppress the LED turn on.

BUG=b:169049942
BRANCH=none
TEST=Build and boot volteer board. Monitor camera privacy LED
and check if it blinks. It should not blink.

Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: Id51c98e42c5f20e231d8096c9d2d98deebc7c968
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tomasz Figa <tfiga@google.com>
2020-10-30 20:25:13 +00:00
Eric Lai b3e9aaf62b mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku
LTE module Fibocom L850-GL is lost after idle overnight,
with this workaround, host will not initiate U3 wakeup
at the same time with device, which will avoid the race condition.

If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR +
offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.

BUG=b:169645448
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3a04320b0e2441dce540a5afdc461f12de45c41b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
2020-10-30 20:20:47 +00:00
Marc Jones 70907b00e6 soc/intel/xeon_sp: Call common soc_get_num_cpus()
Use a common function to get the number of CPUs for each soc. This
removes a #if for different function names in the common code.

Change-Id: I3348d37fcae72247731e465ec2a65d9583a2f180
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-30 18:55:58 +00:00
Marc Jones 444fda4528 soc/intel/xeon_xp: Combine cpx and skx acpi.c
Prepare for common ACPI. Combine cpx and skx acpi.c into a single
file in xeon_sp. This is almost the last step in using common/block
acpi.

Change-Id: I5f40eb7909bb796907682c548219c7515f2ae4d1
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46600
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 18:55:42 +00:00
Marc Jones d49c8cfbf1 soc/intel/xeon_sp/skx/acpi.c: Update with cpx changes
Prepare for common ACPI. This primarily makes the skx madt table
generation match cpx. There are a few other small changes to remove
unused code and make the files match.

Change-Id: I71a59181226d79c40a4af405653c50c970fb720b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46599
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 18:54:10 +00:00
Jonathan Zhang cbbce66baf cpu/x86: increase timeout for CPUs to check in after 2nd SIPI
Increase timeout for CPUs to check in after 2nd SIPI completion
from 10ms to 100ms.

Update logging level for mp init failure cases from BIOS_DEBUG
to BIOS_ERR.

Without this patch, "mp initialization failure" happens on some
reboots on DeltaLake server. As consequence, not all 52 cpus
come up in Linux:
[root@localhost ~]# lscpu
...
CPU(s):                40

Also following Hardware Errors are seen:
[    4.365762] mce: [Hardware Error]: Machine check events logged
[    4.366565] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 9: ee2000000003110a
[    4.367561] mce: [Hardware Error]: TSC 0 ADDR fe9e0000 MISC 228aa040101086
[    4.368563] mce: [Hardware Error]: PROCESSOR 0:5065b TIME 948438164 SOCKET 0 APIC 0 microcode 700001d

With this patch, no such failure is observed with 370 reboots.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iab10f116dd4af152c24d5d8f999928c038a5b208
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46898
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 18:53:20 +00:00
Duncan Laurie 2e9315c4c6 soc/intel/tigerlake: Enable TCSS XHCI device and define port aliases
Enable the USB4 XHCI driver and remove the ACPI name entry from the
SOC level function.

Define aliases for the USB2/3 ports on north and south XHCI devices in
chipset.cb so they can be referenced in the mainboard devicetree.

BUG=b:151731851
TEST=define usb ports by reference in volteer devicetree and ensure
they get properties added in SSDT for both north and south XHCI device.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I724ca874d3a3f6a2b43a700b0b10f77f25c53ee0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-30 18:34:30 +00:00
Duncan Laurie 0f5a17e980 soc/intel/common/block/usb4: Add TCSS XHCI driver for SSDT generation
In order to generate ACPI entries for USB devices attached to the
USB4/TBT/TCSS/North XHCI device it needs to have a driver that will
enumerate static devices on the bus.  This driver does that and nothing
else.

BUG=b:151731851
TEST=boot on volteer and check for USB devices on \_SB.PCI0.TXHC.RHUB

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I5a2ff1cd1bed557e793d45119232cf87032ddd7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46851
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 18:34:19 +00:00
Marc Jones 53b465d1c1 soc/intel/xeon_sp: Move read_msr_ppin() to common util.c
Move CPX and SKX read_msr_ppin() to common util.c file.
Update drivers/ocp/smbios #include to match.

Change-Id: I4c4281d2d5ce679f5444a502fa88df04de9f2cd8
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-30 17:13:53 +00:00
Marc Jones 1f500845b4 soc/intel/xeon_sp: Move common chip.c code
Move common CPX and SKX chip.c code to chip_common.c.

Change-Id: I158882ab15659858c2b13b4a3e02a26ef8d4ed3c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-30 17:13:31 +00:00
Marc Jones 9a0d4f8620 soc/intel/xeon_sp/skx: Simplify pci_domain_read_resource
Use a simpler pci_domain_read_resource for the stacks. This
makes it the same as the cpx function, since both get the stack
information from the FSP.

This will be merged with common xeon cpx/skx in a later patch.

Change-Id: I0130ce671fe9ff04e48021a0c5841551210aa827
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46308
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 17:12:58 +00:00
Marc Jones 0262ffa85c soc/intel/xeon_sp/skx: Add resource allocator helpers
Add and use resource allocator helper functions from cpx. It also
simplifies the allocator by removing IORESOURCE_PCI64 from the resource
type check. It isn't needed since it is an attribute of IO and MEM and
will be added with the appropriate type.

This clean up matches CPX and will help with merging in the future.

Change-Id: I5812b07ba00eeafb4d1e826e9cdf9a659b0248bb
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46306
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 17:12:10 +00:00
Tim Wawrzynczak e1a7a26f5e lib/libpayload: Replace strapping_ids with new board configuration entry
There are currently 3 different strapping ID entries in the coreboot
table, which adds overhead. The new fw_config field is also desired in
the coreboot table, which is another kind of strapping id. Therefore,
this patch deprecates the 3 current strapping ID entries (board ID, RAM
code, and SKU ID), and adds a new entry ("board_config") which provides
board ID, RAM code, SKU ID, as well as FW_CONFIG together.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1ecec847ee77b72233587c1ad7f124e2027470bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-30 15:25:28 +00:00
Tim Wawrzynczak c70505acee fw_config: Make fw_config_get() public
Further patches will make use of this raw 64-bit value.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I161893c09da6a44265299f6ae3c3a81249a96084
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46604
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 15:25:06 +00:00
Tim Wawrzynczak 24b4af668b fw_config: Convert fw_config to a 64-bit field
We all knew this was coming, 32 bits is never enough. Doing this early
so that it doesn't affect too much code yet. Take care of every usage of
fw_config throughout the codebase so the conversion is all done at once.

BUG=b:169668368
TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG
and verify the console print contained that bit.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 15:24:52 +00:00
Tim Wawrzynczak eafe7989ac tigerlake mainboards: switch to devtree aliases for PMC MUX connectors
Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices
can be hooked up together via devicetree aliases.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib51764da5b3c029f9ac7ac60199a0aedfc7f29b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45878
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 15:23:58 +00:00
Tim Wawrzynczak e7881ed447 soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers
Now that device aliases can be used in the devicetree, the hacky function
'soc_get_pmc_mux_device' can be removed and replaced with pointers to the
devices the function was supposed to return (1 for each port).

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45747
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 15:23:34 +00:00
Angel Pons dd0066a919 cpu/intel/Makefile.inc: Use correct Kconfig symbols
Guard CPU code using CPU Kconfig symbols instead of northbridge symbols.

Change-Id: I0e5d7fc2e042381b96d2fbdfa34a3d4bf58201f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46943
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 15:12:03 +00:00
Johnny Li 8269692517 mb/google/volteer/variants/volteer2: I2C5 trackpad bus freq 400 kHz
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec.
This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring
the bus frequency closer to 400kHz.

BUG=b:153588771
TEST=Verified that I2C5 frequency is between 389-396kHz.

Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: If0803a74ba9071acf15486ce4038261c1681a92f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-30 15:04:04 +00:00
Arthur Heymans 69c0b19ae1 {soc/amd,sb/amd/hudson}: Fix generating the ACPI mcfg
The last argument for acpi_fill_mcfg() is the last PCI bus, which is
an uint8_t, not the total number of busses, which overflows the
argument if CONFIG_MMCONF_BUS_NUMBER is 256.

Change-Id: I8887e14128dbe54688eb6e803d6694b7c29956c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-10-30 13:50:00 +00:00
Martin Roth fdcbae0a9b vc/amd/fsp: Update bl_errorcodes_public.h
Replace the initial bl_errorcodes_public.h (a temporary, minimal
version) with the full version released by AMD.

BUG=None
TEST=Build
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I82585c74d74139a96419b9bffe1df3b8c344eb5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-30 13:04:01 +00:00
Marshall Dawson 902518e983 soc/amd/picasso: Fix the PSP SMI trigger info
Align coreboot's PSP MboxBiosCmdSmmInfo setup to how AGESA's PSP
library was implemented.  The trigger address must be an SMI trigger
register.  Assign one of the reserved triggers to the PSP.

The #define of SMITYPE_PSP 33 is still correct and is intentionally
unmodified.

This patch should be innocuous as the system doesn't currently support
SMI-based features of the PSP.  The call only exists so the PSP will
honor a mailbox command during S3 suspend.

BUG=b:171815390
TEST=Run SST on Morphius
BRANCH=Zork

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I74029271a522a4f23e54fd76f99a8e3eb0dd4d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46854
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 13:03:23 +00:00
Zheng Bao c5e28abaf8 amdfwtool: Take a config file instead of command line parameters
To verify the consistency, see if timeless builds with and without
this patch result in identical coreboot.rom files.

BUG=b:154032833
TEST=Build & boot on mandolin

Change-Id: Icae73d0730106aab687486e555ba947796e5e757
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-30 12:10:04 +00:00
Julius Werner 1cd013bec5 cbfs: Hook up to new CBFS implementation
This patch hooks coreboot up to the new commonlib/bsd CBFS
implementation. This is intended as the "minimum viable patch" that
makes the new implementation useable with the smallest amount of changes
-- that is why some of this may look a bit roundabout (returning the
whole metadata for a file but then just using that to fill out the rdevs
of the existing struct cbfsf). Future changes will migrate the higher
level CBFS APIs one-by-one to use the new implementation directly
(rather than translated into the results of the old one), at which point
this will become more efficient.

Change-Id: I4d112d1239475920de2d872dac179c245275038d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38422
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 11:14:11 +00:00
Julius Werner 0655f78041 commonlib/bsd: Add new CBFS core implementation
This patch adds a new CBFS implementation that is intended to replace
the existing commonlib/cbfs.c. The new implementation is designed to
meet a bunch of current and future goals that in aggregate make it
easier to start from scratch than to adapt the exisiting implementation:

1. Be BSD-licensed so it can evetually be shared with libpayload.
2. Allow generating/verifying a metadata hash for future CBFS per-file
   verification (see [1][2]).
3. Be very careful about reading (not mmaping) all data only once, to be
   suitable for eventual TOCTOU-safe verification.
4. Make it possible to efficiently implement all current and future
   firmware use cases (both with and without verification).

The main primitive is the cbfs_walk() function which will traverse a
CBFS and call a callback for every file. cbfs_lookup() uses this to
implement the most common use case of finding a file so that it can be
read. A host application using this code (e.g. coreboot, libpayload,
cbfstool) will need to provide a <cbfs_glue.h> header to provide the
glue to access the respective CBFS storage backend implementation.

This patch merely adds the code, the next patch will integrate it into
coreboot.

[1]: https://www.youtube.com/watch?v=Hs_EhewBgtM
[2]: https://osfc.io/uploads/talk/paper/47/The_future_of_firmware_verification_in_coreboot.pdf
(Note: In early discussions the metadata hash was called "master hash".)

Change-Id: Ica64c1751fa37686814c0247460c399261d5814c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38421
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 11:13:35 +00:00
Patrick Georgi 0a9eea0f5b util/docker: Add sdcc to our build nodes
core-ec will need it.

Change-Id: Id7d677a6f92ce266f893372a2540d77abb613707
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-10-30 09:28:41 +00:00
Patrick Georgi 6065f616eb .gitignore: Split into subdirectory files
There's no need for the global list of files to ignore, so use git's
ability to work with more local configuration.

Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 07:05:27 +00:00
Anil Kumar 33b0f15434 drivers/soundwire/alc711: Add Realtek ALC711 soundwire device
Bug=None
Test=Enabled the device on TGLY RVP and tested that the codec is
     reflected in SSDT. Checked sound card binding works
     and soundwire drivers are enabled in kernel.

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ia7358927fe8531e609ebe070bef259a2bbc09093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-10-30 04:08:17 +00:00
Angel Pons c3a6d4b2c7 soc/intel/broadwell: Drop reg-script to finalize PCH
Tested on out-of-tree Acer Aspire E5-573, still boots.

Change-Id: I3b9ae75842e3ec1ecd02323d104a9f1d45564172
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46710
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 00:47:07 +00:00
Angel Pons 071754c9dc soc/intel/broadwell: Relocate PCH finalisation code
Change-Id: I94a4194e935fddb99645ed2929bdd70583c2fd5b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46709
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 00:46:44 +00:00
Angel Pons 9eaca7dcf4 soc/intel/broadwell: Get rid of `cpu_is_ult`
It is only used in a single file, on two functions that already check
whether coreboot is running on a Haswell or a Broadwell processor.

Change-Id: I86e1061f722e6d6855190c2fd863d85fc24a1ee0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46708
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 00:46:29 +00:00
Angel Pons 37164ff609 soc/intel/broadwell: Inline CPUID helpers
These functions are small and used in various stages. Inline them.

Change-Id: I0d15012f264dbb0ae2eff8210f79176b350b6e7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46707
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 00:46:04 +00:00