Commit Graph

25720 Commits

Author SHA1 Message Date
Furquan Shaikh 39130a4f1e drivers/intel/wifi: Add PCI ID for Intel TP2 Wi-Fi
This change adds PCI ID for Intel TP2 Wi-Fi and adds that to
pci_device_ids in Intel wifi driver.

Change-Id: I51abf615fca6001d564e7cd672cc16f3a0fb8dd6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-01 12:47:40 +00:00
Furquan Shaikh 1f3135427b mb/google/rambi: Set SMI mask using google_chromeec_events_init
This change updates rambi ec init to perform SMI mask setting using
google_chromeec_events_init.

Change-Id: I7def3c07b4d7bfbe15b2d1c45381bdc31b7e3476
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-01 12:47:25 +00:00
Furquan Shaikh 1a5b7c6540 ec/google/chromeec: Initialize SMI mask in google_chromeec_events_init
This change adds smi_events to google_chromeec_event_info and allows
mainboards to set SMI mask if current boot type is not S3 wakeup.

Change-Id: I899a6af6e57d295b4eac2039c8245ebcc73a42bb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-01 12:47:17 +00:00
Patrick Rudolph 9bd6015843 superio/nuvoton/npcd378: Add PSU fan control
Implement method to access the SuperIO's harware monitor (HWM) IO space.
Set the PSU fan using a new CMOS option psu_fan_lvl. Add the CMOS option
to all board that use NPCD378. In case no CMOS is set use the default
fan level 3.

The HWM space can be written to at any time, but the SuperIO has to be
notified that a write is ongoing. After clearing the write-lock bit all
changes are applied at once.

Tested on HP Compaq 8200 SFF.

Change-Id: I56ce7ad1df88638589a577b8a09d5d775557887b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26050
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-01 11:57:25 +00:00
Emil Lundmark 2ad7ea07b8 mb/google/fizz: Add USB port info
This adds all USB ports to the device tree. Additionally, it adds _PS0
and _PS3 ACPI methods for the visible USB A ports, which makes it
possible to control the port power (VBUS) of each port individually.

Change-Id: I80ba090f323fbf9fc2b333b1c647b7dfb3393ff6
Signed-off-by: Emil Lundmark <lndmrk@chromium.org>
Reviewed-on: https://review.coreboot.org/26472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-06-01 08:16:00 +00:00
Marc Jones 9022b9d2aa soc/amd/stoneyridge: Add ACPI device name lookup
Add the ACPI devices defined in ASL to the soc_acpi_name() lookup
function.

BUG=b:80280671
TEST=Add ACPI method to specific GPP bridge. Boot and verify method
with ACPI dump.

Change-Id: I5117e0d39db831364173c9c61ccdab6e34f18c59
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/26698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-06-01 02:52:19 +00:00
Patrick Georgi f743728e9f util/lint: Add check that changes conform to clang-format style
It's a white list (configured through $(top)/.clang-format-scope) with
the expectation that the list will grow over time.
Once everything is covered, we can turn off the white-listing and keep
everything enforced.

To not drive people crazy, only check the files their commit touched.

Change-Id: I52c7ea73fd36aaa46c0bfce928158e1cd6304540
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-05-31 15:33:59 +00:00
Patrick Rudolph ae2cb2d3bf libpayload-x86: Export keyboard modifiers
Add function to get active keyboard modifiers.

Change-Id: Ifc7bd4aa86f20d67c5b542d0458b966e605c5499
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18601
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31 15:31:47 +00:00
Patrick Rudolph 1f5ebf7c8b libpayload: Export usbhid_getmodifiers
Add a new method to retrieve active usb keyboard modifiers.

Change-Id: Ief6679ce782b58b9ced207f4f27504fb2a517b76
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18602
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31 15:28:24 +00:00
Matt DeVillier 9aaf59aa6d soc/intel/broadwell: decouple PEI memory struct from coreboot header
Recent changes to field lengths in include/memory_info.h resulted in
a mismatch between the memory_info struct the MRC blob writes to and
the struct used by coreboot to parse out data for the SMBIOS tables.
This mismatch caused type 17 SMBIOS tables to be filled incorrectly.

The solution used here is to define the memory_info struct as expected
by MRC in the pei_data header, and manually copy the data field by field
into the coreboot memory_info struct, observing the more restrictive
lengths for the two structs.

Test: build/boot google/lulu, verify SMBIOS type 17 tables correctly
populated.

Change-Id: I932b7b41ae1e3fd364d056a8c91f7ed5d25dbafc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/26598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-31 15:28:12 +00:00
Elyes HAOUAS a89b9cd493 arch/x86/include/arch: Remove space after __attribute__
Change-Id: I7c74eff97580fbf39242f16dbdde98286678d596
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26321
Reviewed-by: Christoph Pomaska <cp_public@posteo.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31 15:28:00 +00:00
Werner Zeh 7731932937 i210: Add additional PCI-ID to the i210 driver
When the i210 MACPHY is operated in the SERDES Backplane mode (which
depends on the programmed firmware image), its PCI-ID will be 0x1537.
This does however not change the programming interface for the MAC
address.
Therefore add this new PCI-ID to the driver so that the MAC address can
be programmed in this operation mode as well.

Change-Id: I608535202c49e40690381c2b2ab26322d62cfb37
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/26683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-31 15:27:43 +00:00
Martin Roth ecb4491899 mainboard/google/kahlee: Add careena variant
Add Careena variant, based on the grunt board.

BUG=b:80106042
TEST=Build Careena

Change-Id: I87a24f6d8115aacf5b21181f3820cf2718ad252a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-31 15:25:12 +00:00
Vincent Palatin 405eb44fdb mb/google/poppy/variants/nocturne: configure the FPMCU interface
The FPMCU is using the standard cros-ec-spi interface on GSPI1.
Configure the GPIOs controlling the MCU too.

We need to be able to wake from S3 on the MCU interrupt, re-configure
GPE0 DW0 to point to GPP_C bank.

BRANCH=poppy
BUG=b:79666174
TEST=exercise the cros_ec interface, e.g. 'ectool --name=cros_fp version',
verify the MKBP events by doing 'ectool --name=cros_fp fpmode fingerup'
then 'ectool --name=cros_fp waitevent 5 10000', toggle the other GPIOs
with the flash_fp_mcu script.

Change-Id: Ib417dcf84cda8e354060785cd16a7b6b812148d5
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/26684
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31 15:25:00 +00:00
Nico Huber 9593e973fa soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE)
Boards could choose a high ROM_SIZE that would result in an MTRR config
that conflicts with other resources. Thus, always use the filtered
CACHE_ROM_SIZE.

Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31 15:11:21 +00:00
Nico Huber 654cc2fe10 {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate
Change-Id: Ibc2392cd2a00fde3e15dda4d44c8b6874d7ac8a3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-31 15:10:21 +00:00
Nico Huber 6197b76988 cpu/x86/mtrr: Prepare for ROM_SIZE > 16MiB
Most, if not all, chipsets have MMIO between 0xfe000000 and 0xff000000.
So don't try to cache more than 16MiB of the ROM. It's also common that
at most 16MiB are memory mapped.

Change-Id: I5dfa2744190a34c56c86e108a8c50dca9d428268
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26567
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31 15:09:30 +00:00
Nico Huber b4953a93aa cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE
As far as I can see this Kconfig option was used wrong ever since it
was added. According to the commit message of 107f72e (Re-declare
CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary
to prevent overlapping with CAR.

Let's handle the potential overlap in C macros instead and get rid
of that option. Currently, it was only used by most FSP1.0 boards,
and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?).

Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-31 15:08:48 +00:00
Subrata Banik c51df93ccf soc/intel/skylake: Select common P2SB code
This patch select CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB to include
common p2sb code block.

BUG=b:78109109
BRANCH=none
TEST=Build and boot EVE.

Change-Id: I3f6aa6398e409a05a35766fb7aeb3aa221dd3970
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26165
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31 04:27:28 +00:00
Kyösti Mälkki cea7e8bdef Remove VIA vt8237r southbridge support
Change-Id: I2d0400212d32c4dee71163d2f5919c290b8c0616
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31 03:47:24 +00:00
Kyösti Mälkki ef3f94a5db Remove VIA C7 CPU support
Change-Id: Ib8c943e01ac293bdbf37f43ff72dbb636b46a8af
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31 03:47:04 +00:00
Kyösti Mälkki 5ceaf7bf5f Remove VIA C3 CPU support
Change-Id: Ib33c05cec60238f17b68e3e729c1a9e125bfb179
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31 03:46:22 +00:00
Kyösti Mälkki f99fa1058d Remove VIA VX800 northbridge support
Change-Id: Id6026e9d7ff064d54b0dd93e80dabdcc4efd2b8e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31 03:45:19 +00:00
Kyösti Mälkki e99f0390b9 Remove VIA CX700 northbridge support
Change-Id: Id46e3d40393598f6b03ae4fd3186182635f072ca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31 03:44:42 +00:00
Kyösti Mälkki ec953bc2f9 Remove VIA CN700 northbridge support
Change-Id: I6c33d35718cc445ce67fc625d71420ded3828d8b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31 03:44:20 +00:00
Kyösti Mälkki 7182ccef24 mb/via/epia-m700: Remove board
Platforms with LATE_CBMEM_INIT were agreed to be
removed with 4.7 release late 2017.

Change-Id: I34f9bffcced5ccdd8691994b78fffed057021d0e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31 03:43:58 +00:00
Kyösti Mälkki 6dcedfaaef mb/via/vt8454c: Remove board
Platforms with LATE_CBMEM_INIT were agreed to be
removed with 4.7 release late 2017.

Change-Id: Ic135c3f8eb18818d0ae3b63f53b542905815bbd0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31 03:43:26 +00:00
Kyösti Mälkki 82d7609ea9 Remove all VIA CN700 boards
Platforms with LATE_CBMEM_INIT were agreed to be
removed with 4.7 release late 2017.

Change-Id: I06840476ad187cbb6e6af554b5c8e8c4d66f6624
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31 03:42:57 +00:00
Kyösti Mälkki d840eb5719 Remove AMD K8 cpu and northbridge support
Change-Id: I9c53dfa93bf906334f5c80e4525a1c27153656a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-31 03:42:11 +00:00
Kyösti Mälkki 4979ffc5cb Remove southbridges after K8 board removals
Change-Id: Ib6935c026e2302b037fc82be64163f10bf775751
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-31 03:41:41 +00:00
Kyösti Mälkki 1740230ace Remove all AMD K8 boards
Platforms with LATE_CBMEM_INIT were agreed to be
removed with 4.7 release late 2017.

Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-31 03:41:11 +00:00
Kyösti Mälkki f054a4bf3d mb/msi/ms9652_fam10: Fix dependency on amdk8/util.asl
Change-Id: I0bb515fbf7b1ae9b0dd1b61bad0c45a7f38d6767
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-31 03:40:41 +00:00
Kyösti Mälkki 8251fa0eb0 AGESA binaryPI: Remove dependency on K8 headers
The included .c file also pulled in ancient files
amdk8/pre_f.h and amdk8/raminit.h

Do a dirty copy-paste to work around that.

Change-Id: Ie89a5f91d5234f1ef334d30a43dd56e0b722b5ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-31 03:40:16 +00:00
Martin Roth f8307c3bb4 util/docker: Fix file ownership when building with coreboot-sdk
Instead of requiring the user to enter their root password to set the
created files to their user, create a new user inside the docker
container with the correct UID & GID and build with that.

Change-Id: Ibbeff00211e8cf653f48204d285e06bca39b5fd2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-30 17:15:25 +00:00
Patrick Georgi 5486786495 checkpatch: exclude util/crossgcc/patches
These files are supposed to contain trailing whitespace due to the patch
format. Also use the exclusion list in the pre-commit hook.

Change-Id: I8816c05ea703964a332915a0675096836957b242
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26695
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-30 17:12:00 +00:00
Patrick Georgi 9110c17668 util/gitconfig: improve robustness of checkpatch in pre-commit
Users can have non-default configurations as to how git diff et al are
presenting file names in diffs (default: a/ and b/ prefixes). checkpatch
expects that and trims the first element, so enforce that configuration
for the diff that's sent into it.

Change-Id: I099795119456a73c900b31ce191c2d9e898a5c7e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-30 17:11:51 +00:00
Martin Roth f6081c2deb mainboard/google/kahlee: move grunt's chromeos.fmd to baseboard
The chrmoeos.fmd file will be common across variants, so move it out of
of grunt directory and into the variants/baseboard directory.

BUG=b:80106042
TEST=Build grunt

Change-Id: I259d85f60c5e19e00f7d9149542bcfdcc6dfaf4f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-30 14:29:27 +00:00
Martin Roth ddb2a77511 mainboard/google/kahlee: move SPDs to variants/baseboard/spd
The SPD files will be common to many of the mainboards, so move them out
of grunt and into the variants/baseboard directory.

BUG=b:80106042
TEST=Build grunt, make sure spd.bin is the same.

Change-Id: I53975a46a8c7d7e519bb6f7ef6ccd0b817ac4c92
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-30 14:29:19 +00:00
Philipp Deppenwiese 438b463a8f Documentation: Update index.md and move files
* Add more subdirectories and index.mds.
* Move "getting started" and "lessons" into sub-directories.
* Move "NativeRaminit" into northbridge/intel/sandybridge folder.
* Move "MultiProcessorInit" into soc/intel/icelake folder.
* Reference new files

Change-Id: I78c3ec0e8bcc342686277ae141a88d0486680978
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26262
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-30 09:14:48 +00:00
Aamir Bohra e462585c94 soc/intel/cannonlake: Enable IDT and expection handling support for all stages
Change-Id:I4146a040e5e43bed7ccc6cb0a7dc2271f1e7a8ea
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/26661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-30 04:18:00 +00:00
Hannah Williams b81362a82e libpayload-x86: i8042: fix i8042_data_ready_ps2 and i8042_data_ready_aux
keyboard_disconnect was called without keyboard_init being called and in this
case keyboard_havechar returns true because i8042_data_ready_ps2 is
dereferencing uninitialized variable ps2_fifo from within fifo_is_empty causing
keyboard_disconnect to be stuck in this while loop.
while (keyboard_havechar())
    keyboard_getchar();

BUG=b:80299098
TEST=Check if the normal mode path in depthcharge is not causing a hang

Change-Id: I944b4836005c887a2715717dff2df1b5a220818e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/26590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-30 01:10:44 +00:00
Martin Roth 5474eb15ef src/northbridge: Add and update license headers
This change adds and updates headers in all of the northbridge files
that had missing or unrecognized headers.  After this goes in, we can
turn on lint checking for headers in all northbridge directories.

Change-Id: I8cd7c04ddb8e58946dcdf9c7c125e23698647a73
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-29 22:36:37 +00:00
Martin Roth ebace9f250 src/southbridge: Add and update license headers
This change adds and updates headers in all of the southbridge files
that had missing or unrecognized headers.  After this goes in, we can
turn on lint checking for headers in all southbridge directories.

Change-Id: I09614730bfd4db923dda103bd07bab02836a4c92
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-29 22:36:25 +00:00
Martin Roth c515898b33 src/soc: Add and update license headers
This change adds and updates headers in all of the soc files that
had missing or unrecognized headers.  After this goes in, we can
turn on lint checking for headers in all soc directories.

Change-Id: I8b34dcd10c692f1048bd8d6c0fe3bfce13d54967
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-29 22:36:10 +00:00
Martin Roth 6b1ceacb9b chromeec platforms: Update ACPI throttle handler call
Currently the throttle event handler method THRT is defined as an extern,
then defined again in the platform with thermal event handling.  In newer
versions of IASL, this generates an error, as the method is defined in
two places.  Simply removing the extern causes the call to it to fail on
platforms where it isn't actually defined, so add a preprocessor define
where it's implemented, and only call the method on those platforms.

Change-Id: I6337c52edaf9350843848b31c5d87bbfca403930
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-29 22:35:07 +00:00
Martin Roth 60e084b7d3 mainboard/hp/dl145_g1: Remove empty WAK ACPI method
Change-Id: I16cdf2781ce1bf9458300de70a87a3bb98d01636
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-29 22:34:50 +00:00
Martin Roth a34b5bc6ed southbridge/intel/bd82x6x: Remove unused argument from ACPI method
The method POSC was only using 2 of the 3 arguments passed in to it.
Remove the unused argument.

Change-Id: I6bbc2a034c79581fd338276eea56aac6d1affa58
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-29 22:34:33 +00:00
Nicola Corna 14604dad4e sb/intel/{bd82x6x,ibexpeak}: Fix out of bounds access in intel_me_status()
On Ibex Peak (and maybe also on other platforms), when the AltMeDisable
bit is set (-S or -s option of me_cleaner), the ME PCI device disappears
from the bus and its configuration space is all ones.

This causes a freeze in intel_me_status(), as coreboot tries to access
an out of bounds array element.

Change-Id: I957abebe1db15ec2c9a2b439f0103106bfa56b33
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/26601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-29 07:31:09 +00:00
Kyösti Mälkki b433d26ef1 arch/x86: Define HPET_ADDRESS_OVERRIDE
Symbol defined in via/cx700 but also used elsewhere.

Change-Id: I31d6043e71dea474de00f609b9609a628ecc6eb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-28 16:10:28 +00:00
David Hendricks da8e2ca32e fsp_broadwell_de: Select TSC_MONOTONIC_TIMER by default
This is currently selected by each derivative board's Kconfig even
though it's really an SoC-specific option.

Change-Id: Iad135261915a0857c53c18aaebde7e46c97a8f40
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/26344
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-28 16:10:15 +00:00