size_t is an unsigned type and as such is a bad choice for a counting
down loop counter.
BRANCH=all
BUG=none
TEST=editing cli command line does not cause hangs any more
Change-Id: I0502553b5e2143052345edeb205a01558fccd9b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1c171f739497fcd26589976676ab94b23cd7ee8b
Original-Change-Id: I4aa38379ac356114fc91a32cced2fa45a00a09d6
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/262714
Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Tested-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9891
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The WG (write gate) bit in C0_EBase allows the upper two bits of
the exception base address to be set to something other than 2'b10,
thus allowing it to be relocated out of the traditional KSEG{0,1}
range. Since we're not using the segmentation features introduced
by EVA to relocate the unmapped segments, the exception vectors
should remain in KSEG0. Don't set the WG bit so that the upper
two bits of the exception base (2'b00, because of the identity
mapping) are ignored and we execute the exception vectors out of
KSEG0.
BUG=chrome-os-partner:36258
BRANCH=none
TEST=Build and boot on Pistachio.
Change-Id: Ie8b4eb6e41a328e7055736c9e3f6ff5ec83b9e13
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d5b002f5ae71c7729e467d4fe3fd8db187e15dea
Original-Change-Id: Id8b930db1e7a68f52dd61be4dfa9edaee2bebf7d
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/246697
Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9822
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add helper macros to convert between physical addresses and KSEG{0,1}
addresses. Also get rid of the virt_to_{bus,phys}_offset variables
as these are fixed values.
As nobody seems to be using getpagesize() on MIPS, no need to keep
virtual.c.
BUG=chrome-os-partner:36258
BRANCH=none
TEST=Build and boot on Pistachio.
Change-Id: Ia26c8eae53eb8f860747a6b321363776841d1a94
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c422b02e9a2a20d130913b1cfb835ad74c39ddca
Original-Change-Id: I9476cd225a08534830c700cba7bf9d3ef871757e
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/247190
Reviewed-on: http://review.coreboot.org/9821
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Use bus_to_virt() to convert the physical address of the DMA
coherent region to an address in KSEG1 which is suitable for
device memory accesses.
BUG=chrome-os-partner:36258
BRANCH=none
TEST=Build and boot on Pistachio.
Change-Id: If382feda66f6d829f8b3548ab263cf603cab2e9b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a88a175f6d6db81d3154fb5dd31a44363ab94653
Original-Change-Id: I9ad6435495df2c71d8f81a782f1c3dfcfd4aeb28
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/246696
Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9818
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA and bring up board; works as
expected
BRANCH=none
Change-Id: I368494f388b82969dda0ce73a38824791efce616
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e4c2bbcbdbcf706062724cffe2d5f15953468ace
Original-Change-Id: Id5c9b1d65c6ec87f2aba06995dc940c50afb041f
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/245386
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8746
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add CPU frequency corresponding to SOC.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; behaves as expected.
BRANCH=none
Change-Id: I05458070a15c6cf1ef0fc2104715a63902a38887
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4afe332bcc41afeb7e31e918e345c3336f7dc604
Original-Change-Id: I55b788faf7984bafc2509cac69867a772c7cb863
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/241427
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8853
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The default string functions work with multiple of 4 bytes
(sizeof(unsinged long)); MIPS will use LW/SW instructions
for these operations and if the source and destination
addresses are not aligned it will trigger an exception.
Therefore, this implementation does all data access operations
per byte, because there is no guarantee that the provided
strings are properly aligned.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; behaves as expected
BRANCH=none
Change-Id: I05b43673deb954f022d12cb9c3d7baac26be2a34
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e13b3d31726404abd8c8e5c8780d3d3e16e032d
Original-Change-Id: I456e312eb6b7fee2eff10e461af7f578aed07648
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/241885
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8743
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add the basic build infrastructure and architectural support
required to build for targets using the MIPS architecture.
This will require the addition of cache maintenance.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA with Depthcharge as payload;
successfully executed payload.
BRANCH=none
Change-Id: I75cfd0536860b6d84b53a567940fe6668d9b2cbb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 758c8cb9a6846e6ca32be409ec5f7a888ac9c888
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Change-Id: I0b9af983bf5032335a519ce2510a0b3aca082edf
Original-Reviewed-on: https://chromium-review.googlesource.com/219740
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8741
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Vadim Bendebury