Commit Graph

38661 Commits

Author SHA1 Message Date
Eric Lai bca5bdb056 mb/google/brya: Enable ACPI and add ACPI table
Enable ACPI configuration and add DSDT ACPI table.

BUG=b:174266035
TEST=Build Test

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I08513ec159b69535f742a1fd70cdec9ec845d414
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04 21:09:07 +00:00
yuanliding e1d7d8464c Coachz: change EN_PP3300_DX_EDP from gpio52 to gpio67
Coachz rev1 has changed EN_PP3300_DX_EDP from gpio52 to gpio67.

BRANCH=none
BUG=b:174123578
TEST=emerge-strongbad coreboot chromeos-bootimage.
flash coreboot and boot up normally.

Signed-off-by: yuanliding <yuanliding@huaqin.corp-partner.google.com>

Change-Id: I32a721d0d725bf217debe35a5cdc01aa8f5d5daf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2020-12-04 20:53:57 +00:00
Arthur Heymans 9ddd9002cc cpu/x86/smm_module_loaderv2: Fix compiling for x86_64
Change-Id: I9288ede88f822ff78dd9cb91020451dc935203a0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-04 17:20:30 +00:00
Felix Held 161d809bc6 soc/amd: move smi_util to common block
The functionality in smi_util applies for all 3 AMD SoCs in tree. This
patch additionally drops the HAVE_SMI_HANDLER guards in the common
block's Makefile.inc, since all 3 SoCs unconditionally select
HAVE_SMI_HANDLER in their Kconfig and smi_util doesn't use any
functionality that is only present when that option is selected.

Change-Id: I2f930287840bf7aa958f19786c7f1146c683c93e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-04 13:42:29 +00:00
Paul Menzel 1f03f1ed1f mb/amd/mandolin: Unify devicetree formatting for 00:14 devices
To accommodate also `off`, two spaces are used after `on` to align
comments.

This unifies the devicetree files of the two variants.

Change-Id: I7908fe2313ddccb6a4448a6338d6cd4938264f62
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-04 13:41:40 +00:00
Paul Menzel 0d53e75d85 mb/amd/mandolin: mandolin: Fix typo in *Coprocessor* in comment
This reduces the difference with Cereme’s devicetree file.

Change-Id: I1e6ba5891245562d5132307eab224623031e11c8
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-04 13:41:02 +00:00
Felix Held 5b2405a308 mb/amd/mandolin: use more readable size formats in FMAP files
Since the FMD file isn't parsed any more by a shell script in the SoC's
Makefile.inc, we can use better human-readable numbers for the section
sizes.

TEST=Timeless build results in identical image.

Change-Id: I2117064a694f67767284f6fd4ac3604b254a2734
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-04 13:39:34 +00:00
Felix Held a4819cd0b3 mb/amd/mandolin: removed unused MANDOLIN_MICROCHIP_FW_OFFSET
TEST=Timeless build results in identical image.

Change-Id: Ifa5c14add555b382f74ba1165131b1569bbef123
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-04 13:38:58 +00:00
Arthur Heymans a75a2fa1d6 mb/emulation/x86: Add optional parallel_mp init support
This makes it possible to select both the legacy LAPIC AP init or the
newer parallel MP init.

Tested on i440fx with -smp 32.

Change-Id: I007b052ccd3c34648cd172344d55768232acfd88
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-04 11:12:13 +00:00
Arthur Heymans 5e31a1939b cpu/qemu-x86: Increase MAX_CPUS to have actual AP init
CONFIG_MAX_CPUS=4 is the maximum supported with SMM_ASEG.

TESTED: on q35 and i440fx -smp 4/32.

Change-Id: I696856870e34e7a7ad580bc83c6b38f1dfb4511d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-04 11:11:45 +00:00
Arthur Heymans 91d5a6cc47 cpu/x86/lapic/secondary.S: Adapt for x86_64
Adapt the old lapic init code for x86_64.

Change-Id: I5128ed574323025e927137870fb10b23d06bc01d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-04 11:11:26 +00:00
Arthur Heymans d79e48570c cpu/qemu-x86: Add the option to have no SMM
Qemu i440fx does not support an smihandler at the moment.

Change-Id: I5526b19b8294042a49e5bca61036e47db01fd28a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-04 11:11:17 +00:00
Arthur Heymans d0e9538f88 drivers/intel/fsp2_0: FSP-T requires NO_CBFS_MCACHE
When FSP-T is used, the first thing done in postcar is to call FSP-M
to tear down CAR. This is done before cbmem is initialized, which
means CBFS_MCACHE is not accessible, which results in FSP-M not being
found, failing the boot.

TESTED: ocp/deltalake boots again.

Change-Id: Icb41b802c636d42b0ebeb3e3850551813accda91
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48282
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 11:00:45 +00:00
V Sowmya 407488edaa src/soc/intel/alderlake: Enable the PCH HDA
This patch enables the PCH HDA device based on the devicetree
configuration.

Change-Id: I1791b769f4ab41cf89d82cf59049a2980c6c1eb0
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48272
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 07:05:43 +00:00
Felix Held fef413e4be MAINTAINERS: add maintainers for soc/amd/cezanne and soc/amd/common
Change-Id: Ib661fdf27d5cdb6c2b989c7f2acfc8a6e061657c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48239
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 02:04:17 +00:00
Michael Niewöhner 9b57022ab4 mb/supermicro/x11ssm-f: correct trigger for SMI/NMI interrupt inputs
All four SMI/NMI interrupt inputs have an external pull-up resistor and
get triggered by pulling the line low. Thus, correct the trigger to
active-low.

Also document the signals by adding appropriate comments.

The pads' connections have been determined by dissecting a dead board.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Id1a8c1e0b9fe723a15d04a88d565a53eeba9b085
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48093
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 00:11:17 +00:00
Michael Niewöhner d328934c9b mb/supermicro/x11ssm-f: drop NMI overrides
Drop the NMI overrides, since NMI now gets configured in gpio common
code. Also remove the variant init mechanism, which is unused now.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I02e0c679f9aafe33108320a8dfc62dcb278202ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48092
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 00:10:52 +00:00
Michael Niewöhner 51f5ff6d27 soc/intel/{skl,cnl}: add NMI_{EN,STS} registers
Add NMI_EN and NMI_STS registers, so they can be configured for using
NMI gpios.

References:
- CMP-LP: Intel doc# 615146-1.2
- CMP-H:  Intel doc# 620855-002
- SPT-H:  Intel doc# 332691-003
- SPT-LP: Intel doc# 334659-005
- CNP-H:  Intel doc# 337868-002

Test: trigger NMI via gpio on Supermicro X11SSM-F did not work before
but now makes the Linux kernel complain about a NMI.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I4d57ae89423bdaacf84f0bb0282bbb1c9df94598
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48091
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 00:10:38 +00:00
Michael Niewöhner 14512f9a9b soc/intel/common/block/gpio: add code for NMI enabling
Especially server boards, like the Supermicro X11SSM-F, often have a NMI
button and NMI functionality that can be triggered via IPMI. The purpose
of this is to cause the OS to create a system crashdump from a hang
system or for debugging.

Add code for enabling NMI interrupts on GPIOs configured with
PAD_CFG_GPI_NMI. The enabling mechanism is the same as SMI, so the SMI
function was copied and adapted. The `pad_community` struct gained two
variables for the registers.

Also register the NMI for LINT1 in the MADT in accordance to ACPI spec.

Test: Linux detects the NMI correctly in dmesg:
[    0.053734] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1])

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I4fc1a35c99c6a28b20e08a80b97bb4b8624935c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48090
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 00:10:24 +00:00
Michael Niewöhner c3ab442cc1 intel/common/block/gpio: only reset configured SMI instead of all
Currently, when a SMI GPIO gets configured, the whole status register is
get written back and thus, all SMIs get reset.

Do it right and reset only the correspondig status bit of the GPIO to be
configured.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Iecf789d3009011381835959cb1c166f703f1c0cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48089
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 00:09:59 +00:00
Martin Roth 6a62cc85e6 mb/google/zork: Set S0IX_SLP_L high in S0, low in S3
This is used as a signal to show the system state.  It hadn't been used
up to this point as we're not currently using S0i3, but the fingerprint
sensor will use it to go into a low power mode, so set it appropriately
on Trembyle.  Dalboz devices don't use the FPMCU, but set there as well
so that the state matches.

BUG=b:174695987
TEST=Verify GPIO state in S0 and S3 with the EC
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibc725905909830d44f77c2498a26edf6d7a3dc05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48255
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Vincent Palatin <vpalatin@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 23:44:28 +00:00
Nico Huber 361a5c0952 spi/flashconsole: Fix internal buffer overflow
Once the console's FMAP region is full, we stop clearing the line
buffer and `line_offset` is not reset anymore. Hence, sanity check
`line_offset` everytime before writing to the buffer.

The issue resulted in boot hangs and potentially a brick if the
log was very verbose.

Change-Id: I36e9037d7baf8c1ed8b2d0c120bfffa58c089c95
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48074
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 23:26:43 +00:00
Ao Zhong 20426858c5 mb/hp/z220_sff_workstation/Kconfig: Select MAINBOARD_USES_IFD_GBE_REGION
Select MAINBOARD_USES_IFD_GBE_REGION to make CONFIG_HAVE_GBE_BIN
(Add gigabit ethernet configuration) selection available. Without that
onboard Ethernet won't work.

Signed-off-by: Ao Zhong <hacc1225@gmail.com>
Change-Id: I9fe138363fc47254285ebaa4a7dbe5b94a0a8784
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48007
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 23:20:43 +00:00
Felix Singer 424467c2a3 soc/intel/skylake: Add chipset devicetree
Set most of the devices to off to keep current behaviour.

Change-Id: Ic4dbd965c84c3679e42a181dea0e7e618c12fb97
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-03 21:55:42 +00:00
Julius Werner 20f5dcec63 cbfs: mcache: Fix end-of-cache check
After the mcache is copied into CBMEM, it has *just* the right size to
fit the final tag with no room to spare. That means the test to check if
we walked over the end must be `current + sizeof(tag) <= end`, not
`current + sizeof(tag) < end`.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I25a0d774fb3294bb4d15f31f432940bfccc84af0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-03 21:21:11 +00:00
Julius Werner fdabf3fcd7 cbfs: Add verification for RO CBFS metadata hash
This patch adds the first stage of the new CONFIG_CBFS_VERIFICATION
feature. It's not useful to end-users in this stage so it cannot be
selected in menuconfig (and should not be used other than for
development) yet. With this patch coreboot can verify the metadata hash
of the RO CBFS when it starts booting, but it does not verify individual
files yet. Likewise, verifying RW CBFSes with vboot is not yet
supported.

Verification is bootstrapped from a "metadata hash anchor" structure
that is embedded in the bootblock code and marked by a unique magic
number.  This anchor contains both the CBFS metadata hash and a separate
hash for the FMAP which is required to find the primary CBFS. Both are
verified on first use in the bootblock (and halt the system on failure).

The CONFIG_TOCTOU_SAFETY option is also added for illustrative purposes
to show some paths that need to be different when full protection
against TOCTOU (time-of-check vs. time-of-use) attacks is desired. For
normal verification it is sufficient to check the FMAP and the CBFS
metadata hash only once in the bootblock -- for TOCTOU verification we
do the same, but we need to be extra careful that we do not re-read the
FMAP or any CBFS metadata in later stages. This is mostly achieved by
depending on the CBFS metadata cache and FMAP cache features, but we
allow for one edge case in case the RW CBFS metadata cache overflows
(which may happen during an RW update and could otherwise no longer be
fixed because mcache size is defined by RO code). This code is added to
demonstrate design intent but won't really matter until RW CBFS
verification can be supported.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I8930434de55eb938b042fdada9aa90218c0b5a34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-12-03 00:11:08 +00:00
Julius Werner 0ba16637d8 x86: Put bootblock startup code into .text._start section
The initial bootblock assembly code on x86 is just put into the .text
section, which just happens to come before all the individual .text.*
function sections in the program.ld script. So it tends to be at the
start of the image, but if you inserted another linker script section
with contents before .text, it would cause a problem. (I'm not sure if
it's an architectural requirement for _start16bit to come at the start
of the image, but at least its 4K alignment requirement would waste a
lot of space if it didn't.)

This patch moves the section to .text._start which is the name other
architectures use for the code they want in the very front of the image
and which is listed first in program.ld.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia84e6e33ec29584d356e226e8fdcb8c9334d49af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46834
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 00:10:34 +00:00
Julius Werner c4ee28c61d cbfstool: Hide hash printing behind -v and add to parseable output
With the upcoming introduction of CBFS verification, a lot more CBFS
files will have hashes. The current cbfstool default of always printing
hash attributes when they exist will make cbfstool print very messy.
Therefore, hide hash attribute output unless the user passed -v.

It would also be useful to be able to get file attributes like hashes in
machine parseable output. Unfortunately, our machine parseable format
(-k) doesn't really seem designed to be extensible. To avoid breaking
older parsers, this patch adds new attribute output behind -v (which
hopefully no current users pass since it doesn't change anything for -k
at the moment). With this patch cbfstool print -k -v may print an
arbitrary amount of extra tokens behind the predefined ones on a file
line. Tokens always begin with an identifying string (e.g. 'hash'),
followed by extra fields that should be separated by colons. Multiple
tokens are separated by the normal separator character (tab).

cbfstool print -k -v may also print additional information that applies
to the whole CBFS on separate lines. These lines will always begin with
a '[' (which hopefully nobody would use as a CBFS filename character
although we technically have no restrictions at the moment).

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I9e16cda393fa0bc1d8734d4b699e30e2ae99a36d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-12-03 00:08:03 +00:00
Julius Werner 7066a1e7b3 cbfstool: Rename cbfs_walk() to cbfs_legacy_walk()
This function name clashes with cbfs_walk() in the new commonlib CBFS
stack, so rename it to cbfs_legacy_walk(). While we could replace it
with the new commonlib implementation, it still has support for certain
features in the deprecated pre-FMAP CBFSes (such as non-standard header
alignment), which are needed to handle old files but probably not
something we'd want to burden the commonlib implementation with. So
until we decide to deprecate support for those files from cbfstool as
well, it seems easier to just keep the existing implementation here.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I37c7e7aa9a206372817d8d0b8f66d72bafb4f346
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-12-03 00:07:05 +00:00
Elyes HAOUAS 48a6c018bc src: Remove redundant use of ACPI offset(0)
IASL version 20180927 and greater, detects Unnecessary/redundant uses of
the Offset() operator within a Field Unit list.
It then sends a remark "^ Unnecessary/redundant use of Offset"

example:
    OperationRegion (OPR1, SystemMemory, 0x100, 0x100)
    Field (OPR1)
    {
        Offset (0),     // Never needed
        FLD1, 32,
        Offset (4),     // Redundant, offset is already 4 (bytes)
        FLD2, 8,
        Offset (64),    // OK use of Offset.
        FLD3, 16,
    }

We will have those remarks:
dsdt.asl     14:         Offset (0),
Remark   2158 -                 ^ Unnecessary/redundant use of Offset operator

dsdt.asl     16:         Offset (4),
Remark   2158 -                 ^ Unnecessary/redundant use of Offset operator

Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 00:05:52 +00:00
Julius Werner d477565dbd cbfstool: Use cbfs_serialized.h and standard vboot helpers
This patch reduces some code duplication in cbfstool by switching it to
use the CBFS data structure definitions in commonlib rather than its own
private copy. In addition, replace a few custom helpers related to hash
algorithms with the official vboot APIs of the same purpose.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I22eae1bcd76d85fff17749617cfe4f1de55603f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-12-03 00:00:33 +00:00
Julius Werner 9d0cc2aea9 cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()
This patch introduces two new CBFS API functions which are equivalent to
cbfs_map() and cbfs_load(), respectively, with the difference that they
always operate on the read-only CBFS region ("COREBOOT" FMAP section).
Use it to replace some of the simple cases that needed to use
cbfs_locate_file_in_region().

Change-Id: I9c55b022b6502a333a9805ab0e4891dd7b97ef7f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39306
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 00:00:19 +00:00
Kyösti Mälkki 8c99c27df1 lib/trace: Remove TRACE support
Looks like the option is generally not compatible with
garbage collections.

Nothing gets inlined, for example is_smp_boot() no longer
evaluates to constant false and thus the symbols from
secondary.S would need to be present for the build to pass
even if we set SMP=n.

Also the addresses of relocatable ramstage are currently
not normalised on the logs, so util/genprof would be unable
dress those.

Change-Id: I0b6f310e15e6f4992cd054d288903fea8390e5cf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-02 23:35:58 +00:00
Eric Lai 5e053af7a6 mb/google/brya: Add GPIO stubs
Add stubbed out GPIO configuration and perform GPIO initialization
during bootblock and ramstage.

BUG=b:174266035
TEST=Build Test

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia658ab4b466242cf8658abb239f19a9c0a03849a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-02 23:00:36 +00:00
Eric Lai 50886827b5 mb/google/brya: Add entry stubs of each stage
Add entry point stubs of each stage for Brya. More functionalities will
be added later.

BUG=b:174266035
TEST=Build Test

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I44934c05ee32090b6e34648ee02f004c83e93d57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48063
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02 23:00:28 +00:00
Eric Lai be104a2760 mb/google/brya: Add flashmap descriptor
BUG=b:174266035
TEST=Build Test

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia1ba8c997680c60ee1eabfae82459e127f664117
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48062
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02 23:00:21 +00:00
Maxim Polyakov b7eca6f123 drivers/i2c/nct7802y: Move the sensor initialization procedure
The current location for the sensor initialization procedure was chosen
by mistake. Move this into a separate function in nct7802y.c .

Change-Id: I093ae75db5f0051bff65375b0720c86642b9148a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-02 22:22:50 +00:00
Julius Werner d17ce41e29 cbfs: Port cbfs_load() and cbfs_map() to new API
This patch adapts cbfs_load() and cbfs_map() to use the new CBFS API
directly, rather than through cbfs_boot_locate(). For cbfs_load() this
means that attribute metadata does not need to be read twice.

Change-Id: I754cc34b1c1471129e15475aa0f1891e02439a02
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-12-02 22:13:42 +00:00
Julius Werner 834b3ecd7c cbfs: Simplify load/map API names, remove type arguments
This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file()
to cbfs_map() and cbfs_load() respectively. This is supposed to be the
start of a new, better organized CBFS API where the most common
operations have the most simple and straight-forward names. Less
commonly used variants of these operations (e.g. cbfs_ro_load() or
cbfs_region_load()) can be introduced later. It seems unnecessary to
keep carrying around "boot" in the names of most CBFS APIs if the vast
majority of accesses go to the boot CBFS (instead, more unusual
operations should have longer names that describe how they diverge from
the common ones).

cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly
reap mappings when desired. A few new cbfs_unmap() calls are added to
generic code where it makes sense, but it seems unnecessary to introduce
this everywhere in platform or architecture specific code where the boot
medium is known to be memory-mapped anyway. In fact, even for
non-memory-mapped platforms, sometimes leaking a mapping to the CBFS
cache is a much cleaner solution than jumping through hoops to provide
some other storage for some long-lived file object, and it shouldn't be
outright forbidden when it makes sense.

Additionally, remove the type arguments from these function signatures.
The goal is to eventually remove type arguments for lookup from the
whole CBFS API. Filenames already uniquely identify CBFS files. The type
field is just informational, and there should be APIs to allow callers
to check it when desired, but it's not clear what we gain from forcing
this as a parameter into every single CBFS access when the vast majority
of the time it provides no additional value and is just clutter.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02 22:13:17 +00:00
Julius Werner 0d9072b1a1 cbfs: Move more stuff into cbfs_boot_lookup()
cbfs_boot_locate() is supposed to be deprecated eventually, after slowly
migrating all APIs to bypass it. That means common features (like
RO-fallback or measurement) need to be moved to the new
cbfs_boot_lookup().

Also export the function externally. Since it is a low-level API and
most code should use the higher-level loading or mapping functions
instead, put it into a new <cbfs_private.h> to raise the mental barrier
for using this API (this will make more sense once cbfs_boot_locate() is
removed from <cbfs.h>).

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4bc9b7cbc42a4211d806a3e3389abab7f589a25a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-12-02 22:13:06 +00:00
Julius Werner baf27dbaeb cbfs: Enable CBFS mcache on most chipsets
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is
enabled by default. Some older chipsets with insufficient SRAM/CAR space
still have it explicitly disabled. All others get the new section added
to their memlayout... 8K seems like a sane default to start with.

Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-02 22:12:10 +00:00
Furquan Shaikh 4a1cbdd51a soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry
This change drops the special check added for TGL/JSL platforms and
performs cse_fw_sync on BS_PRE_DEVICE entry. This was being done later
in the boot process to ensure that the memory training parameters are
written back to SPI flash before performing a reset for CSE RW
jump. With the recent changes in CB:44196 ("mrc_cache: Update
mrc_cache data in romstage"), MRC cache is updated right away in
romstage. So, CSE RW jump can be performed in BS_PRE_DEVICE phase.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I947a40cd9776342d2067c9d5a366358917466d58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2020-12-02 21:53:17 +00:00
Felix Held a5a529599d soc/amd: factor out common SMI/SCI enums and function prototypes
At least a part or the remaining definitions in the soc-specific smi.h
files are also common, but those have to be verified more closely.

Change-Id: I5a3858e793331a8d2ec262371fa22abac044fd4a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02 21:33:14 +00:00
Felix Held f42da176de soc/amd/common/smbus: remove misleading definition
SMBHST_STAT_NOERROR was a redefinition of SMBHST_STAT_INTERRUPT that was
used in smbus_wait_until_done. Remove the misleading bit definition that
also didn't correspond with the register definitions and replace it with
the definition of the actual bit that gets checked. Also add a comment
that the code actually checks the IRQ status flag to see if the last
command is already completed.

Change-Id: I1a58fe0d58d3887dd2e83320e977a57e271685b3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02 21:28:19 +00:00
Felix Held 43a5f88bb4 soc/amd: factor out fch_smbus_init
Change-Id: I6df9323dc4e7ca99fd5368f0262e850c0aca5c54
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02 21:27:49 +00:00
Felix Held 875e5aa96c soc/amd: factor out SMBUS controller registers into common header
The patch also rewrites the bit definition using shifts to make them
easier to read.

The older non-SoC chips can probably also use the new header file, but
for this patch the scope is limited to soc/amd, since the older non-SoC
chips don't use the SMBUS controller code in soc/amd/common.

TEST=Timeless build for amd/mandolin and amd/gardenia doesn't change.

Change-Id: Ifd5e7e64a41f1cb20cdc4d6ad1e675d7f2de352b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02 21:27:21 +00:00
Felix Held 6443ad4a53 soc/amd: factor out common AOAC device enable and status query functions
The code on Stoneyridge didn't set the FCH_AOAC_TARGET_DEVICE_STATE bits
to FCH_AOAC_D0_INITIALIZED like the code for Picasso does, but that is
the default value after reset for those bits on both platforms.

Change-Id: I7cae23257ae54da73b713fe88aca5edfa4656754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02 21:27:03 +00:00
Felix Held 5b3831c75a soc/amd: factor out common AOAC definitions
The register locations and bit definitions are the same for Stoneyridge
and Picasso. Since not all devices are present on all SoCs, keep those
numbers in the SoC-specific code.

Change-Id: Ib882927e399031c376738e5a35793b3d7654b9cf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02 21:26:50 +00:00
Mike Banon f7b410d409 vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile
The ability to set up a custom memory profile is useful if you don't
like the XMP memory profiles (if they exist) of your RAM sticks, or
want to try some overclocking. Read SPD data will be overriden by your
custom values. Tested on Crucial BLT8G3D1869DT1TX0 (1866MHz 9-9-9-27).

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I1238ff00ef0efd11ea807794827476c30ac98065
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-02 18:18:27 +00:00
Mike Banon 3ee9935f63 vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
Add XMP memory profiles support that has been tested on f15tn (A88XM-E)
and f16kb (AM1I-A) with two Crucial BLT8G3D1869DT1TX0, XMP 1 profile.
Added using the datasheets from https://github.com/mikebdp2/ddr3spd :
JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I584416e3376afdf377a11783e55c5e9ff41e6b0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40488
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02 17:05:39 +00:00