Commit Graph

31423 Commits

Author SHA1 Message Date
Kyösti Mälkki 2491d790d2 arch/x86: Remove acpi_fail_wakeup() and cbmem_fail_resume()
Unused since commit d46b8d5.

Change-Id: If0f1e0381dd7698f842dc1288ff222a4d5d4783c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35389
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-14 10:55:34 +00:00
Maxim Polyakov 66d875a143 mb/asrock/h110m: configure SuperIO global registers
Information based on superiotool dump.

Change-Id: I24ae9b1a7eab3095518341354544efe613912a6a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-14 05:48:22 +00:00
Maxim Polyakov 15b0ab51b9 mb/asrock/h110m: configure GPIOs in SuperIO chip
Enables and configures GPIOs in the NCT6791D chip. The values for
registers taken from the superiotool dump.

Change-Id: I5968a6c20cc013697d64bfbe4fc2e7b2390b72b0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-14 05:47:59 +00:00
Maxim Polyakov afd7ce680b mb/asrock/h110m: enable ACPI LDN in SuperIO
Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-14 05:47:18 +00:00
Maxim Polyakov 7d549f8908 mb/asrock/h110m: set I/O Range for SuperIO HWM
Change-Id: I30de4f40f8ca87c54faee84053c4bb0f874b2884
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35369
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-14 05:46:54 +00:00
Julius Werner b3f24b4884 arm64: Uprev Arm TF and adjust to BL31 parameter changes
This patch uprevs the Arm Trusted Firmware submodule to the new upstream
master (commit 42cdeb930).

Arm Trusted Firmware unified a bunch of stuff related to BL31 handoff
parameters across platforms which involved changing a few names around.
This patch syncs coreboot back up with that. They also made header
changes that now allow us to directly include all the headers we need
(in a safer and cleaner way than before), so we can get rid of some
structure definitions that were duplicated. Since the version of entry
point info parameters we have been using has been deprecated in Trusted
Firmware, this patch switches to the new version 2 parameter format.

NOTE: This may or may not stop Cavium from booting with the current
pinned Trusted Firmware blob. Cavium maintainers are still evaluating
whether to fix that later or drop the platform entirely.

Tested on GOOGLE_KEVIN (rk3399).

Change-Id: I0ed32bce5585ce191736f0ff2e5a94a9d2b2cc28
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-14 05:01:16 +00:00
Kyösti Mälkki 8b93689a35 timestamps: Remove TIMESTAMP_CACHE_IN_BSS
This was implemented for LATE_CBMEM_INIT support which
has already been deprecated.

Change-Id: I39225ba675bc3389e051e15b400a905431969715
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35375
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13 19:48:26 +00:00
Kyösti Mälkki b6b13c9f29 timestamps: Further simplify timestamp_reinit()
Allocation of new table always happens in romstage.

Change-Id: I089a84b372893fb3018a796fb1e16cd58753bdf4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35374
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13 19:47:58 +00:00
Kyösti Mälkki b2536f418f drivers/pc80: Remove some __PRE_RAM__ and __SMM__
Change-Id: Ic90df69c27d524086405238b9683a69771c1b9d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35388
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13 19:29:46 +00:00
Kyösti Mälkki b590a04f78 security/vboot: Replace use of __PRE_RAM__
Change-Id: Ibaeda2762c733fdbe48979b635cc0cfd7ee4295d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35387
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13 19:29:18 +00:00
Kyösti Mälkki 55d0ab5dc4 intel/broadwell: Replace some __PRE_RAM__ use
Guards are required due to different PCI accessor
signatures.

Change-Id: I60e87f16a48565917f6ee9d05cc59d2b9373270c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35381
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13 19:28:53 +00:00
Kyösti Mälkki 80f963ccd5 intel/haswell: Remove some __PRE_RAM__ use
Change-Id: I167e9a171af4fe7997ebb76cdfa22a4578817a55
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35380
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13 19:28:36 +00:00
Kyösti Mälkki e9dcc7a3c5 soc/intel: Remove some __PRE_RAM__ use
Change-Id: I35b44967de4e8d9907dc887fe35407bcaf334adc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35379
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13 19:28:19 +00:00
Peichao Wang fd15c99f4e mb/google/hatch: Merge emmc_sku_gpio_table and gpio_table to one table
BUG=b:140008849, b:140573677
TEST=verify eMMC SKU and SSD SKU will bring up normally.

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I0c0adf569cc92e8b44ab72379420f2b190fa31f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-09-13 18:05:54 +00:00
Himanshu Sahdev 20667c59d8 emulation/qemu-i440fx/fw_cfg_if.h: replace macro with enum
replace multiple existing FW_CFG_* defines with enum fw_cfg_enum.

Change-Id: I9699df4aeb2d8b18f933bb9aaed16008d10158ad
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-13 17:52:05 +00:00
Marshall Dawson 71dbcf127a drivers/intel/fsp2_0: Allocate cfg_region_size for UPD
In FSP-S, the driver constructs its pointer to UPD using the offset
in the header.  Similarly, use the header's cfg_region_size for
allocating memory and copying the default configuration.

Add sanity checks for unexpedted configuration and UPD header
conditions.

TEST=Verify OK on Mandolin, verify a mock error condition
BUG=b:140648081

Change-Id: I20fad0e27a2ad537898b6d01e5241e1508da690c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-13 09:59:56 +00:00
Himanshu Sahdev aka CunningLearner 2b84008ed9 arch/x86/bootblock_crt0.S: Leverage eax in protected mode entry
Leverage already used eax register in bootblock_protected_mode_entry.
Avoid another register ebx just for preserving eax value as it is not
needed and is not used at all after moving the value into mm0.
Allow EBX to be preserved for other usage.

Change-Id: Ia668b78f2f97cf026692f1fe63ff8a382a162474
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35292
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13 09:59:17 +00:00
Kyösti Mälkki 7f50afb0c7 drivers/elog: Add elog_boot_notify()
Change-Id: I898188d31fcfd153eb95d0a7324fa9fd85316e3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-13 09:58:33 +00:00
Kyösti Mälkki 2cce24dd4b intel/nehalem: Refactor ACPI S3 detection
Change-Id: Ib405f3c3a6143e972963307eef7371dd43b9b5fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-13 09:58:18 +00:00
Kyösti Mälkki 216db613a7 intel/fsp2_0: Move TS_BEFORE_INITRAM
Exclude FSP-M loading from the timestamps used for
RAM detection and training process.

Change-Id: I859b292f2347c6f0e3e41555ad4fb8d95a139007
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-13 09:57:25 +00:00
Selma BENSAID cfcf3c584f mb/google/drallion: Use arcada_ish.bin for arcada_cml
drallion_ish.bin is updated for drallion GPIO changes
and not compatible with arcada_cml.

TEST=Build and boot arcada_cml

Signed-off-by: Selma BENSAID <selma.bensaid@intel.com>
Change-Id: Idb35c33425bfd50533df74349dd645db18a65bc5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-09-13 09:57:12 +00:00
Bora Guvendik 349b6a1152 soc/intel/cannonlake: Allow coreboot to reserve stack for fsp
FSP BIOS 212 / 07.00.6C.40 for CNL/WHL supports FSP to use coreboot stack.
This change selects common stack config, that enables coreboot to support
share stack with FSP.

TEST=Boot to OS on WHL platform

Change-Id: I0778ee21cb4f66b8ec884b77788c05a73c609be6
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-09-13 09:56:54 +00:00
Philip Chen 48427512d6 mb/google/hatch/var: Increase Goodix touchscreen reset delay to 500ms
Even though GT7375P programming guide rev0.4 only requires a reset delay
of 120ms, in practice, we have to increase the reset delay to 500ms, or
Goodix FW update would fail.

This is a workaround. In the long run, we hope Goodix can fix the power
sequence in touch firmware.

BUG=b:138795891, b:138796844
TEST=boot helios board and verify Goodix FW update succeeded

Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: Ic0049bf240de0a1c7f1b1f39bf155d48bb76fb86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35350
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13 03:12:31 +00:00
Marshall Dawson 09d50671e6 soc/amd/picasso: Refactor AOAC enabling
Replace the raw register definitions with device numbers and macros
for determining the register offsets.  Rewrite the source to refer
to AOAC device numbers instead of a structure.

Remove the calculated offset for the console UART.  Picasso's UARTs
are not contiguous so handle them separately.

Change-Id: Iffc87f39ebe38394a56d41bb0940e9701fd05db9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-09-13 02:45:11 +00:00
Ivy Jian 59674c984e mb/google/drallion: Update memory map
This will increase ME region size and reduce the BIOS region size.

BUG=b:140665483
TEST='compile successfully'

Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I5be2580d280569421d0870a06f9b93124b564b6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35304
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-12 13:17:04 +00:00
Subrata Banik 8cced29eed soc/intel/cnl: Remove unnecessary FSP UPD “PchPwrOptEnable” usage
PchPwrOptEnable FSP UPD is for internal testing and not really available
in externally released FSP source hence assigning this UPD using devicetree
config dmipwroptimize doesn't do anything.

TEST=Build and boot sarien/arcada.

Change-Id: I6da2a088fb697e57d12008fa18bd1764b3da7765
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-09-12 13:16:46 +00:00
Patrick Rudolph d589c8681e mainboard/sifive/hifive-unleashed: Update devicetree
With the current devicetree the kernel doesn't provide any serial
after serial init.
Update the devicetree to resolve this issue.

Tested on HiFive Unleashed.

Change-Id: I4427d34a12902e0eaa2186121a53152b719cadff
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2019-09-12 13:16:24 +00:00
Elyes HAOUAS c27014b9df src/{northbridge,soc}: Remove not used #include <elog.h>
Change-Id: I01e1e356936b85b186d9bd5f1c1e5e3a1157a30b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33732
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-12 13:16:10 +00:00
Elyes HAOUAS 3270ce03d6 src/vendorcode: Remove not used #include <elog.h>
Change-Id: Id0b9fd9cd248c83b00bc84e9d21abc6b095ecf76
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33731
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-12 13:16:04 +00:00
Elyes HAOUAS 680594b50c southbridge: Remove not used #include <elog.h>
Change-Id: Ifa88e3fd824ec57c21de5967e1634c8823fe0fbb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33730
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-12 13:15:40 +00:00
Angel Pons 18a55cdd49 nb/intel/nehalem: Add a header for raminit_tables.c
This is necessary to get rid of a .c include.

Also do some cosmetic fixes to a table, now that the line length limit
has been raised.

Change-Id: I6fd7fa5c9b21368bde8f089060733df6de34b4fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-12 13:15:25 +00:00
Sridhar Siricilla b9d075b0fc src/soc/intel/common/block/cse: Make hfsts1 common & add helper functions
Host FW status 1 (FWSTS1/HFSTS1) register definition is common across SoCs,
hence move it to common. Also add below helper function,

* wait_cse_sec_override_mode() - Polls ME status for "HECI_OP_MODE_SEC_OVERRIDE".
  It's a special CSE mode, the mode ensures CSE does not trigger any
  spi cycles to CSE region.

* set_host_ready() - Clears reset state from host CSR.

TEST=Verified CSE recover mode on CML RVP & Hatch board

Change-Id: Id5c12b7abdb27c38af74ea6ee568b42ec74bcb3c
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-09-12 13:14:39 +00:00
Peichao Wang bc553e6a5b mediatek/mt8183: tune EDID for BOE panel
BUG=b:140545315
TEST=builds Kodama image and verify display working properly

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I52a56f9bbbbef5937a9601f9371e415c74ac9a7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2019-09-12 13:06:57 +00:00
Kyösti Mälkki 3c559e791f timestamps: Mostly remove struct timestamp_cache
Change-Id: Ifcd75630e562af302312f93bdf180aa90f18d21d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35290
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-12 10:17:57 +00:00
Kyösti Mälkki 72e634fa73 timestamps: Refactor CBMEM hook
Separate timestamp_sync_cache_to_cbmem() as it is only
used with ENV_ROMSTAGE.

Change-Id: Ibe18a5ecf09b2b87d8ee3e828728ad6a8a262206
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35280
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-12 10:17:33 +00:00
Aamir Bohra 8dda419b3c mb/google/hatch: Configure SATA DEVSLP pad reset config to PLT_RST
BUG=b:133000685

Change-Id: Ia12174e3254153dbca55070f5daf84fd8aac51d0
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-09-12 06:20:10 +00:00
Aamir Bohra 87bb5f5e7a soc/intel/cannonlake: Add config for sata devslp pad reset configuration
CML FSP now provides a provision to configure the SATA devslp
GPIO pad reset configuration. This config would help set the
the required pad reset configuration.

BUG=b:133000685

Change-Id: I4eaea9c6da67f1274ad3e392046a68cddc1b99b6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-09-12 06:19:53 +00:00
Subrata Banik 0e3c245c6c soc/intel/{cnl, icl}: Cache the TSEG region
This patch helps to save additional ~19ms of booting time in
normal boot and s3 resume on CML-hatch.

BUG=b:140008206
TEST=Verified normal boot time on CML-Hatch with latest coreboot

Without this CL:
Total Time: 929ms

With this CL: (TSEG marked as WB)
Total Time: 910ms

For test marked TSEG as WP/WC:
Total Time: ~920ms

Change-Id: Ie92d2c9e50fa299db1cd8c57a6047ea3adaf1452
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35026
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-12 04:28:37 +00:00
Subrata Banik 3eff037f8c soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API
This patch removes dedicated function call to make TSEG region cache
from soc and refers to postcar_enable_tseg_cache().

BUG=b:140008206

Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-12 04:28:20 +00:00
Julius Werner b3426c03b4 Revert "security/tpm/tss/tcg-2.0: Add multi digits support to tlcl_extend()"
This reverts commit fdb9805d68.

CB:33252 wasn't reviewed by a TPM maintainer and breaks abstraction
layers (pulling TSS-details into TSPI, completely changing
interpretation of the arguments to tlcl_extend() based on TSS version).
It's also not clear why it was implemented the way it was (should have
been much easier and cleaner ways to achieve the same thing).

Since the author is not reacting, let's revert it for now. It can be
cleaned up and resubmitted later. (Not reverting the header changes
since those are not objectionable, and there are later patches dependent
on it.)

Change-Id: Ice44f55c75a0acc07794fe41c757a7bca75406eb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-09-11 22:14:54 +00:00
Manoj Gupta 297e9c826f futility: Use HOSTPKGCONFIG for host PKG_CONFIG
futility is built for the host. However, when cross-compiling,
the target's pkg-config is called to get the library paths which
can add paths from the cross-compilation tree instead of host.
e.g. /build/elm/usr/bin/pkg-config gets called instead of /usr/bin/pkg-config
. /build/elm/usr/bin/pkg-config adds the paths specific to the
cross-compilation target e.g. /build/elm/usr/lib instead of /usr/lib.

This causes linker to complain that files in library paths do not
match the architecture. BFD produces a warning while LLD errors out.

Fix this by passing PKG_CONFIG from host when building futility.

BUG=chromium:999217
TEST=coreboot builds
BRANCH=None

Cq-Depend: chromium:1778519
Change-Id: Id3afbf25001cf3daa72f36a290c93136cf9f162d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35316
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11 20:41:47 +00:00
Subrata Banik 1d260e6573 intel/fsp2_0: Add help text for FSP_TEMP_RAM_SIZE Kconfig
For CML & ICL, FSP requires at least heap = 0x10000 and stack = 0x20000.
Refer to FSP integration guide to know the exact FSP requirement.

BUG=b:140268415
TEST=Build and boot CML-Hatch and ICL.

Change-Id: Ic1463181b4a9dca136d00cb2f7e3cce4f7e57bd6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35301
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11 14:46:13 +00:00
Subrata Banik 8edc6dc91f arch/x86: Cache the TSEG region at the top of ram
This patch adds new API for enabling caching for the TSEG region
and setting up required MTRR for next stage.

BUG=b:140008206
TEST=Build and boot CML-Hatch.

Change-Id: I59432c02e04af1b931d77de3f6652b0327ca82bb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-11 14:45:38 +00:00
Elyes HAOUAS d2496576f1 src: Remove unneeded include <arch/interrupt.h>
Change-Id: I3323d25b72dab2f9bc8a575ba41faf059ee1ffc4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-11 14:45:08 +00:00
Wisley Chen ded3f909cb mb/google/hatch: Create dratini variant
Create dratini variant

BUG=b:140610519
TEST=emerge-hatch coreboot, and boot into chromeos on proto board

Change-Id: Ied1240d1be831568e4ab4695b893c3f48821f68b
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35285
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11 14:44:47 +00:00
Eric Lai 3f19e1d97f mb/google/drallion: enable Elan and Melfas touch panel
Drallion uses the same touch panel as Sarien. Copy the deivce
from Sarien.

BUG=b:140415892,b:138082886
BRANCH=N/A
TEST=N/A

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8e6d2dcf4bd2ed2325137a05811af03692d40342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35305
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11 14:44:35 +00:00
Michael Niewöhner 5403a8e861 superio/common: fix regression in ssdt
ITR2 is specified twice here, which leads to the following error message
in Linux:
[    0.263591] ACPI BIOS Error (bug): Failure creating named object
[\_SB.PCI0.LPCB.SIO0.ITR2], AE_ALREADY_EXISTS (20190509/dsfield-633)

Add comments and fix duplicated field.
As there are no users of this code yet, just rename the fields.

Tested on Supermicro X11SSH-TF.

Change-Id: I4f3307d0992fcf5ad192f412c2bd15d02572a6b0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35294
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11 13:49:28 +00:00
Himanshu Sahdev 660ff2072d emulation/qemu-i440fx/northbridge.c: Fix minor whitespace
Change-Id: Ifc3825119c8463a7d17a5c162330f49612ae1b85
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-09-11 13:18:26 +00:00
Sridhar Siricilla 2cc66916e5 soc/intel/common/block/cse: Move me_read_config32() to common code
me_read_config32() is defined in multiple places, move it to common
location. Also, this function is usually used for reading HFSTS
registers, hence move the HFSTS register definitions to common location.

Also add a funtion to check if the CSE device has been enabled in the
devicetree and it is visible on the bus. This API can be used by
the caller to check before initiating any HECI communication.

TEST=Verified reading HFSTS registers on CML RVP & Hatch board

Change-Id: Icdbfb6b30a007d469b5e018a313c14586addb130
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35225
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11 09:21:13 +00:00
Kyösti Mälkki 910490f3f4 arch/x86: Restrict use of _car_global[start|end]
Restrict the use of symbol names _car_global_[start|end]
to be used exclusively with CAR_GLOBAL_MIGRATION=y.
They just alias the start and end of .bss section in CAR.

Change-Id: I36c858a4f181516d4c61f9fd1d5005c7d2c06057
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-09-11 06:28:27 +00:00