Update 3rdparty/fsp submodule to include AlderLake FSP.
Hook up the Kconfig settings to point to Fsp.fd and headers for
ADL-S and ADL-P platforms which the FSP has been published for.
The FSP binaries are compliant with the specification revision 2.3
so update these settings accordingly.
Although FSP header is v2.3 compliant, the features set of the FSP
v2.3 is not being met.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I577931da7952b681534bb78b7b2c7683cd99febd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65519
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 25b94935:
vboot_ref/futility: Wrap flashrom_drv behind USE_FLASHROM
to commit id 61971455:
vboot_ref/Makefile: Expose symbols irregardless of USE_FLASHROM
This brings in 90 new commits.
BUG=b:207808292,b:231152447
TEST=builds with vboot_ref uprev.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: Id542f555732b58e1205e757393f9d5fdbde2de68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Updating from commit id 9ab0f0b:
sc7280: Update AOP firmware to version 379
to commit id e8efa5d:
sc7180/boot: Update qclib blobs binaries from 44 to 46
This brings in 7 new commits.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I5f0a9075cde90991e927f3bfb75246bdb9877837
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Updating from:
f4bbf5a Apollo Lake MR10 FSP
Updating to:
c607bab Whitley&CedarIsland: Fix link issue with newer toolchains
This brings in 10 new commits:
* c607bab Whitley&CedarIsland: Fix link issue with newer toolchains
* 08c041d Alder Lake - P IoT FSP PV
* a3dc6c6 Alder Lake - P IoT FSP PV
* 2cedeba Alder Lake - S IoT FSP MR1
* 72266f6 Elkhart Lake MR3 FSP
* 48d4c23 Tiger Lake - IoT FSP 4391_03
* e86327d Alder Lake - S IoT FSP PV
* 478a80a Whitley FSP 2.2.0.3A
* cb94d31 Whitley FSP 2.2.0.3A
* d678813 Alder Lake - S IoT FSP PV
Change-Id: I2473bfa5718676e5b6c90b76a3b817cd9f55da4b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Updating from commit id 73193689c:
2021-12-06 16:47:33 +0100 - (Merge changes I7c9f8490,Ia92c6d19 into integration)
to commit id e0a6a512b:
2022-02-03 22:59:34 +0100 - (Merge changes from topic "msm8916" into integration)
This brings in 324 new commits.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I44bca36f4b05e08fe7d7de0966131be84c0a7d2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Updating from commit id 98db386:
2021-08-03 11:57:30 -0700 - (herobrine: Add gsi_fw_blobs and Release Notes)
to commit id 9ab0f0b:
2022-01-18 19:01:30 +0530 - (sc7280: Update AOP firmware to version 379)
This brings in 13 new commits:
9ab0f0b sc7280: Update AOP firmware to version 379
826cb9c sc7180/boot : Update qclib blobs binaries and release notes
ddf67d1 sc7280/ boot and shrm blobs updated
8592f11 sc7280: Update AOP firmware to version 364
aef8a0a sc7280/ boot and shrm blobs updated
c72bc4e sc7280/cpucp: Update cpucp blobs binaries and release notes version from 054 to 060
33e57fe sc7280/boot,/shrm : Update qclib blobs binaries and release notes version 13
511851b sc7180/boot : Update qclib blobs binaries and release notes version 30
f91d0ef herobrine: qc_sec blob update
8c50f78 sc7180/boot : Update qclib blobs binaries and release notes
8523ef4 sc7180/qtiseclib: Update version from 26 to 44
5b77a37 sc7280/qtiseclib: Update version from 33 to 44
4815cc2 sc7280: Update AOP firmware to version 360
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I510141916900507fd29a0e9315a3f8d954bc0cab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This adds the following commits:
* 22ce1b5 cezanne: Upgrade SMU to 64.60.0
* dd37ad2 cezanne: Update ABL to 0x1B096070
* 01fbf5d cezanne: Update SMU to 64.58.0
* f638765 cezanne: Update ABLs to 0x1A296070
BUG=none
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8f51cb007ce4127428b7b81095fb2c7afb33e608
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Updating from commit id 4c21b57eb:
2021-07-19 11:36:07 +0000 - (pd: Fix missing polarity_rm_dts in some conditions)
to commit id e486b388a:
2022-01-12 21:11:11 +0000 - (zephyr: Update power policy for API change)
This brings in 2212 new commits.
Signed-off-by: zhixingma <zhixing.ma@intel.com>
Change-Id: I4437f09c3193ec7c89f7f9550940a0fa5464a511
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Thejaswani Putta <theja427@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Updating from commit id 586aafa3a:
2021-07-19 05:36:18 +0200 - (Merge "errata: workaround for Neoverse V1 errata 1791573" into integration)
to commit id 73193689c:
2021-12-06 16:47:33 +0100 - (Merge changes I7c9f8490,Ia92c6d19 into integration)
This brings in 684 new commits.
Change-Id: I4173f3cb646839ad12c4e43e8c50b0be53364f04
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This brings in EC firmware binaries for Star Labs laptops, as
well as a custom bootsplash image.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iab5ff610b19fbe6a2e61999457a13a86d47f0ca7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This adds the following commits from the submodule:
* cezanne: Upgrade blobs to 1.0.0.5
* cezanne: Upgrade ABL to ver. 0x19036070
* cezanne: Upgrade SMU FW to 64.52.0
* cezanne: Upgrade SMU to 64.57.0
* cezanne: Update ABLs to 0x1A296070
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id7b3f5d38d34c2714548dff92b7b83fb2628e936
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58989
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id c5a482ed:
2021-09-08 17:16:59 +0000 - (sign_official_build: disable gsetup for reven)
to commit id 13f601f:
13f601f vboot: boot from miniOS recovery kernels on disk b
This brings in 14 new commits.
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: I66788ea434a6000435b97ce64107f3b5da882414
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57994
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This includes the Cedar Island FSP which is used by xeon_sp/cpx.
Also updates EHL FSP to latest MR1 version.
Change-Id: I1c2d440ce0f20a0922e5d91f615771843281fca6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57488
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 4423276b:
2021-08-31 17:41:34 +0000 - (crossystem: add a hwid override mechanism from chromeos-config)
to commit id c5a482ed:
2021-09-08 17:16:59 +0000 - (sign_official_build: disable gsetup for reven)
This brings in 10 new commits.
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: I67d4bfa182eae98bb23ae487f117c991502b66ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Update submodule pointer to include microcode for TGL and others.
Tested the following still boot:
- galp3-c (WHL-U): sig=0x806eb pf=0x80 revision=0xe9
- oryp5 (CFL-H): sig=0x906ea pf=0x20 revision=0xe9
- gaze15 (CML-H): sig=0xa0652 pf=0x20 revision=0xe9
coreboot reports the revision as -1 from what it actually is. i.e.,
these should report revision=0xea (and that is what Linux reports).
However, this behavior is not new.
Change-Id: I084ba67e8eaf7383f1c05fa5589b63c92ff900b1
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56861
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that gsi_fw blob has landed, need to uprev the qc_blobs.
Change-Id: I0bf67a560ee2e5d771bdb71b60e3d3d372dad567
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56776
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 1e800ac83:
2021-03-01 22:59:54 +0000 - (docs: point md files in master to main/HEAD)
to commit id 4c21b57eb:
2021-07-19 11:36:07 +0000 - (pd: Fix missing polarity_rm_dts in some conditions)
This brings in 3145 new commits.
Change-Id: Iff2e9f766e750070d71644c2f9895ad10e8b1c9a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56431
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 96404aa27:
2021-05-13 18:27:27 +0200 - (Merge "build(hooks): update Commitizen to ^4.2.4" into integration)
to commit id 586aafa3a:
2021-07-19 05:36:18 +0200 - (Merge "errata: workaround for Neoverse V1 errata 1791573" into integration)
This brings in 207 new commits.
Change-Id: Iaf8af5ffaf377070ee1430ed7cfdc51001a1ba6b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56416
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that cpucp blobs have landed, need to uprev the qc_blobs.
Change-Id: I62dc410cee7baf5efa5c0406f35ee05a535f49b1
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Updating from commit id b38e3a63:
cros_ec: Use boot mode to check if EC can be trusted
to commit id ccc56f4:
vboot: add x86 SHA256 ext support
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I4e170e84a12646386d3fd84ae97add6c19f23809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This updates the intel-sec-tools submodule pointer to include a fake
acm binary to be included for buildtesting.
Change-Id: Id4a9e177f71306b8c5538a578da229a53d19487a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This brings in three new commits that are mostly concerned about
fixing the build with gcc 11.
Change-Id: I35f9100e2bfb2a261b3a0a128697550caf5840d9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55498
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This update adds a commit to fix building libgfxinit with gcc 11
Change-Id: I5c0e3823ab7219667f9430bce74e4f2fba0c0c3a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The commit currently being pointed to is unreachable. Use the same
commit that exists in a reachable branch.
Fixes: Commit 1128817ed6
(3rdparty/intel-sec-tools: Update to support Boot Guard)
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: I1cfc08d48fe5471592fea1013e8b43bea5d7b565
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55414
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update intel-sec-tools to commit of BootGuard support.
Remove --coreboot argument in src/security/intel/cbnt/Makefile.inc:
was removed as argument for cbnt
Change-Id: Iaf34bdb65a5f067d1d632e35d340b8fc49aaf318
Signed-off-by: Christopher Meis <christopher.meis@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55013
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Newest master includes these changes:
1. Introduce the FSP package for Elkhart Lake SKUs
2. Introduce the FSP package for Tiger Lake IoT SKUs
3. Update the FSP package to latest version for Apollo Lake,
Comet Lake and Tiger Lake (client SKUs)
You can get further 3rdparty/FSP commit history here:
https://github.com/intel/FSP/commits/master
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I96d147fec82d0fcd5c7748c277deb0672a975ceb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55228
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id e681c37:
change node locked version expectations
to commit id b38e3a63:
cros_ec: Use boot mode to check if EC can be trusted
Change-Id: Id6de185af85a61a3843b302fef6fa0d4d3c17aef
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55026
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the vboot submodule from commit 57c0c5b:
cgpt: Move all GPT on SPI-NOR infra behind a flag
to e681c37:
change node locked version expectations
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: Ifd130e3f66f1819f59f00703f0ad0c2278b544bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Updating from commit id 7ad39818b:
2020-10-12 09:16:21 +0000 - (Merge "mediatek: mt8192: add GIC600 support" into integration)
to commit id 96404aa27:
2021-05-13 18:27:27 +0200 - (Merge "build(hooks): update Commitizen to ^4.2.4" into integration)
This brings in 861 new commits.
Change-Id: I912545022e4320b86ab8a382144c02e315d0c835
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Now that Boot blobs have landed, need to uprev the qc_blobs.
Change-Id: I510de2d1e4334612c81f35a082dea92d445da0bb
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Some changes:
- bg-prov got renamed to cbnt-prov
- cbfs support was added which means that providing IBB.Base/Size
separatly is not required anymore. Also fspt.bin gets added as an
IBB to secure the root of trust.
Change-Id: I20379e9723fa18e0ebfb0622c050524d4e6d2717
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52971
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 9d4053df:
2020-11-20 01:51:08 +0000 - (Revert "Reland: Clean up implicit fall through.")
to commit id 57c0c5be:
2021-04-09 11:45:39 +0800 - (cgpt: Move all GPT on SPI-NOR infra behind a flag)
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Id50a892f12ff3c4147c422c98b640ac047143128
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52453
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
mb/google/guybrush: Update APCB - disable debug
mb/google/guybrush: Add APCB to get through memory training
soc/mediatek/mt8192: Add EMI Settings of 8GB Normal Mode
soc/mediatek/mt8192: Update MCUPM firmware
soc/mediatek/mt8192: Add version info for SSPM
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I445d753c712670fe80efcdf29459736df2b76666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Updating from commit id 3a9d7cd:
2021-03-03 15:37:08 -0700 - (picasso: Update Dali SMU firmware)
to commit id dded82f:
2021-03-23 15:36:36 -0600 - (picasso: Update Dali SMU firmware)
This brings in 2 new commits.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If71e52a2a3e50aeb8599798de7b49bc71ed26a04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This includes the bg-prov tool.
Change-Id: Iba8efe3bcb67694da76ef78abaa0562d47f7850b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Michał Żygowski