Commit Graph

44506 Commits

Author SHA1 Message Date
Angel Pons 4d794bd4ec soc/intel/*/cpu.c: Add missing space in comment
Add a space before the `*/` C-style comment ending.

Change-Id: Ic8928286c8237808b9e380e4393078792589615d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-10-12 17:36:34 +00:00
Patrick Huang fcc556f88e mb/google/guybrush/var/nipperkin: update MAX98360 HID to MX98360A
Update MAX98360 ACPI HID from "MX98357A" to "MX98360A"

BUG=b:198716348
TEST=Build nipperkin, codec is functional with new machine driver.

Cq-Depend: chromium:3195465

Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Change-Id: I8a1155848856db0cc4f42cfee0d914f8d1186b34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-12 12:53:10 +00:00
Matt Papageorge cc2fa98c58 mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO Descriptor
coreboot normally owns PCIe resets for all Cezanne based systems.
However during S0i3 resume coreboot cannot intervene for S0 GPIOs
(S5 carry over fine) so we needed an alternate way to de-assert
this reset on guybrush. This change feeds in the given S0 reset
GPIO (69 in this case) so that SMU may de-assert this reset on
S0i3 resume.

BUG=b:199780346
TEST=With latest FSP verify SD device trains each of 10 cycles

Cq-Depend: chrome-internal:4157948
Change-Id: Ieee31651db30147fda84ee1aa31df7cb1c206356
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58198
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-11 15:59:10 +00:00
Matt Papageorge 0367c47eb0 vc/amd/fsp/cezanne: Add UPD fsp_owns_pcie_resets to FSP-M for Cezanne
Update UPD to include option for FSP to de-assert PCIe reset GPIOs as
specified in the DXIO descriptors. This change requires FSP version
1.0.4 revision 2 otherwise setting this value does affect any FSP
behavior.

BUG=b:199780346
TEST=Verify toggling this value is reflected in FSP

Cq-Depend: chrome-internal:4170351
Change-Id: I0dee05fb0a650f026c2f09581117fa7fb5f6a90a
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-11 15:55:35 +00:00
Felix Held 8b17cb8a8c mb/google/guybrush: drop printk in bootblock_mainboard_early_init
bootblock_mainboard_early_init gets called before console_init.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia5a1da336e8dfc451177a5319a656c407c9fef7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11 15:16:28 +00:00
Felix Held c3a9e53714 mb/google/guybrush/bootblock: add comment to PM_ACPI_CONF write
Document what setting the PM_ACPI_S5_LPC_PIN_MODE and
PM_ACPI_S5_LPC_PIN_MODE_SEL bits causes. The corresponding code will
eventually be factored out and moved to the Cezanne SoC code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I10e3eee5cfc1c5ba2c88b8b7e83e96e481f787e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11 15:16:16 +00:00
Felix Held 0cd81c325c mb/google/guybrush: simplify LPC_MISC_CONTROL_BITS update
Since the LPC_LDRQ0_PD_EN gets set right after it got cleared, we can
remove the clearing of that bit. This is split off from the previous
patch to be able to use timeless build to verify that the previous patch
didn't change any behavior.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieb300e7c7ce7e74c32ebdade0360ee4bd499b11a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11 15:16:02 +00:00
Raul E Rangel abbb5b58ec mb/google/guybrush: Use register and bit defines for eSPI setup
It's hard to understand what this code is doing because it uses hard
coded values, so use the register and bit defines instead.

BUG=none
TEST=Timeless build for guybrush results in identical binary.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d74ed3b9b4984ab1e2a22c50375baf9c9589df0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-11 15:15:54 +00:00
Felix Held 3df6f41928 soc/amd/cezanne/include/southbridge: add some more PM register defines
Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib109efe679560604ff8209b4177611eb2aa9ebdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11 15:15:41 +00:00
Felix Held 0c5885cd94 soc/amd/common/include/lpc: add definitions for LPC LDRQ control bits
The definitions of bit 9 and 10 somehow got swapped between Picasso and
Renoir/Cezanne, so put those in the Cezanne-specific header file. The
reference code writes the same values to the raw bits in both, so we
probably would still get away with putting this into the common header,
but it's better to keep the defines consistent with the documentation in
all cases.

Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03
and cross-checked to be compatible with the Picasso PPR #55570 Rev 3.16.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a033d63eeb06eed6783e4c3797ad8dea490db8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11 15:15:27 +00:00
Jakub Czapiga 3d91b47b42 libpayload: Add mock architecture
Mock architecture can be used to build libpayload using host compiler.
It can be enabled by setting ARCH_MOCK=y in the dotconfig. It sets
LITTLE_ENDIAN=y, as most machines these days use little-endian CPUs.
Libpayload will use HOSTCC as CC, HOSTLD as LD, etc. instead of tools
provided by xcompile.
Mock architecture configuration can be used by payloads for testing
purposes. Thanks to it, tests can be architecture-independent,
and can be executed without requiring compatible Kconfig options,
e.g. ARCH_ARM64=y for ARM64 machine. However, one has to provide
implementation for most architecture-specific functions present
in arch/* directories.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ie3a6e6f6cad2f8a2e48a8e546d3b79c577653080
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-11 12:59:57 +00:00
Furquan Shaikh b40fdbaa64 Makefile: Add src/soc/* to subdirs
This change adds src/soc/* to subdirs before src/soc/*/* to allow
Makefile in src/soc/* to provide any common helpers that will be
useful for any src/soc/*/*. This is done to primarily ensure that the
helpers are defined before being invoked by the SoC Makefile.inc. This
is utilized by Intel CSE stitching mechanism in following changes.

BUG=b:189177580

Change-Id: I91579a87016fdc2b9ca2d798b81969c21c18b4a3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11 12:57:58 +00:00
Matt DeVillier 8feb8669dd mb/google/fizz: Drop broken USB ACPI code
Fizz's USB ACPI code is intended to allow the OS to control port
charging power, but since Fizz's ports are dumb (vs smart), it
controls power to the port itself. The end result is that active
ports become disabled when rebooting from Windows (10/11), and
power is not restored until the device is powered down (a warm
reboot is not sufficient).

Subsequent Chromebox models (eg, Puff-based variants) don't bother
with EC-controlled USB port power, so just drop it since it's
problematic and provides no benefit.

Test: boot Windows 10/11, reboot, observe active USB ports still
functional (eg, USB KB still works)

Change-Id: I2c13d49b3ce8de8b0a38512db3c57d0c8ecbf0ad
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-10-11 12:57:18 +00:00
Matt DeVillier ff1ef8db4a nb/intel/sandybridge: Populate meminfo when using MRC
Populate a memory_info struct with PEI and SPD data, in order to inject
the CBMEM_INFO table necessary to populate a type17 SMBIOS table.

On Broadwell, this is done by the MRC binary, but the older Sandy Bridge
MRC binary doesn't populate the pei_data struct with all the info
needed, so we have to pull it from the SPD.

Some values are hardcoded based on platform specifications.

Change-Id: I15e00a01121150b778cfa684b9147d0cac97beb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-11 12:56:45 +00:00
Jakub Czapiga 4d9694e6bc tests: Fix JUNIT_OUTPUT=y to write to files instead of stderr
CB:57144 broke JUNIT_OUTPUT=y, and unit-tests were writing to stderr
instead of selected XML files, because test name used for XML file
creation contains test path. Build system did not create necessary
directiories, which CMocka required to create output files.
This commit fixes writing to XML files with JUNIT_OUTPUT=y, but had to
sacrifice path in test name, as it was causing a lot of problems
(because CMocka does not know, how to write multiple test groups to one
XML file, so it uses test group name [here __TEST_NAME__(test_group)] as
part of output filename).
Example:
 Test: tests/lib/rtc-test
 Output file:
 `build/tests/junit-tests_lib_rtc-test(tests).xml

Change-Id: I09891aca923bf1271cafeaa09f89b6539022709c
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-10-11 12:55:36 +00:00
Matt DeVillier 64fb9fc53e purism/librem_bdw: add support for ACPI brightness controls
Test: build/boot Purism Librem 13v1, verify brightness controls
work under Windows 10/11 with Tianocore payload.

Change-Id: I27d04655adcd4a5dd42b025cfccb508cfd7aaeae
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11 12:54:36 +00:00
Matt DeVillier 78a6cae9be mb/google/caroline: Update _HID for digitizer
Caroline uses a Wacom digitizer, so adjust the ACPI HID
so that the proper drivers attach under Windows/Linux.

Change-Id: I732b09001dc41a91a32a5f9260abdab435b28b8a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11 12:54:13 +00:00
Hsuan Ting Chen 3a30cf951d mb/google/guybrush: Build chromeos.c in verstage
Before attempting another commit 6260bf71 (vboot_logic: Set
VB2_CONTEXT_EC_TRUSTED in verstage_main), ensure that guybrush builds
chromeos.c in verstage to call get_ec_is_trusted() in vboot
verstage_main().

Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: Ic22519fdde1b18f6ce0237022dee02ca37181a74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11 12:53:03 +00:00
Hsuan Ting Chen 3bfe46c2b0 mb/google/guybrush: Add GPIO EC in RW to early GPIO tables
Before attempting another commit 6260bf71 (vboot_logic: Set
VB2_CONTEXT_EC_TRUSTED in verstage_main), ensure that guybrush programs
GPIO_EC_IN_RW (GPIO_91) as an early GPIO so that it can be read from in
verstage.

Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: Ia6dcb225bbca89f3a873aad75a7d67625cdd3742
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-10-11 12:52:38 +00:00
FrankChu d6606f1745 mb/google/dedede/var/galtic: Add fw_config probe for ALC5682-VD & VS
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11)
for codec selection.

ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"

BUG=b:198713670
TEST=ALC5682-VD/ALC5682I-VS audio codec can work

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Iaba136a836b89f42411474ae733380e345cce687
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58162
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-11 12:51:50 +00:00
Johnny Lin cfe15a2088 mb/ocp/deltalake: Fix SMBIOS type 9 bugs
1. Fix PCIe slot capabilities not being really read from an IIO root
   port device. The Hot-Plug capability of IIO root port cannot be
   enabled due to FSP limitation (v2.1-0.2.2.0), but the code should
   reflect the true capabilities by reading the root port device's CSR.

2. Initialize the characteristics flags to 0 in the for-loop to fix the
   issue of the flags values persists to the next iterations.

Tested=On OCP Delta Lake, dmidecode -t 9 shows the expected results.
For example without the fix it shows 'Hot-plug devices are supported'
but in fact it's not:
System Slot Information
        Designation: SSD1_M2_Data_Drive
        Type: x4 PCI Express 3 x4
        Current Usage: Available
        Length: Short
        ID: 1
        Characteristics:
                3.3 V is provided
                PME signal is supported
                Hot-plug devices are supported
        Bus Address: 0000:00:1d.0

With the fix it shows the correct result:
Handle 0x0016, DMI type 9, 19 bytes
System Slot Information
        Designation: SSD1_M2_Data_Drive
        Type: x4 PCI Express 3 x4
        Current Usage: Available
        Length: Short
        ID: 1
        Characteristics:
                3.3 V is provided
                PME signal is supported
        Bus Address: 0000:00:1d.0

Change-Id: Iea437cdf3da5410b6b7a749a1be970f0948d92d9
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58100
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-11 12:51:31 +00:00
Mario Scheithauer 08d304f05b mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devices
On this mainboard there is a legacy PCI device, which is connected to
the PCIe root port via a PCIe-2-PCI bridge. This device only supports
legacy interrupt routing. For this reason, we have to adjust the PIR8
register (0x3150) which is responsible for PCIe device 25h. The bridge
is connected to PCIe root port 7.

The following routing is required:
INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB#

TEST:
- Boot into system software

Change-Id: Id6bb8d00458c4d1e3fefd01ac3848078355868d9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-11 12:50:56 +00:00
Mario Scheithauer d7f45ea87b mb/siemens/mc_ehl: Add variant_mainboard_final()
In upcoming patches, we need mainboard specific adjustments.

Change-Id: Icf9d829b19b2d26a39ad34be4658064083e9da6d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11 12:50:10 +00:00
Mario Scheithauer 93b537f907 mb/siemens/mc_ehl2: Enable LPC ComB
Enable LPC ComB on this mainboard.

TEST:
- Boot Linux and check with 'dmesg | grep tty'

Change-Id: I7ec58685a723c177df18144011934b206e6425d0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11 12:49:46 +00:00
Mario Scheithauer 645b4d6efc mb/siemens/mc_ehl2: Disable INTEL_LPSS_UART_FOR_CONSOLE
This mainboard uses an eSPI-to-LPC bridge for console output. For this
reason, the internal LPSS UART must be disabled.

Change-Id: I86777cf719def331f4d257ddd94e9a87125ebce8
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11 12:49:29 +00:00
Mario Scheithauer 4951fe1fb7 mb/siemens/mc_ehl2: Adjust GPIOs
Set the GPIOs according to the circuit diagram for this mainboard.

Change-Id: I19dc24a16ee9f533b45879bf60fb441e24018cc8
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11 12:49:11 +00:00
Mario Scheithauer 6deadeeeca mb/siemens/mc_ehl2: Disable SATA Port 0
This mainboard has only SATA Port 1 available with no device sleep
feature.

Change-Id: I338833f2f9bcb407599cfc676ead0b8a9d7379bd
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11 12:48:55 +00:00
Mario Scheithauer 5cb62f1aa3 mb/siemens/mc_ehl2: Enable SD-Card
This mainboard has SD slot available and therefore it should be enabled.

Change-Id: I0c97e2dc589bf6b89713a473925e42a20278f457
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11 12:48:41 +00:00
Mario Scheithauer d3e6574b66 mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2
This board has the RTC RX6110SA connected to the I2C2 instead of SMBus
as in mc_ehl1. Set the bus speed for I2C2 to 100 kHz, since this RTC
only supports the standard speed.

TEST:
- Console Log shows no errors for RX6110SA during I2C2 init
- Finalize device for I2C 00:32 shows correct date and time

Change-Id: I679c6397fa0d213a25eebaf8a9e0bda9941acd26
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-11 12:48:27 +00:00
Mario Scheithauer 670462c7c6 mb/siemens/mc_ehl2: Update SPD for DDR4 devices
Since this variant uses different DDR4 devices compared to mc_ehl1 in a
memory down configuration, the SPD data file must be adapted.
In a first configuration we use Micron MT53D512M32D2NP modules.

Following values were adjusted according to this board characteristic
and with help of Serial Presence Detect (SPD) for LPDDR3 and LPDDR4
SDRAM Modules JEDEC Spec and the Specification for this Micron modules
itself:

- SPD Byte 4 - only 4Gb density instead of 8Gb for mc_ehl1
- SPD Byte 5 - different Row and Column Address Bits
- SPD Byte 29/30 - 4Gb LPDDR4 needs 130ns tRFCab
- SPD Byte 31/32 - 4Gb LPDDR4 needs 60ns tRFCpb

Change-Id: Icb25f418952f0c96117140863d0d9c897d814ac5
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-11 12:48:02 +00:00
Alex1 Kao 70a8c046c9 mb/google/dedede/var/pirika: Add Synaptics I2C touchpad device
Add Synaptics touchpad device support in devicetree.

BUG=b:201043984
BRANCH=dedede
TEST=Touchpad device function is OK

Change-Id: Ifb240d7113e401de827384697fc752a76fbf7ac7
Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-11 12:47:18 +00:00
Sumeet Pawnikar 7c1ce19abd drivers/intel/dptf: return package with value
Return the package with a value for the dptf user space service.
This is required in write tpch method for pch device under dptf
driver.

BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board

Change-Id: I64e1bb04a6115c7f93c84a5d6644101ac1d3d8ba
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11 12:47:07 +00:00
John Zhao 7227cef0d7 soc/intel/tigerlake: Add ACPI addition for USB4/TBT latency optimization
The PCI-SIG engineering change requirement provides the ACPI additions
for firmware latency optimization. This change adds additional ACPI DSM
function with both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME to the
USB4/TBT topology. The OS is informed to reduce latency for upstream
ports while connecting USB4/TBT devices.

BUG=b:199757442
TEST=It was validated that the first connected device waits only 50ms
instead of 100ms and all functions work on Voxel board.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I5a19118b75ed0a78b7436f2f90295c03928300d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11 12:46:39 +00:00
Sumeet Pawnikar e0bff814da drivers/intel/dptf: Add support for PCH methods
Add various methods support for pch device under dptf driver.
This provides support of different control knobs for FIVR.

BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board

Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11 12:45:47 +00:00
Wisley Chen 14886aec99 mb/google/brya/var/redrix: select CHROMEOS_DSM_PARAM_FILE_NAME
Enable CHROMEOS_DSM_PARAM_FILE_NAME to report dsm parameter file name.

BUG=b:197076844
TEST=build and check SSDT.

Change-Id: I726e5854bc6a8fb125cb3b7572ddedff49c3c403
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11 12:45:12 +00:00
Ian Feng 16fc6221b6 mb/google/dedede/var/corori: Add ssfc codec ALC5682-VS support
Add ALC5682-VS codec support in corori.

ALC5682-VD/ALC5682-VS use different kernel driver by different hid name.
Update hid name depending on the AUDIO field of ssfc.

ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"

BUG=b:201372531, b:194436265
TEST=ALC5682-VD/ALC5682-VS audio codec can work.

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I2f3edb0b594066714b42050a411103a215e68b12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2021-10-11 12:44:49 +00:00
Kevin Chiu 7cbeaff5de mb/google/guybrush/var/nipperkin: Enable RTD3 support for eMMC as NVMe
nipperkin has different H/W topology to guybrush that the eMMC device
is on a different GPP:
guybrush: GPP3
nipperkin: GPP2

Hence we need to enable RTD3 for nipperkin additionally which refers
to this one:
https://review.coreboot.org/c/coreboot/+/54967

BUG=b:200246826
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
     run suspend test on eMMC sku

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I1dca8f9e4739514d2d024374d8686f27b25582a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11 12:44:19 +00:00
Michael Niewöhner 607a266acc soc/intel/dnv_ns: drop redundancies from soc_fill_fadt
Drop overrides from `soc_fill_fadt` that do not differ from what common
ACPI code already sets.

Change-Id: I7a5f43f844b12ff0e9bc5c7426170383209c8e0a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-11 08:38:00 +00:00
Felix Friedlander 45ce84113e payloads/tianocore/Kconfig: Extend help for bootsplash file
Add more detail as to why a smaller-than-screen-size image is to be
preferred, in contrast to other payloads' bootsplash images.

Signed-off-by: Felix Friedlander <felix@ffetc.net>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: Ib4c6666bb0e49369fe8fe2ae3dc12c023f668da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-09 20:56:21 +00:00
Tim Crawford ca1851dc1c mb/system76: tgl-u: Add gfx register for GMA ACPI
Add gfx register to System76 TGL-U boards so GMA ACPI data is generated.

Change-Id: If944a90921b518efdcd5f0e0998bddb4f56e5764
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-09 19:28:24 +00:00
Michael Niewöhner ef353e03c2 soc/intel/dnv_ns: add the Kconfig value for CPU_XTAL_HZ
Reference: Intel doc#558579 rev2.2

Change-Id: Iab5dca6eb42abc00bc7da33f640350e994f0bd02
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-09 08:28:52 +00:00
Tim Wawrzynczak 36721a483b mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables
Before attempting another commit 6260bf71 ("vboot_logic: Set
VB2_CONTEXT_EC_TRUSTED in verstage_main"), ensure that brya's variants
all program EC_IN_RW as an input GPIO in bootblock so that it can be read
from in verstage.

Change-Id: I6b1af50f257dc7b627c4c00d7480ba7732c3d1a0
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
2021-10-08 18:11:08 +00:00
Patrick Georgi 3394f4a8f6 Documentation: Explain how to join Slack
Change-Id: I6a4d5011ea47576c9a459f20e0b368cff8a326c2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-08 15:42:25 +00:00
Michael Niewöhner ab088c9345 acpi: add macros for MSR and `unsupported` register resource types
These will be used in the follow-up change.

Change-Id: I4723ffaf0adff8cb5b1717600ed4d1634768e2b7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-08 05:21:21 +00:00
Bora Guvendik 953a8762f8 mb/intel/adlrvp: Drop INTEL_CAR_NEM Kconfig select on ADL-M RVP
This patch enables eNEM flow for ADL-M

TEST=Able to build and boot ADL-M RVP using eNEM mode.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I69959f4c53f4073e6e8b51491747d8358b4c907b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-10-08 05:19:43 +00:00
Angel Pons f6a54d2229 mb/prodrive/hermes: Enable SATA power optimizer
Enable SATA power optimizer as recommended by Intel. Tested, a SATA SSD
is still detected correctly by SeaBIOS (version 1.14.1).

Change-Id: Ia6d29de08583dfc0c2d38e8395adcaa2c540ec7b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-08 05:05:45 +00:00
Rex-BC Chen 1259da13e3 vc/mediatek/mt8195: fix misleading-indentation error
Fix misleading-indentation error in dramc_pi_calibration_api.c.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I680e9e6fffaebb23bf1f156a7f614345e952ed95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-10-08 03:41:37 +00:00
Rex-BC Chen dc9abea4fc payloads: Allow selecting UefiPayload on ARM64 platforms
Some ARM64 platforms (e.g., MT8195) are now able to compile
and run EDK2 (UefiPayload). As a result, we should allow selecting
PAYLOAD_TIANOCORE for ARM64 platforms.

TEST=show strings correctly.
1. make menuconfig
2. select Mainboard -> Vendor=Google, model=Cherry
3. select Payload -> Add a payload -> Tianocorepayload
4. make -j
5. build/cbfstool  build/coreboot.rom extract
   --name fallback/payload --file out.elf -m arm64
6. file out.elf # ELF 64-bit LSB executable, ARM aarch64
7. strings out.elf | grep tianocore # lots of tianocore stuff

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I10777a341d46240b91ceeeb1be26c33a0c5db839
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58054
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-08 03:41:25 +00:00
Sugnan Prabhu S 1de90868b7 mb/google/brya: Disable unused i2s pins for BT offload
BT offload hardware design is using only i2s0 pins. Need to disable
i2s2 pins which are not used. As per the hardware spec there is an OR
operation between vgpio and physical gpio pins related to i2s2. During
BT offload configuring the i2s2 pins to its native function is causing
offload issue on proto 2 boards.

BUG=b:201736222
TEST=Verified BT offload on brya on proto 1 and proto 2.

Change-Id: Ifbc53848c6ad12e537216cac3c2871088c094f3d
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-10-07 18:52:28 +00:00
Seunghwan Kim bd4487c869 mb/google/dedede/var/bugzzy: Update GPP_D5 configuration
As we checked the panel doesn't display firmware screen if we hold
GPP_D5(TOUCHSCREEN_RESET) low on bugzzy. It's because of that bugzzy
uses the built-in touch screen on the panel, the panel seems like
under reset state by the TOUCHSCREEN_RESET signal.
This change sets default GPP_D5 level to high for bugzzy.

BUG=b:None
BRANCH=dedede
TEST=built and verified bugzzy showed firmware screen

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I53e4fc52ceb14ba23c22d3c105f65634b09029f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Doan <edoan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-07 18:22:00 +00:00