Commit Graph

30595 Commits

Author SHA1 Message Date
Kyösti Mälkki 3e7727908c google/rambi,intel/baytrail: Simplified romstage flow
Change-Id: I99440539d7b7586df66395776dcd0b4f72f66818
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34964
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28 22:49:27 +00:00
Kyösti Mälkki 81100bf7ff soc/intel: Move fill_postcar_frame to memmap.c
Change-Id: I84b1fad52d623a879f00c3f721f480f58d7d6d8a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34894
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28 22:48:00 +00:00
Raul E Rangel 4007d7f8c7 Makefile: Pass .xcompile into genbuild_h
I'm moving the .xcompile file into the $(obj) directory so we can leave
the source pristine. We need to pass the location of .xcompile into
genbuild_h.sh.

BUG=b:112267918
TEST=Ran genbuild_h with and without an .xcompile and verified it was
passed.

Change-Id: I8b3a75b478fad92a0b09246f0a00b0580f8c4aef
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-28 18:29:15 +00:00
Patrick Georgi 3beb108a62 what-jenkins-does: Use abuild's -Z option
This reduces disk usage during builds by removing all object files and
other intermediate files directly after a build instead of waiting for
the entire build to pass.

Change-Id: Ic2feecd58658e8bac8c6e7a851737784e35b83ef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35112
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28 16:30:04 +00:00
Patrick Georgi 93bcebcfff abuild: Add -Z / --clean-somewhat option
This option removes everything in the build tree but coreboot.rom,
config.build, config.h and make.log - a useful subset of the tree for
further testing.

Change-Id: I27e559d8d7dc90d8fe5c4ed8e25249e202e5da36
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35136
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28 16:30:00 +00:00
Sumeet Pawnikar e34c80256e mb/google/hatch/variants: Increase touchscreen reset delay to 120ms
During boot sequence sometime touchscreen reset keeps failing. Also, kernel
dmesg shows "dmesg:i2c_hid i2c-GDIX0000:00: failed to reset device" message.
This adds around 4 more seconds to the boot sequence. Setting the appropriate
delay of 120ms between enable and reset for Goodix Touchscreen helps to
synchronize and address this failure. This value is 120 ms as per Goodix Spec.

BUG=b:138413748
BRANCH=None
TEST=Built and tested on Hatch system

Change-Id: I15005c568f285ec7bad9a0bec4498e2fdd20782b
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34626
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28 15:49:43 +00:00
Aaron Durbin df2bfb9a1a arch/x86/postcar: unexpose postcar_commit_mtrrs() symbol
postcar_commit_mtrrs() isn't used outside the postcar_loader
compilation unit. Make it static to reduce API surface area.
Additionally the return value was not being utilized. Modify
the return type to be void to align with the current usage.

Change-Id: If07f34467941d00de731489867e485cfff80ea63
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-08-28 13:34:19 +00:00
Kyösti Mälkki 1225afe482 google/leon: Add DRIVERS_I2C_RTD2132
This is LVDS bridge, I assume this was lost while upstreaming
or converting boards to variants.

Change-Id: I816a6b4035c4e935150cc77089c4224eee719c10
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-08-28 13:21:34 +00:00
Kyösti Mälkki 9389fdfe4d lenovo/t431s,w530: Add DRIVERS_RICOH_RCE822
Device is present in devicetree but not included in
the build.

Change-Id: I8555d94902e94c623d8fbe6f1a4ffe7637988530
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-28 13:21:20 +00:00
Meera Ravindranath 970f1a4101 soc/intel/cnl: Add CML IGD IDs
BUG=b:139798422
TEST=Build and boot CMLRVP.

Change-Id: Ib79995606f6da12bfa7aa5c1a1dbc0b972bb1688
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-08-28 11:12:33 +00:00
Jamie Chen 640215e6f4 mb/google/hatch: Enable Override DLLs for Kindred
Enable SOC_INTEL_COMMON_MMC_OVERRIDE for Kindred

BUG=b:136784418
BRANCH=none
TEST=Boot to OS 100 times on Kindred proto 1 board.

Change-Id: I390d237b9119ae42f4b0bb802bf9857552af78bf
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-28 09:22:41 +00:00
Kane Chen 01ebc74d56 soc/intel/common/block: Provide mmc.c for setting dll registers
Currently, we don't have UPDs to set emmc settings per mainboard on CML.

This code change is to create mmc.c to provide interface to override dll
settings per mainboard.

Notice: set_mmc_dll function will override the dll values in FSP.

BUG=b:131401116
BRANCH=none
TEST=Boot to OS and confirm the dll values have been overridden.

Change-Id: Ib3c72b9851f41585ec099d8ae83a721af87ed383
Signed-off-by: Kane Chen <kane.chen@intel.com>
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-28 09:22:34 +00:00
Jamie Chen fdd0e9b38f mb/google/hatch: Override DLL values for Kindred
New emmc DLL values for Kindred

BUG=b:136784418
BRANCH=none
TEST=Boot to OS 100 times on Kindred proto 1 board.

Change-Id: I52acb445c47fcdb9b60512dd501d810b1ae4dc10
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35041
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28 09:22:21 +00:00
Raul E Rangel 6325ce2ddd Makefile: Move the .xcompile rule out of the if !NOCOMPILE block
Generating the .xcompile file should be possible even without a config.

BUG=b:112267918
TEST=Ran make and verified .xcompile was created

Change-Id: I8075f71e6e3e2c150378818eeff2858c36b35843
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-28 09:22:09 +00:00
Martin Roth cf5312b17b AUTHORS: Move src/arch/ppc64 copyrights into AUTHORS file
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file.  This will happen a bit at a time, as we'll be unifying
license headers at the same time.

Additional changes in this patch:
- Move descriptions below the license header

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I51d5b1f01ff47ed752761116e3f32cb9e168584f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34637
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28 09:21:05 +00:00
Eric Lai 7cb4f4edbf mb/google/drallion: remove GBE file
Drallion doesn't have on board LAN, remove GBE bin file config.

BUG=b:139906731
TEST=emerge-drallion coreboot chromeos-bootimage and check
image-drallion.bin not include GBE region

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifbc295afd8d875b5098b0ce75252b51523a5c76e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mathew King <mathewk@chromium.org>
2019-08-28 09:20:19 +00:00
Eric Lai 65e4f7858e mb/google/drallion: add dummy SPD file
Drallion will use soldered down memory. Add dummy spd file.

BUG=b:139397313
BRANCH=N/A
TEST=Build and check cbfs has the dummy spd.bin

Change-Id: Ife59c2dd689d72b117f30e832a3ce7eed4fa4220
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35113
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28 09:19:53 +00:00
Ren Kuo 02240b7a5e mb/google/poppy/variant/nami: add sku ids of bard/ekko
add sku ids of bard/ekko

BUG=b:139886622
TEST=emerge-nami coreboot

Change-Id: Iabc3d587c3839e4a3121cea8504c50e2dc4f9699
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35115
Reviewed-by: Vincent Wang <vwang@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28 09:18:04 +00:00
Kyösti Mälkki 568a42ab8c intel/baytrail: Use smm_subregion()
Change-Id: Ic2677bcf9f2f79c4db725ebcf342a8575ee7bc38
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34739
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-27 16:14:48 +00:00
Kyösti Mälkki 44449192ab intel/baytrail: Reorganize romstage.c
Done just for future review convenience.

Change-Id: I9cfb0a8177c8ca18947ef0109550a36aa4333383
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34910
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-27 16:13:48 +00:00
Kyösti Mälkki 2a3f9f543a smsc/superio/sio1007: Fix header name
The file chip.h has a special purpose for defining the
configuration structure used in static devicetree.

Change-Id: If0289c29ca72768009c1b7166311bc4c3cee4171
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-08-27 11:52:13 +00:00
Johnny Lin eb6cac2f16 soc/intel/fsp_broadwell_de: Add ACPI HPET table
Tested on Mono Lake
TEST=Note the kernel log:
hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
hpet0: 8 comparators, 64-bit 14.318180 MHz counter

Change-Id: Idae9a7d3d4233037214d6203996bf44fe5f3a845
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35027
Reviewed-by: Johnny Lin
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-27 09:43:11 +00:00
Subrata Banik 1799011dc6 soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c code
This patch includes common romstage code to setup the console
and load postcar.

Fix booting regression issue on all latest IA-SOC introduced by CB:34893

Change-Id: I9da592960f20ed9742ff696198dbc028ef519ddf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-27 08:25:10 +00:00
Eric Lai da10b9224a libpayload/usb: add USB 3.1 GEN2 support
USB 3.1 GEN2 report speed type 4, add into speed enum.

BUG=b:139787920
BRANCH=N/A
TEST=Build libpayload and depthcharge on sarien and boot with
USB GEN2 HUB with USB disk. Check ultra speed device in cbmem log.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia0ef12b2f0d91bf0d0db766bbc9019de1614a4f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35023
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-27 07:21:00 +00:00
Martin Roth 1458777c3b AUTHORS: Move src/arch/mips copyrights into AUTHORS file
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file.  This will happen a bit at a time, as we'll be unifying
license headers at the same time.

Additional changes in this patch:
- Remove comments saying that a file is based on another file from the
coreboot project.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If61689db67c58f0d66ab96ca749bfcd589935ce2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34607
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-27 07:02:57 +00:00
Patrick Georgi 3807ecdc54 build system: add kconfig/toada to tools list
Without this, we're lacking a serialization point in abuild when doing
parallel builds. This manifests in parallel attempts to write the toada
binary, which fails.

Change-Id: Id6ebbb3750284225670608e4927d80c4eea96afb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-08-27 05:40:22 +00:00
Kyösti Mälkki a7d2f29823 intel/car: Use common TS_START_ROMSTAGE
This timestamp also got unintentionally removed from some
boards as they were transformed to use common romstage entry.

Change-Id: I12be278a674f9a2ea073b170a223c41c7fc01a94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34970
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26 22:53:31 +00:00
Martin Roth 8418fd418c x86: Introduce RESET_VECTOR_IN_RAM option
Create a new Kconfig symbol that allows an x86 device to begin execution
when its reset vector is in DRAM and not at the traditional 0xfffffff0.

The implementation will follow later, this is just to setup various
ENV_xxx definitions correctly for the build environment.

Change-Id: I098ecf8bf200550db1e15f178f7661c1ac516dc5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26 22:53:07 +00:00
Kyösti Mälkki a165c07ed7 arch/x86: Simplify <arch/early_variables.h>
This enables the use of .bss section for ENV_BOOTBLOCK
and ENV_VERSTAGE even with CAR_GLOBAL_MIGRATION=y.

In practice, boards with CAR_GLOBAL_MIGRATION=y currently
build with romcc-bootblock so they will not be using .bss.

Change-Id: Ie9dc14f3e528d3e4f48304f4d7de50df448a8af6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26 22:52:10 +00:00
Patrick Georgi 19e1d631e3 what-jenkins-does: keep essential artifacts arounds
Keep for every board: coreboot.rom, config.h, config.build

That way these can be used in follow-up jobs.

Change-Id: I5ca5cb84ab1bcffbc92a972980cd0769ebf02462
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-26 21:55:47 +00:00
Kyösti Mälkki eb0eeb21be emulation/qemu-x86: Rename memory.c to memmap.c
Change-Id: I311423cb565485236f89bd6043155aaf6296a031
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34974
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26 21:13:28 +00:00
Kyösti Mälkki f0a3d44458 emulation/qemu-x86: Use common romstage code
This provides stack guards with checking and common
entry into postcar.

Change-Id: If0729721f0165187946107eb98e8bc754f28e517
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34973
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26 21:12:29 +00:00
Kyösti Mälkki 101ef0b528 lib/bootblock: Add simplified entry with basetime
This allows for minor optimization as num_timestamps becomes
a constant zero for a function with local scope. The loop
with calls to timestamp_add() gets removed from bootblock.

Change-Id: Id230075c0e76fe377b6ea8c8ddf8318e07d29b91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26 21:11:31 +00:00
Kyösti Mälkki cd7a70f487 soc/intel: Use common romstage code
This provides stack guards with checking and common
entry into postcar.

The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.

Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26 21:08:41 +00:00
Kyösti Mälkki 16248e89ec arch/non-x86: Use ENV_ROMSTAGE_OR_BEFORE
Change-Id: I9dbf0fc14516f766fd164c7308906456f2865e89
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34982
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26 21:04:42 +00:00
Kyösti Mälkki 21160a72eb Add definition for ENV_ROMSTAGE_OR_BEFORE to <rules.h>
ENV_ROMSTAGE_OR_BEFORE is a direct replacement for testing
defined(__PRE_RAM__) as a true statement instead of with the
help of the preprocessor.

Note that for x86, due to existence of ENV_POSTCAR and ENV_SMM,
ENV_ROMSTAGE_OR_BEFORE and ENV_RAMSTAGE are not the inverse of
each other.

Change-Id: Ibd2292f922ccb9e79d10ca9bc35797048d174287
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34939
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26 20:59:45 +00:00
Kyösti Mälkki 117cf2bdcb Split MAYBE_STATIC to _BSS and _NONZERO variants
These are required to cover the absensce of .data and
.bss sections in some programs, most notably ARCH_X86
in execute-in-place with cache-as-ram.

Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26 20:56:29 +00:00
Kyösti Mälkki f2cc52b694 Move and rename ARCH_STAGE_HAS_xxx_SECTION rules
Currently only x86 requires special handling here, for simplicity
avoid introducing <arch/rules.h> and deal with this directly in
<rules.h>.

For consistency prefixes are changed from ARCH_ to ENV_.

Change-Id: I95a56dbad3482202f6cc03043589bebfb13c39af
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26 20:55:49 +00:00
Kyösti Mälkki 2f944f4da4 mb/scaleway/tagada: Remove use of car_get_var()
Board has CAR_GLOBAL_MIGRATION=n and can use .bss for a
variable that was previously declared with CAR_GLOBAL.

Test for !defined(__PRE_RAM__) can be transformed into
ENV_RAMSTAGE here as the warnings about invalid bmcinfo
structure do not need to be repeated in SMM console, which
is generally disabled anyways due to DEBUG_SMI=n.

Change-Id: I6b63213484107fa0eeb0d952d8766916b44a3c4e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-26 20:54:39 +00:00
Jamie Chen ec88c5c688 soc/intel/common: Include cometlake EMMC controller ID
Add cometlake EMMC controller ID

BUG=none
BRANCH=none
TEST=none

Change-Id: I3943dad57918df3df7885c2e2d3a86ab0e1d6008
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-08-26 20:13:35 +00:00
Martin Roth 96c075a359 AUTHORS: Move src/arch/arm64 copyrights into AUTHORS file
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file.  This will happen a bit at a time, as we'll be unifying
license headers at the same time.

Additional changes in this patch:
- Make sure files say that they're part of the coreboot project
- Move descriptions below the license header

Note that the file include/arch/acpi.h is a fantastic example of why
moving to the authors file is needed.  Excluding the guard statements,
it has 8 lines of copyrights for 3 function declarations.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I334baab2b4311eb1bd9ce3f67f49a68e8b73630c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34606
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26 19:20:00 +00:00
Yu-Ping Wu 5bfb5cc485 google/kukui: Enable CHROMEOS_USE_EC_WATCHDOG_FLAG
Kukui AP doesn't remember if the last AP reset was due to AP watchdog.
We need to enable CHROMEOS_USE_EC_WATCHDOG_FLAG so that it will query
the reset reason from EC.

BUG=b:109900671,b:118654976
BRANCH=none
TEST=1. run 'mosys eventlog clear; stop daisydog; echo > /dev/watchdog'
     2. wait for watchdog reset
     3. check 'mosys eventlog list | grep watchdog'

Change-Id: I053cc7664bbaf0d3fcae26ba9481a0ad700dca90
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-26 15:13:52 +00:00
Martin Roth 155c8023dd AUTHORS: Move src/arch/arm copyrights into AUTHORS file
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file.  This will happen a bit at a time, as we'll be unifying
license headers at the same time.

Additional changes in this patch:
- Make sure files say that they're part of the coreboot project
- Move descriptions below the license header
- Fix some spacing

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Id5f26a73f0df366651c076a94975bce1fb321b70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34605
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26 13:52:01 +00:00
Frans Hendriks 4a9cd2e237 mb/facebook/fbg1701/data.vbt: Correct EFP1 configuration
EFP1 is configured as 'DisplayPort with HDMI/DVI
compatibility'. Using this setting 4K monitor is configured
into lower resolution.

Change EFP1 setting to 'HDMI/DVI'
The next addtional small changes are made in VBT:
UEFI GOP Driver
    Child Device 2 = LFP
    Child Device 3 = EFP1/LFP
LFP Panel configuration Y-Res of Panel #10 = 1920

BUG=N/A
TEST=LCD and HDMI on Facebook FBG1701

Change-Id: Idc694b15ff94b83291a8c8252e269b7e6d96f87b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35043
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26 13:46:29 +00:00
Frans Hendriks 47cef8f95b vendorcode/eltan/security/lib: Always include cb_sha.c for bootblock
cb_sha.c depends on C_ENVIRONMENT_BOOTBLOCK.
Include cb_sha.c unconditional since C_ENVIRONMENT_BOOTBLOCK is default for
chipsets.

BUG=N/A
TEST=Boot Linux 4.20 and verify logging on Facebook FBG-1701

Change-Id: If93195596efe7d8f298430e67eb1cf79804b96fc
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-08-26 13:46:13 +00:00
Matt DeVillier 4af1fe23f8 google/link: fix detection of dimm on channel 1
Changes to the sandybridge memory init code (both MRC
and native) now require SPD data on all populated channels
in order for dimms to be detected properly, so copy
spd_data[0] to spd_data[2], as LINK always has 2
channels of memory down.

Test: boot google/link, observe onboard RAM correctly
detected on both channels

Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-08-26 13:45:32 +00:00
Asami Doi a5d9e7a628 mainboard/emulation/qemu-aarch64: Update DRAM_SIZE_MB
DRAM_SIZE_MB should be the maximum size (255GiB / -m 261120M)
that’s possible with QEMU on AArch64 virt because it tries to search
the DRAM_SIZE_MB range to find the true memory size.

Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Change-Id: Id479c0b18d1e1adceecdcca13e36119b95617e6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-08-26 07:15:06 +00:00
Asami Doi 06993ee729 lib: ramdetect: Register exception handlers for ARMv8
Register exception handlers to avoid a Synchronous External Abort
that is raised when you try to access a non-memory address on ARMv8.
An exception handler can jump over the faulting instruction.
This is the feature only for QEMU/AArch64.

Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Change-Id: I09a306ca307ba4027d9758c3debc2e7c844c66b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-08-26 07:14:03 +00:00
Aamir Bohra b0b99058cc soc/intel/cannonlake: Add config to disable display audio codec
FSP 1263 looks for UPD configuration of "AudioLinkHda"
if false it disables SDI# link for the codec.

Change-Id: I8330f47416e580bf6b9ca1faed1de5cd578d0e2e
Signed-off-by: Selma BENSAID <selma.bensaid@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35078
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26 07:13:13 +00:00
Nico Huber 4a86b3b036 nb/intel/gm45: Call ddr3_calibrate_zq() only for DDR3 :)
Change-Id: I7d00ddf727e7250b767a1c4b58bf11b17e900fc1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34828
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26 07:12:13 +00:00