Commit Graph

1913 Commits

Author SHA1 Message Date
Patrick Georgi 49f0f9a422 libpayload: Refer to vboot source consistently
Don't assume that libpayload is built from a fully checked
out coreboot tree.
There's already an override when building vboot, so reuse
that override when referring to its header files.

Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I503c69a593dd68b3a974fbdbb64d7bb25d6c7f63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-28 14:47:38 +00:00
Paul Menzel bf52cdbca1 Revert "SeaBIOS: Update stable release to 1.15.0"
This reverts commit 2a8de6dafb.

SeaBIOS 1.15.0 regresses on systems with NVMe devices [1]:

> Greetings! Was this patch set tested on bare metal hardware? I'm
> seeing "GRUB loading: Read Error" when attempting to boot from NVMe on
> various Purism Librem devices (Intel Skylake thru Cometlake hardware).
> Reverting this series resolves the issue.

So, revert back to SeaBIOS 1.14.0.

[1]: https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/message/SRECAGH4NE3XPDWJ2YI526L5LPSJWENJ/

Change-Id: If2ec738d478f11b203f499eaa28197357de6630d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61179
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-24 18:18:21 +00:00
Jakub Czapiga 28a97a2ae5 libpayload/Makefile.inc: Fix ar calls to support llvm-ar
llvm-ar does not support "open" script command, and fails with an error.
This patch fixes it by removing lines `$(AR) rc <object-files>` and
it puts them as "addmod" commands. This way all object files and
archives can be packed into one archive.

Change-Id: I0c53d1d613b5edc321e268d1d996fac3146680f8
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-20 09:22:26 +00:00
Jakub Czapiga 395f5b3129 libpayload: Install vboot headers and add include paths to lpgcc
New CBFS API uses commonlib/bsd/cbfs_serialized.h, which includes
vboot's vb2_sha.h. And, because vboot's includes are not available
in libpayload's installation directory nor in lpgcc paths, it was
causing compilation errors. This patch fixes this issue.

lpgcc will look for `vboot` directory like it is doing for `include`
directory to create correct paths. However, if payload will be built
using libpayload's build dir as a base, then vboot headers from
3rdparty/vboot will be used, as there is no way to pass VBOOT_SOURCE
from makefile to lpgcc.

Moreover, this patch moves VBOOT_SOURCE to the main Makefile to
make it available for installation target, to install headers from
vboot directory provided by caller.

Change-Id: I68dd7e1545cfcaf24547d8a9fe289447c79da222
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reported-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-15 00:22:41 +00:00
Julius Werner db29b3765b libpayload: Fix legacy CBFS code after recent refactoring
The goal when adding the new CBFS API in CB:59497 was that the old CBFS
code would be left completely untouched and just moved to the side a
bit, so that it could continue to work for the payloads that use it
until they all have time to transition to the new CBFS API.
Unfortunately, between the different iterations of the patch something
went wrong with that and the final committed version of cbfs_legacy.c
does differ in some parts from the original code, including a changed
macro definition that breaks decompression support. This patch restores
all the legacy CBFS files to exactly what they used to be (other than
the necessary changes in cbfs_core.h to avoid double definition
clashes).

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ic7fd428acb03d3830f66f807cd1d7cdbd652f409
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-01-14 00:41:13 +00:00
Jakub Czapiga a2f51f2225 libpayload/libcbfs/Kconfig: Make CBFS_VERIFICATION depend on VBOOT_LIB
CBFS_VERIFICATION was depending on the VBOOT instead of on VBOOT_LIB,
which made enabling CBFS_VERIFICATION impossible. VBOOT is not
available, like in the main coreboot, but is was changed to VBOOT_LIB,
and was not correctly adjusted in patch instroducing CBFS_VERIFICAITON
option.

Change-Id: Ie23bad5f0ed3faf17a2ed7a3ad99310ee803edd2
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-14 00:30:41 +00:00
Jakub Czapiga ad45f681aa libpayload/libcbfs: Add unverified_area APIs
This patch introduces equivalents of unverified_area CBFS access
functions added to the main coreboot tree in CB:59678

Change-Id: Ibadfd2a5cb6ad037ef1222b0a4301f90a79a127b
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-12 16:15:59 +00:00
Jakub Czapiga 63e54275f6 libpayload: Implement new CBFS access API
This commit adds new CBFS API, which is based on the one available in
the main coreboot source tree. Libpayload implementation supports RO/RW
file lookups and file contents verification.

Change-Id: I00da0658dbac0cddf92ad55611def947932d23c7
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-10 14:30:04 +00:00
Jakub Czapiga 1fa3da4d9b libpayload: Enable vboot integration
This patch introduces building and linking of 3rdparty/vboot with
libpayload. VBoot can be enabled by setting CONFIG_LP_VBOOT_LIB.
Moreover it can be configured to use either TPM or TPM 2.0 mode,
and whether to use SHA256 processor extension instructions on x86.

Change-Id: I2d9d766a461edaa0081041c020ecf580fd2ca64e
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-10 14:29:50 +00:00
Nicholas Chin 15d4b95cc6 payloads/Makefile.inc: Add warning for image built with no payload
Writing a coreboot image without a payload to a board's flash chip will
result in a non-bootable system, so warn the user if this is the case.

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Change-Id: I15ae9548a45e9f566c84db41e8e171c6bc179057
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-23 14:39:57 +00:00
Jakub Czapiga 8fac662f30 libpayload/libc/fmap: Implement new FlashMap API
This patch introduces new FlashMap API, the fmap_locate_area().
It works on cached FlashMap provided in lib_sysinfo.fmap_cache.

Change-Id: Idbf9016ce73aa58e17f3ee19920ab83dc6c25abb
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-23 14:37:42 +00:00
Jakub Czapiga e7006fb414 libpayload: Add commonlib/bsd include path to lpgcc
coreinfo and nvramcui are using libpayload/bin/lpgcc and libpayload
build directory as a base, instead of installing it first. This caused
include errors, because commonlib/bsd is not present there. This patch
introduces comonlib/bsd include path to lpgcc CFLAGS if it is being
built using libpayload build directory as a base.

Change-Id: I7d1fe9e5dc3e7c1c1ba825a1bf19972722b42778
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-23 14:37:04 +00:00
Jakub Czapiga f490d48b5c libpayload: Add -Wno-address-of-packed-member for ARCH_MOCK
When compiling libpayload using x86_64 toolchain for ARCH_MOCK compiler
reports an error about gerring address of packed member. Until now it
had to be disabled by passing -Wno-address-of-packed-member to
EXTRA_CFLAGS. This patch disables this warning.

Change-Id: I9a948fabe66f7297632ecaca8ec1bfa5c842b750
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-20 17:47:50 +00:00
Bill XIE d85cee8310 payloads/U-Boot: Fix various build errors
1. Fix the inconsistence of the target path of U-Boot payload
   between Kconfig and Makefile.inc.

2. Perform full clone (to the destined commit) in order to get
   tags.

3. Move stable commit id of U-Boot payload from Makefile to
   Kconfig, and make prompt consistent with it.

Change-Id: Ic0f11c16274456a452a0422e19fab0c61d8b5d5b
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-14 16:13:06 +00:00
Jianjun Wang 8bb59ca2fa lib: Add __fls() (Find Last Set)
Implement __fls() as an alias for log2(), and remove the duplicate
definitions in commonlib/storage/sdhci.c.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ib458abfec7e03b2979569a8440a6e69b0285ac32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-13 02:57:07 +00:00
Jakub Czapiga f7d6eb2fef libpayload: Add boot_device_read() function
This patch adds a new way of implementing flash access for libpayload.
Until now all reads had to be performed using cbfs_media, which is
obsolete. From now on all reads should be performed using
boot_device_read().

This patch also provides a default implementation of boot_device_read()
for x86 architecture.

Change-Id: I1babd2a8414ed9de3ca49903fcb4f036997b5ff3
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-10 17:56:34 +00:00
Martin Roth 2a8de6dafb SeaBIOS: Update stable release to 1.15.0
SeaBIOS 1.15.0 was released on December 2nd.  This updates the stable
version from 1.14.0 to 1.15.0

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ibc526fbddf8a13e7b00e963f9c2e73a9863c9daa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-12-09 12:19:11 +00:00
Jakub Czapiga 289e2f6a64 libpayload/Makefile: Improve object files list creation
This patch ports some parts of main coreboot Makefile to the libpayload
Makefile in order to improve object files creation.

Moreover, the coreboot source files are now accessible an will be
correctly compiled under libpayload build directory.

Change-Id: If1280c0a3f7e99aad2ecf8a0379a98af31ccefc3
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2021-12-08 14:42:25 +00:00
Jakub Czapiga 0b25e00ab1 libpayload: Add include/commonlib/bsd to installed headers
Copy header files from the main commonlib/bsd to libpayload output
installation directory.

Change-Id: Idc7175240f3077ec98280331f9a952310aae4341
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2021-12-08 14:42:02 +00:00
Julius Werner c90d406008 tests: Disable -Wmain-return-type for clang
Unit tests fail on clang 13.0 because Cmocka's main() function is
declared with return type int, but through some of our chain-include
games it sometimes gets coreboot's main_decl.h which declares the
function as void. Compilers have traditionally always been very
laissez-faire about the signature of the main function, but it seems
that clang has been getting more strict by default recently. Explicitly
disable the related warning to shut it up.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I867c9dac659be86e7b7cf4cc41d6fa105aa9ac41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-12-07 17:47:35 +00:00
Julius Werner 3332c2dc6e tests: Disable -Wsource-mgr for clang
Unit tests fail on clang 13.0 with a cryptic

  error: _timestamp_size changed binding to STB_WEAK [-Werror,-Wsource-mgr]

Probably something related to the weird things we do to mock memlayout
areas. Too lazy to track it down. Let's just disable this
(clang-specific, not properly documented) warning flag.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ie49c9eef3c74592c068c899c6717621dbcb9f609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-12-07 17:47:09 +00:00
Jakub Czapiga b88d845c56 tests: Fix objcopy --add-symbol arguments creation
Remove unnecessary escape bachslashes from:
addr="$(echo \"$$$$sym_line\" ...
The 'echo' will print output line with double quote characters, which
then will be included in the values passed to --add-symbol. This can
cause errors.

Change-Id: I6023515191d6c236bf57870159a35d518f25e9d8
Reported-by: Yu-Ping Wu <yupingso@chromium.org>
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-06 12:34:09 +00:00
Jakub Czapiga 2f236c232d libpayload: Add CBMEM_IMD_ENTRY support to coreboot tables parser
coreboot stores much information in the CBMEM IMD. Until now it was
ignored. This patch makes use of these coreboot tables entries.
It also removes get_cbmem_addr() function as it is no longer needed.

Moreover, the coreboot tables entry CB_TAG_MRC_CACHE does not exist
anymore, as it is not created by the code. It was replaced by
CBMEM_ID_MRCDATA entry, so MRCDATA should now be accessible through
sysinfo structure field.

Change-Id: I5bd02a98ba2631f34014bc0f8e7ebd5a5ddd2321
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-03 16:51:41 +00:00
Jakub Czapiga 39b2e7abdd libpayload: Add coreboot commonlib/bsd include path
Make BSD part of the coreboot commonlib accessible to libpayload.

Change-Id: I09f475d399ab785f3d3ffdb4b42950d2b397845e
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2021-12-01 13:32:06 +00:00
Simon Glass 1a2e5c5627 payloads/U-Boot: Move to v2021.10
Move to building the latest U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I33fcfc3135e55d16b0dcd8135217bd5adcef2099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-25 21:06:15 +00:00
Simon Glass 92ca892727 payloads/U-Boot: Enable the frame buffer
U-Boot normally runs with a display if available. Enable this option so
that the display shows if U-Boot supports it.

Use 'select' rather than 'imply' since the CI complains.

Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: Ie5684c6ead30076689f43034675ff9f3531970fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-25 21:05:57 +00:00
Simon Glass 6c59f377ec payloads/U-Boot: Correct start address
At present U-Boot crashes on entry as the start address is wrong. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I65e32fbb4ffea04b99abe4dc5afccfacd06c986e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-25 21:05:06 +00:00
Simon Glass 2e6c9d6488 payloads/U-Boot: Do a shallow clone
We don't need all the git history. Speed up the build by doing a shallow
clone.

Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: If31c9dd158aa23f242e4fd145449ef7502fb1ab1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-25 21:04:47 +00:00
Simon Glass ed533f7077 payloads/U-Boot: Use the correct output binary
The u-boot.bin file should be used, rather than u-boot-dtb.bin

While they are often the same, the -dtb version is really just for
legacy use now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I5558ed94c7dd6cc57ceb835fe367bfa050ad2150
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-25 21:04:36 +00:00
Simon Glass 03f0fa1822 payloads/U-Boot: Tidy up the U-Boot build
This doesn't work at present, merely printing an error when U-Boot is
selected as a payload. This is because it adds a file into the U-Boot
tree which makes U-Boot's build system think that the tree is unclean.

Update the rules to put the tag file outside the source tree. Use an
out-of-tree build for U-Boot to avoid changing the source tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I24d6545b54f97afeefaca3ffed79eec2e7afacb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-25 21:04:06 +00:00
Jakub Czapiga 7f61d41c1b libpayload/tests: Fix mocks __real_<func> symbol creation
There were escape backslashes around regular expression passed to grep.
Because of that, grep was returning empty results as a consequence of
pattern mismatch, and thus symbols pointing to original functions were
not created correctly.

Change-Id: I751109735b6c56824df9a560ae989bf062a0e9a6
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-24 14:17:01 +00:00
Jakub Czapiga c69ea3285e libpayload: Add mock assert support for unit testing purposes
Some unit tests might require catching assert failures. This patch adds
an assert() variant depending on __TEST__ define passed to unit tests.

Change-Id: I7e4620400f27dbebc57c71bbf2bf9144ca65807f
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-23 23:38:15 +00:00
Jakub Czapiga 162083072e libpayload/tests: remove tests/include/mocks include path
Some files in tests/include/mocks might have the same name as main
libpayload include files. Remove this path from default includes to
force addition of mocks/ prefix in include paths. This will help
avoiding name clashes and will also make mock headers visible.

Change-Id: I4baa07472f0379d56423cf7152b1ecc9a4824539
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-23 23:38:09 +00:00
Shelley Chen 4e9bb3308e Rename ECAM-specific MMCONF Kconfigs
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space.  Some platforms have a different way of mapping the PCI config
space to memory.  This patch renames the following configs to
make it clear that these configs are ECAM-specific:

- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH

Please refer to CB:57861 "Proposed coreboot Changes" for more
details.

BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
     Make sure Jenkins verifies that builds on other boards

Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-10 17:24:16 +00:00
Jakub Czapiga 111de557ee tests: Move x86 I/O functions to include/mock/arch/io.h
Move th x86 I/O functions declarations from tests mocks to the mock
architecture io.h. This will make x86 I/O-dependent tests simpler,
because the x86_io.h from mocks will not have to be included manually.

Change-Id: Ie7f06c992be306d2523f2079bc90adf114b93946
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-04 15:07:38 +00:00
Matt DeVillier 67258983e6 payloads/Tianocore: re-add CorebootPayload build option
Some older devices, like the x230 Thinkpad, do not boot with the
newer Tianocore UefiPayloadPkg build target, and cannot easily be
debugged without serial UART output. As a stopgap solution, re-add
the older (now deprecated/removed) CorebootPayloadPkg build target.

This partially reverts commit d3b49b4c,
"payloads/Tianocore: Update default build target, simplify build options"

Change-Id: I81490c277626fc69d95920868d80cb24c0763de4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-11-01 16:36:03 +00:00
Jakub Czapiga 12ae850dfc libpayload: Add unit-tests framework and first test case
This commit adds a unit-tests framework ported from coreboot, and test
for drivers/speaker. Usage of the unit-tests framework is same as for
the coreboot one.

Change-Id: Iaa94ee4dcdc3f74af830113813df0e8fb0b31e4f
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-10-18 12:33:49 +00:00
Jakub Czapiga 3d91b47b42 libpayload: Add mock architecture
Mock architecture can be used to build libpayload using host compiler.
It can be enabled by setting ARCH_MOCK=y in the dotconfig. It sets
LITTLE_ENDIAN=y, as most machines these days use little-endian CPUs.
Libpayload will use HOSTCC as CC, HOSTLD as LD, etc. instead of tools
provided by xcompile.
Mock architecture configuration can be used by payloads for testing
purposes. Thanks to it, tests can be architecture-independent,
and can be executed without requiring compatible Kconfig options,
e.g. ARCH_ARM64=y for ARM64 machine. However, one has to provide
implementation for most architecture-specific functions present
in arch/* directories.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ie3a6e6f6cad2f8a2e48a8e546d3b79c577653080
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-11 12:59:57 +00:00
Felix Friedlander 45ce84113e payloads/tianocore/Kconfig: Extend help for bootsplash file
Add more detail as to why a smaller-than-screen-size image is to be
preferred, in contrast to other payloads' bootsplash images.

Signed-off-by: Felix Friedlander <felix@ffetc.net>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: Ib4c6666bb0e49369fe8fe2ae3dc12c023f668da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-09 20:56:21 +00:00
Rex-BC Chen dc9abea4fc payloads: Allow selecting UefiPayload on ARM64 platforms
Some ARM64 platforms (e.g., MT8195) are now able to compile
and run EDK2 (UefiPayload). As a result, we should allow selecting
PAYLOAD_TIANOCORE for ARM64 platforms.

TEST=show strings correctly.
1. make menuconfig
2. select Mainboard -> Vendor=Google, model=Cherry
3. select Payload -> Add a payload -> Tianocorepayload
4. make -j
5. build/cbfstool  build/coreboot.rom extract
   --name fallback/payload --file out.elf -m arm64
6. file out.elf # ELF 64-bit LSB executable, ARM aarch64
7. strings out.elf | grep tianocore # lots of tianocore stuff

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I10777a341d46240b91ceeeb1be26c33a0c5db839
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58054
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-08 03:41:25 +00:00
Yu-Ping Wu e5824ff2a9 libpayload: cbgfx: Clear screen by memcpy
Instead of setting each pixel in the framebuffer, use memcpy() to clear
screen faster. As this method should be fast enough, remove the fast
path using memset().

The speed of clear_screen() on brya (x_resolution = 1920,
bytes_per_line = 7680):

- Using memset(): 15ms
- Setting each pixel: 25ms
- Using memcpy(): 14ms

Also remove set_pixel_raw() since it's now used in only one place.

BUG=none
TEST=emerge-brya libpayload
TEST=Saw developer screen on brya
BRANCH=none

Change-Id: I5f08fb50faab48d3db6b61ae022af3226914f72b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-10-07 14:11:56 +00:00
Roja Rani Yarubandi acd2218bc3 libpayload: Enable UART driver for sc7280
Add Qualcomm's QUPV3 serial driver for herobrine board

BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board.

Change-Id: I3a745afd7bbabdd29f1f369612c990526e5a2335
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-06 23:57:20 +00:00
Nick Vaccaro 15066ba8d4 driver/intel/pmc_mux/conn: Move typec_orientation enum to coreboot_tables.h
Move the locally declared typec_orientation enum from chip.h to
coreboot_tables.h.

Change enum typec_orientation name to type_c_orientation for consistency
with contents of coreboot_tables.h.

Rename TYPEC_ORIENTATION_FOLLOW_CC to TYPEC_ORIENTATION_NONE.

BUG=b:149830546
TEST="emerge-volteer coreboot" and make sure it compiles successfully.

Change-Id: I24c9177be72b0c9831791aa7d1f7b1236309c9cd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-04 17:15:47 +00:00
Nick Vaccaro a62b41819c coreboot tables: Add type-c port info to coreboot table
This change adds type-c port information for USB Type-C ports to the
coreboot table.  This allows depthcharge to know the usb2 and usb3
port number assignments for each available port, as well as the SBU
and data line orientation for the board.

BUG=b:149830546
TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds
successfully.  Cherry-pick CL to enable this feature for volteer,
flash and boot volteer2 to kernel, log in and check cbmem for type-c
info exported to the payload:
  localhost ~ # cbmem -c | grep type-c
  added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0
  added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0

Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04 17:12:48 +00:00
Julius Werner ea03d0047b device/mmio: Make buffer_to_fifo32() take a const buffer
The input buffer to the buffer_to_fifo family of functions is only read,
so it can be a const pointer. (Also, remove the MIPS check in libpayload
for these functions... the MIPS architecture has been removed a while
ago.)

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I021069680cf691590fdacc3d51f747f12ae3df31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-09-20 12:07:51 +00:00
Sean Rhodes 766e481adb payloads/external/tianocore: Add build argument for 4G Decode
Add Kconfig option TIANOCORE_ABOVE_4G_DECODE to pass build option to
edk2 to enable or disable "Above 4G Decode". Disabling allows certain Linux
distributions to boot such as Qubes, Zorin and Proxmox.

Requires commit `2f6d4cbcc7fa49462e607baed7626524ccd59ad3` that is
present in the `uefipayload_202107` branch of MrChromebox's edk2 
repository.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia3b1d15196c0ec611431af29031682fea626d19d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-09-08 07:19:10 +00:00
Jakub Czapiga c35659d930 libpayload: Move EXTRA_CFLAGS to enable option override
Before this patch EXTRA_CFLAGS were placed before many other options.
This made overriding impossible even, when necessary. This patch moves
EXTRA_CFLAGS to be placed after original CFLAGS, thus making option
overriding possible.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: If8394b151696eee4bd736d2fb1ad340209e05fbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57181
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01 19:34:20 +00:00
Yu-Ping Wu 52889c9c9f libpayload: cbgfx: Clear screen by sequential access
Currently clear_screen() calls set_pixel() to set all pixels. However,
the actual order of pixels being set depends on the framebuffer
orientation. With NORMAL orientation, the framebuffer is accessed
sequentially; with LEFT_UP/RIGHT_UP orientation, it is accessed back and
forth, leading to performance drop (>1 second on bugzzy).

Therefore, ensure sequential access to the framebuffer, regardless of
the orientation.

BUG=b:194967458
TEST=emerge-cherry libpayload
BRANCH=dedede

Change-Id: Iecaff5b6abc24ba4b3859cbc44c0d61b2a90b2d9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57104
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27 02:53:38 +00:00
Nico Huber 6cf47f524a libpayload: Mark Intel 300 series AHCI as tested
Tested with filo on roda/rw14.

Change-Id: Ia5f868d3a9cead0a872e6d3e9fdacd6eeb7f158b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56666
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12 17:57:35 +00:00
Rex-BC Chen 5889f02032 payloads/libpayload: add MTK_TIMER_V2 config
The timer structure (in particular, the offset to memory addresses)
on recent MTK SoCs for example MT8195 has been changed.

BUG=b:195274787

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ifd6ff65a825c4309c47f3b115b80a8ecd42fedac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56845
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09 01:53:20 +00:00
Matt DeVillier 94aa18f527 payloads/tianocore: update MrChromebox UEFIPAYLOAD branch
Update tianocore branch used with default UEFIPAYLOAD option to
mrchromebox/uefipayload_202107 (July 2021) branch. This branch is
rebased on edk2 upstream commit 12e34cd2f7900578ee83cb01b8f1696a7bb7511b
[OvmfPkg/Bhyve: clean up TPM_ENABLE remnants] vs tag edk2-stable202105.

The main changes are fixes for e820 table parsing and support to disable
"Above 4G decode", which is required to boot distros with bootloaders
that expect to be loaded into RAM below 4G. This fixes booting with
Qubes, ZorinOS, Proxmox, among others.

Additionally, several commits on top of upstream have been consolidated,
reworked, and/or reordered for readability and maintainability.

Change-Id: I6f04fd027a0599ca6892a1376938108a2e402ac2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-02 15:19:41 +00:00
Paul Menzel f72568cad3 payloads: FILO: Hook up autoboot options
FILO allows to configure a line to autoboot. Hook this up into
coreboot’s build system.

TEST=Configure coreboot for QEMU i440fx with FILO as payload and
configure:

    CONFIG_FILO_MASTER=y
    CONFIG_FILO_USE_AUTOBOOT=y
    CONFIG_FILO_AUTOBOOT_FILE="hda1:/vmlinuz root=/dev/sda1 console=tty0 console=ttyS0,115200 initrd=hda1:/initrd.img"
    CONFIG_FILO_AUTOBOOT_DELAY=5

Boot Debian image with:

    qemu-system-x86_64 -bios /dev/shm/coreboot/build/coreboot.rom -L /dev/shm -enable-kvm -smp cpus=2 -m 1G -hda /dev/shm/debian-32.img -serial stdio -net nic -net user,hostfwd=tcp::22222-:22

Change-Id: Id167e9a144bf466da87469108002672b299b702a
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-19 09:20:52 +00:00
Paul Menzel 1ff60178a9 libpayload: curses: Only call `serial_set_color()` with initialized values
Building nvramcui with i386-elf-gcc (coreboot toolchain
v2021-04-06_7014f8258e) 8.3.0 and Link Time Optimization (LTO) enabled
in libpayload (`CONFIG_LP_LTO=y`) fails with the error below.

        LPGCC      nvramcui.bin
    curses/PDCurses/pdcurses/refresh.c: In function 'wrefresh':
    curses/pdcurses-backend/pdcdisp.c:217:4: error: 'bg' may be used uninitialized in this function [-Werror=maybe-uninitialized]
    curses/pdcurses-backend/pdcdisp.c:214:18: note: 'bg' was declared here
    curses/pdcurses-backend/pdcdisp.c:217:4: error: 'fg' may be used uninitialized in this function [-Werror=maybe-uninitialized]
    curses/pdcurses-backend/pdcdisp.c:214:14: note: 'fg' was declared here
    lto1: all warnings being treated as errors
    lto-wrapper: fatal error: i386-elf-gcc returned 1 exit status
    compilation terminated.
    /opt/xgcc/lib/gcc/i386-elf/8.3.0/../../../../i386-elf/bin/ld.bfd: error: lto-wrapper failed
    collect2: error: ld returned 1 exit status

`pair_content()` returns in case `PAIR_NUMBER(attr)` is invalid, so
guard the usage of `serial_set_color()`.

    if (pair < 0 || pair >= COLOR_PAIRS || !fg || !bg)
        return ERR;

Note, building with x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1
20210110 does *not* fail.

Change-Id: Ic63e34f2b5bc9f826db37597bebc6b20542481d7
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-14 08:22:05 +00:00
Patrick Georgi 53ea1d44f0 util/kconfig: Uprev to Linux 5.13's kconfig
This was originally several commits that had to be squashed into one
because the intermediate states weren't able to build coreboot:

 - one to remove everything that wasn't our own code, leaving only
   regex.[ch], toada.c, description.md and Makefile.inc.
 - one to copy in Linux 5.13's scripts/kconfig and adapt Makefile.inc
   to make the original Makefile work again.
 - adapt abuild to use olddefconfig, simplifying matters.
 - apply patches in util/kconfig/patches.
 - Some more adaptations to the libpayload build system.

The patches are now in util/kconfig/patches/, reverse applying them
should lead to a util/kconfig/ tree that contains exactly the Linux
version + our own 5 files.

Change-Id: Ia0e8fe4e9022b278f34ab113a433ef4d45e5c355
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-13 20:28:14 +00:00
Furquan Shaikh bda86bd497 nvs: Add Chrome OS NVS (CNVS) information to coreboot tables
CB:51638 separated Chrome OS NVS from global NVS by allocating it
separately in CBMEM. CNVS is used in depthcharge to fill firmware
information at boot time. Thus, location of CNVS needs to be shared in
coreboot tables for depthcharge to use.

This change adds a new coreboot table tag
`CB_TAG_ACPI_CNVS`/`CB_TAG_ACPI_CNVS`(0x41) which provides the
location of CNVS in CBMEM to payload (depthcharge).

Additionally, CB:51639 refactored device nvs(DNVS) and moved it to the
end of GNVS instead of the fixed offset 0x1000. DNVS is used on older
Intel platforms like baytrail, braswell and broadwell and depthcharge
fills this at boot time as well. Since DNVS is no longer used on any
new platforms, this information is not passed in coreboot
tables. Instead depthcharge is being updated to use statically defined
offsets for DNVS.

BUG=b:191324611, b:191324611
TEST=Verified that `crossystem fwid` which reads fwid information from
CNVS is reported correctly on brya.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I3815d5ecb5f0b534ead61836c2d275083e397ff0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55665
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 18:38:14 +00:00
Nico Huber 358c84a5a8 includes: Move *abs() declarations into `stdlib.h`
Change-Id: Id4df2d3210735bee737353d293450e59cf93bd9a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55593
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 04:39:26 +00:00
Nico Huber c538ce12ae includes: Remove dangling doxygen @}
Change-Id: I05e02f9689c1a6dafb3943657a3db975c2aeacbe
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55592
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 04:38:50 +00:00
Nico Huber c1536adcf4 includes: Define `CHAR_BIT` in `limits.h`
Change-Id: Ib1d80d0c7457f90596ef5cd9d5ad0c4a33c8d473
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55591
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 04:38:33 +00:00
Nico Huber 2eae410c54 includes: Provide `wchar.h` with `wchar_t` and `wint_t`
Change-Id: Iacb0e4eaf3f0b6bf843f3bfda5bdfde0f7a98808
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55590
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 04:38:16 +00:00
Nico Huber 0a31d5e7f5 includes: Add include guards to `stddef.h`
Change-Id: Ifae4f07abd75da9784967c2020eed2c3fe64afa0
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55589
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 04:37:18 +00:00
Matt DeVillier c6a3f34096 payloads/tianocore: Fix orphaned reference to 'bootloader' variable
commit d3b49b4
[payloads/Tianocore: Update default build target, simplify build options]
simplified the build string and removed the bootloader Makefile variable,
but one reference was missed. Luckily the variable being empty didn't
break things, but correct it regardless.

Change-Id: If37b291dda59c20bfe4c6e5b9100fac52d11a2f4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55239
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07 11:34:50 +00:00
Matt DeVillier 3469378a17 payloads/tianocore: Restrict bootsplash option to UEFIPAYLOAD
The custom bootsplash option only functions when using the UEFIPAYLOAD
payload option, so restrict visibility to when that option is selected.

Change-Id: If5fe46b629e5275da54a5e86465a68271110397b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-07 05:06:01 +00:00
Matt DeVillier ba7f116728 payloads/tianocore: Add Kconfig option to enable cbmem logging
Logging to coreboot cbmem, instead of a serial console, was
added to MrChromebox's uefipayloadpkg branch. Add a Kconfig
option to enable this, and restrict it to the UEFIPAYLOAD
payload option, since this feature does not exist in upstream
edk2.

Change-Id: Idef125235dc7ba885eb22ac69c6f752588a9e295
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2021-06-07 05:05:24 +00:00
Angel Pons 17852e61df option: Turn CMOS option backend into choice
In order to add more option backends, transform the current CMOS option
backend into a Kconfig choice. Replace the `select` directives, as they
cannot be used with choice options.

Change-Id: Id3180e9991f0e763b4bae93a92d40668e7fc99bc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-28 11:37:16 +00:00
Lijian Zhao 943e479b3e payload/tianocore: Drop TIANOCORE_TARGET_IA32
Since upstream edk2 totally drop 32-bit support for UefiPayload, totaly drop it.

Test: Build and run qemu successful boot up into EFI shell with UEFIPAYLOAD option.

Change-Id: Iadd9a3c455fad4eede8a0a017415acd2c57fba04
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54189
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18 10:04:47 +00:00
Matt DeVillier d3b49b4cda payloads/Tianocore: Update default build target, simplify build options
Drop the deprecated COREBOOTPAYLOAD option, and replace it with MrChromebox's
updated UefiPayloadPkg option. Simplify the Kconfig options to make it easier
to build from upstream edk2 master. Drop the TIANOCORE_USE_8254_TIMER Kconfig
option since it applied only to CorebootPayloadPkg. Clean up the Makefile now
that we're only building from a single Tianocore package/target.

Test: build/boot qemu Q35 target with both UefiPayload and Upstream options.

Change-Id: If545fbd0c30be6dcc6ff43107b80980fa23a527e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54019
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-13 08:30:57 +00:00
Duncan Laurie d87bbde169 libpayload: i8042: Enable keyboard translation by default on exit
Add a Kconfig option to set the keyboard translation state on exit and
set the default to true.  This restores the keyboard to the power-up
defaults for firmware that does not always run libpayload keyboard init
to have consistent state, and provides an option to disable translation
for keyboards that might need it.

Change-Id: I25dfe3f425a5bb57e97476564886672b707aa3bd
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-05-03 15:55:52 +00:00
Bora Guvendik 5f445f97c2 payloads/depthcharge: Use static_fw_config.h file for depthcharge build
Use static_fw_config.h during depthcharge build to be in line with latest
depthcharge changes on the main branch.
https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/2523517

BUG=none
TEST=Boot to OS

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I72a681d9321750c392000e11a21d81020dde3fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
2021-04-23 15:37:45 +00:00
Nico Huber 1f2b5fb201 libpayload/keyboard: Reset to scancode set #2 on exit
If we select scancode set #1 and keep that, it can confuse Linux
with keyboards that don't return to set #2 when asked to load the
defaults. This happens for instance with various integrated Think-
Pad keyboards but was also seen with an external PS/2 one.

The chosen configuration, scancode set #2 without translation, seems
to be the default for many systems. So we can expect other payloads
and kernels to work with it.

Change-Id: I28d74590e9f04d32bb2bbd461b67f15014f927ec
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18 20:45:23 +00:00
Nico Huber 4dc92782fc libpayload/keyboard: Add a detention state
Instead of ignoring keyboards indefinitely when they failed to
initialize, we wait 5s and then start over with the hotplug
detection. As we always assume a present keyboard at first,
we'd otherwise never have a chance to hot plug a device after
the initial 30s timer ran out.

Change-Id: I8dec4921b2e932442d52b5118cdcf27090633498
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18 20:45:02 +00:00
Nico Huber e97d320df2 libpayload/keyboard: Implement hot (un)plugging
While we assume a keyboard is attached, we send an echo command every
500ms. If there is no data coming from the keyboard within 200ms, we
assume it was detached.

Correspondingly, if we assume no keyboard is attached, we run an echo
command once per second.

Change-Id: I2c75182761729bf30711305f3d8b9d43eafad675
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18 20:43:58 +00:00
Mike Banon 40df8aa84b tint: introduce the new tint build system with checksum verification
Three stages of the new tint build system:

 1) generate_core.sh extracts the core part from buildgcc script,
     most importantly the checksum calculation/verification functions.

 2) tintify_core.sh adds the tint-specific footer/header to the core,
     such as the properties of current version including its checksum.

 3) tint.sh - generated and "tintified" core script - builds a tint.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ib71f5b861ecf91949a5af12812258e60873f0498
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-04-16 06:49:18 +00:00
T Michael Turney 0ce7f4da70 libpayload: Support herobrine
BUG=b:182963902
TEST= validated on qualcomm sc7280 developement board

Change-Id: Ic28f02cdf5c0e4c2458aee0ad7c74383c88d8874
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-04-15 19:08:23 +00:00
Meera Ravindranath 5c9bacca32 payloads/external/dc: Update depthcharge branch from master to main
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Change-Id: Ice0b908b23921cd9afbef52d2471f5ded277a136
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-15 10:54:27 +00:00
Matt DeVillier 544d7e2b91 payloads/tianocore: Fix compilation for UEFIPAYLOAD option
Upstream edk2 dropped separate 32-bit support for UefiPayloadPkg, and
removed the architecture suffix from the package dsc filename.

Test: build/run qemu with CONFIG_TIANOCORE_UEFIPAYLOAD selected.

Change-Id: I40077f1d370f0cb5627645b305b57e6c71e44095
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-04-10 20:24:50 +00:00
Alexander Couzens 605c6da4e4 payloads/LinuxBoot: make linux kernel build reproducible
Reproducible builds have to be independent from user, host,
domain, time.
Taken from OpenWrt (GPL2).

Change-Id: I420588acc66647051c08e4da6fbedc205cd62877
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35393
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-09 06:09:59 +00:00
Thomas Heijligen fffc21d3dc libpayload/storage: Add NVMe driver
Tested with qemu virtual NVMe and Intel hardware. Works with FILO.

Change-Id: Ie75b1dc743dac3426c230c57ee23b771ba3a6e0c
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33582
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-07 10:58:04 +00:00
Alexander Couzens 6e4e6207f1 payloads/LinuxBoot/u-root: add boot template to u-root
Without the boot template, u-root doesn't include any boot commands.
Booting other OS is impossible.

Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: I7d0742d115715eb40e293e2a8711d1ff20d8970a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51331
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14 02:41:56 +00:00
Patrick Georgi 9de060fd34 libpayload: Use volatile pointers in {read,write}{8,16,32,64}
This is already the case on x86 but not on the ARM platforms, and
{read,write}[bwl] are using volatile pointers, too, so follow suit.

Change-Id: I6819df62016990e12410eaa9c3c97b8b90944b51
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20 17:01:09 +00:00
Martin Roth 5c7341331d treewide: Remove trailing whitespace
Remove trailing whitespace in files that aren't typically checked.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I8dfffbdeaadfa694fef0404719643803df601065
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-17 17:30:05 +00:00
Mike Banon f124939945 tint: update the patch version numbers according to a new tint version
Rebase the libpayload_tint.patch to update its internal version
numbers from 0.04+nmu1 to 0.05.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I91f780f80026147c3c35330625a4106c65a1ddf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50468
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:17:51 +00:00
Mike Banon f238ead6f1 tint: update the archive from 0.04+nmu1 to 0.05
Old archive is not available anymore. The tint sources inside the new
archive are the same (something changed in a debian subdirectory but
we aren't using it), so a libpayload_tint.patch is still valid.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: If556fac7d1d8379a022f59ed6aee1450b7bc5aa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48616
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07 22:00:23 +00:00
Nico Huber b726e09157 payloads: Force sub-make runs for in-tree payloads
The sub-process calls break make's dependency tracking, hence we have
to always perform the calls if we want to allow automatic, incremental
builds.

We let each rule depend on a new, phony target `force-payload`. It has
roughly the same effect as tagging all the targets as phony, but doing
so would feel wrong as some of them are actual files.

Change-Id: I1bc2406db371e8dddbfdf71f68a6665a5b558f5e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07 16:31:56 +00:00
Nico Huber a7d3293886 payloads: Pass $(CCACHE) on to in-tree payloads
Change-Id: Ie15aec4059fbeb99f714c3d674df5fabdb7c081c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07 16:27:07 +00:00
Nico Huber dd11bf9fe3 nvramcui: Use libpayload's new `Makefile.payload`
Change-Id: I34bf659c1a069ccc27ca613bbf86780d4da49259
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47636
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07 16:23:33 +00:00
Nico Huber 552163ef79 coreinfo: Use libpayload's new `Makefile.payload`
Change-Id: I388d60e6f3aeb2184966152f0934845d42834de0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47634
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07 16:22:56 +00:00
Nico Huber 9c8f0424d6 libpayload: Add a Makefile for in-tree payloads
The new `Makefile.payload` can be included by the Makefiles of pay-
loads for in-tree builds. The basic idea is to use libpayload's
build results without the `make install` step, and to ensure that
incremental builds work. For instance, if libpayload's code changes,
a `make` for the payload would automatically update the libpayload
build and rebuild the payload. But if there are no code changes in
libpayload, only updated files of the payload will be re-built.

The configuration of libpayload is supposed to be automatically
generated from a `defconfig` file. If this `defconfig` changes,
libpayload and the payload will be re-built.

Change-Id: If5319f1bf0bcd09964416237c5cf7f8e59f487a2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47633
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07 16:22:45 +00:00
Nico Huber 30570a7de1 nvramcui: Unexport COREBOOT_EXPORTS
coreboot's Makefile exports a lot of variables that influence make sub-
processes (e.g. for Kconfig). We don't want these variables leak into
sub-processes for (lib)payload builds, hence unexport them.

Change-Id: I8da2d8db6238d456723b9c22bee80c62e97027b0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48940
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07 16:11:32 +00:00
Nico Huber 1132600478 coreinfo: Unexport COREBOOT_EXPORTS
coreboot's Makefile exports a lot of variables that influence make sub-
processes (e.g. for Kconfig). We don't want these variables leak into
sub-processes for (lib)payload builds, hence unexport them.

Change-Id: I7d65c0aa6d4550bd6600c437e838339af69496da
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48939
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07 16:11:19 +00:00
Arthur Heymans 372766f26b payloads/external/FILO: Pass Libpayloads path on the clean target
FILO's Makefile will check for libpayload and might not even `clean`
if it's not found.

Change-Id: If5f8f4ecce317e54cd4b5688553cc38220f6e6df
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-06 18:55:54 +00:00
Elyes HAOUAS 9c55c37a18 payloads/libpayload/arch/arm64/mmu.c: Fix typo in comment
Change-Id: Ieb10a881ef1d983f11318f0f6934491fd19fd0bf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-02-05 09:40:39 +00:00
Elyes HAOUAS 00b5f53361 treewide [Kconfig]: Remove useless comment
Change-Id: I3dafffa61f4fe6089fd11ef6579626aff8088df5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-02 13:49:49 +00:00
Patrick Georgi 60f5328c7d libpayload/arm*: Add 64bit memory access primitives
Add read64 and write64 for consistency with x86.

BUG=b:178785769

Change-Id: I342e3a23201d0b804ea5ecfe47ee3e4bb516de4c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-30 20:17:47 +00:00
Patrick Georgi 2cc5bcbf7f build system: Always add coreboot.pre dependency to intermediates
They all operate on that file, so just add it globally.

Change-Id: I953975a4078d0f4a5ec0b6248f0dcedada69afb2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-15 23:54:09 +00:00
Patrick Georgi d6eb72c87e build system: Structure and serialize INTERMEDIATE
Target added to INTERMEDIATE all operate on coreboot.pre, each modifying
the file in some way. When running them in parallel, coreboot.pre can be
read from and written to in parallel which can corrupt the result.

Add a function to create those rules that also adds existing
INTERMEDIATE targets to enforce an order (as established by evaluation
order of Makefile.inc files).

While at it, also add the addition to the PHONY target so we don't
forget it.

BUG=chromium:1154313, b:174585424
TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2
timeout and sercon) and saw that they were executed.

Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-14 16:53:06 +00:00
Nico Huber 92675d6723 nvramcui: Make local render_form() function static
Allows us to build with `-Wmissing-prototypes`.

Change-Id: I722b41e515ee472697028a912b9136ce59611051
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47635
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-13 12:14:11 +00:00
Nico Huber 712ca31933 libpayload/lpgcc: Drop redundant linker path
It either doesn't exist (in-tree builds) or is the same as $_LIBDIR.

Change-Id: I9551cbfc3295d86c22a3785be7cdc0f65eeb08c4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47632
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11 23:33:03 +00:00
Nico Huber ec70383acc libpayload/lpgcc: Set proper include paths for in-tree builds
We only need `$_OBJ` in the include path for in-tree builds. Also,
curses only need special handling for those and PDCurses turned out
to need many more include paths.

Change-Id: Idd29ef33065033e26ba61b09d412d8ca3566d643
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-11 23:32:32 +00:00
Nico Huber 3e0b3f17af libpayload/lpgcc: Add more variables to support in-tree builds
Add $_DOTCONFIG and $_XCOMPILE pointing to the respective files and
use them.

Change-Id: I719b42d1c8abf055948daf5b000daa30cd249edd
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-11 23:31:45 +00:00
Arthur Heymans c6bdabd983 payloads/external: Update cbfs-ints with CONFIG_UPDATE_IMAGE
Change-Id: Icfbfff3ba680a85eb2f683867064b19f40b9d40f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48898
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:09:08 +00:00
Arthur Heymans 17c951b2c4 */Makefile.inc: Add some INTERMEDIATE targets to .PHONY
Change-Id: I125e40204f3a9602ee5810d341ef40f9f50d045b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48897
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:08:07 +00:00
Nico Huber 9d233ba9a9 libpayload/lpgcc: Check for `libpayload.config` for in-tree builds
Instead of checking for an already fully build `libpayload.a`, we check
for the `libpayload.config` which is the actual prerequisite to start
using `lpgcc`. This will allow compilation of payload sources before or
in parallel with the build of `libpayload.a`.

Change-Id: Ic0143fefe33560af8b013ae48bbbe231b3ad46f3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-01 21:42:41 +00:00
Nico Huber dc5c83812b libpayload/lpgcc: Turn references to build dir into a variable
Introduce a `$_OBJ` variable, that points to the build directory for
in-tree usage of `lpgcc`. If unset, the default `../build` relative
to the location of `lpgcc` is used.

Change-Id: I35112d7533d69aa51252dd2bceec010a62522403
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47629
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-01 21:41:48 +00:00
Nico Huber 1dba2ed806 libpayload: Keep a copy of .config in the build dir
This should make it easier to find the correct config for in-tree
builds.

Change-Id: I08d396ae3cedc65f63c4b8865701ea123c7d56cb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47628
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-01 21:31:29 +00:00
Nico Huber 1823d53cbf libpayload: Move .xcompile into $(obj)
Keep libpayload's xcompile in its build dir. While we are at it,
align things with the top-level version.

Having `.xcompile` in a central place led to race conditions when
multiple payloads try to build their own libpayloads in parallel.

Change-Id: I504e1862db79b368289867f7568c9169f27a1549
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-01 21:30:44 +00:00
Matt DeVillier 4b9b44696d payloads/tianocore: Clean up build string
Extract the architecture (-a) and package (-p) options into a
new variable (ARCH) to simplify the construction of BUILD_STR.

Test: build/boot various boards w/Tianocore payload

Change-Id: I490d48428ac56d613d0b704700dfcf4ebfb2d245
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48942
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-30 01:27:51 +00:00
Matt DeVillier 61a3c8a005 payloads/tianocore: Add Kconfig to set boot timeout
Add a Kconfig option to set the tianocore boot timeout,
which is passed to the payload via a command line parameter.

Allows boards without an internal display (eg) to set a longer
boot timeout, in order to ensure the boot splash/menu prompt
are visible upon boot.

The associated changes on the tianocore side have already been
merged into MrChromebox's CorebootPayloadPkg and UefiPayloadPkg
branches (coreboot_fb and uefipayloadpkg respectively).

Change-Id: Ifeaadff05f6667d642c05b81f53c1d2dbc450af6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-28 16:47:59 +00:00
Nico Huber 4f7b687fb7 libpayload/i8042: Add API to peek on keyboard input queue
Change-Id: I60699e044b5bacd3f5292fed7edbf529ae133284
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47592
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24 08:29:18 +00:00
Nico Huber 6e021d31f9 libpayload/keyboard: Add debug output to all state transitions
Change-Id: I643a821d4c41fc068f2bab0bd571b0a4a359f59a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24 08:29:07 +00:00
Nico Huber b2569eaa82 libpayload/keyboard: Hide console output by default
Change-Id: I855d975a4729da34a6fa73a63dbbd12c856bdc00
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24 08:20:32 +00:00
Nico Huber e9c572f203 libpayload/keyboard: Implement self-test
The keyboard self-test is required for some devices. At least one
device (integrated keyboard in a ThinkPad X201) actually starts the
test automatically leading to spurious output and no response for
the first seconds.

We wait up to 5s for the self-test result. On failure or timeout,
the command will be repeated until the 30s init timer runs out. This
happens all in the background of the UI polling loop.

To not unnecessarily delay the boot process, we first try an oppor-
tunistic initialization which skips the self-test.

Change-Id: Ie07b31e74d06e116ac81e76309621eed39a19b49
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24 08:20:16 +00:00
Nico Huber 777c599747 libpayload/keyboard: Add timestamp to track time spent in a state
Will be used to time out in states that don't always advance.

Change-Id: I28235e7638d8157cedf81fd915a41d28a1fc070b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47087
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24 08:20:01 +00:00
Nico Huber 260dd9eb7e libpayload/keyboard: Turn init sequence into a state machine
We'll process the init sequence as part of the polling loop. This
should have several advantages:

* It eases error handling, i.e. we can return to an earlier state.
* We don't have to stall initialization when a keyboard takes a
  little longer.
* Generally, these keyboards can be hot-plugged (albeit not by
  design).

Change-Id: I9cf5cf31eb420b3994bec20e56a72d37f3d2996e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24 08:19:48 +00:00
Nico Huber 828f6b428e libpayload/keyboard: Avoid races around input draining
Draining the keyboard's buffer is only possible when the keyboard
port is enabled. We should also disable input scanning before, as
the buffer could be filled again with new keystrokes otherwise.

Change-Id: Ibac9c0d04880ff4a3efda5ac53da2f9731f6602c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24 08:19:18 +00:00
Nico Huber f7faac151a libpayload/keyboard: Introduce keyboard_drain_input()
Move the input-buffer draining into a function. It uses the low-level
i8042 API directly to avoid conflicts with changes in the high-level
keyboard API.

Change-Id: I9427c5b8be4d59c2ee3da12d6168d34590043682
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47084
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24 08:18:57 +00:00
Nico Huber a160d93dda libpayload/keyboard: Revise keyboard_cmd() error handling
Even if we are careful, it's still possible that we read spurious
data from the keyboard, e.g. keystrokes. Namely, when we send the
reset/disable command, there is a race before the command is pro-
cessed.

So we should always process data from the keyboard in a loop. We
break it, when an ACK (0xfa) or a NAK (0xfe) is received, and warn
on unexpected data unless it might be due to the mentioned race.

This also gives us the opportunity to use command-specific timeouts
which we take from Linux: 1s for the keyboard self-test (as there
are keyboards that perform the test before acking the command) and
200ms for all other commands.

Change-Id: I60a2643a8ff4b9231c63bf970c8749c97c7d8926
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24 08:18:41 +00:00
Nico Huber a69d682a0b libpayload/keyboard: Revise scancode set and translation config
Some background first: The original XT keyboards used what we call
scancode set #1 today. The PC/AT keyboards introduced scancode set #2,
but for compatibility, its controller translated scancodes back to
set #1 by default. Newer keyboards (maybe all we have to deal with)
also support switching the scancode set.

This means the translation option in the controller and the scancode
set selection in the keyboard have to match. In libpayload, we only
support set #1 scancodes. So we either need the controller's trans-
lation on and set #2 selected in the keyboard, or the controller's
translation off and set #1 selected in the keyboard.

Valid configurations:
* SET #1 + XLATE off
* SET #2 + XLATE on

Both with and without the PC_KEYBOARD_AT_TRANSLATED option, we were
only configuring one of the two settings, leaving room for invalid
configurations. With this change, we try to select scancode set #2
first, which seems to be the most supported one, and configure the
controller's translation accordingly. We try to fall back to set #1
on failure.

We also keep translation disabled during configuration steps to
ensure that the controller doesn't accidentally translate confi-
guration data.

On the coreboot side, we leave the controller's translation at its
default setting, unless DRIVERS_PS2_KEYBOARD is enabled. The latter
enables the translation unconditionally. For QEMU this means that
the option effectively toggles the translation, as QEMU's controller
has it disabled by default. This probably made a lot of earlier
testing inconsistent.

Fixes: commit a95a6bf646 (libpayload/drivers/i8402/kbd: Fix qemu)
       The reset introduced there effectively reverted the scancode
       selection made before (because 2 is the default). It's unclear
       if later changes to the code were only necessary to work
       around it.

Change-Id: Iad85af516a7b9f9c0269ff9652ed15ee81700057
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-23 03:29:32 +00:00
Nico Huber 0e1d19baa6 libpayload/i8042: Add API to get/set kbd translation state
Change-Id: I49aa1c244cb60ea290df102f06f641c765f59fa5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-23 03:29:16 +00:00
Furquan Shaikh 493937e1d6 coreboot tables: Add SPI flash memory map windows to coreboot tables
This change adds details about the memory map windows to translate
addresses between SPI flash space and host address space to coreboot
tables. This is useful for payloads to setup the translation using the
decode windows already known to coreboot. Until now, there was a
single decode window at the top of 4G used by all x86
platforms. However, going forward, platforms might support more decode
windows and hence in order to avoid duplication in payloads this
information is filled in coreboot tables.

`lb_spi_flash()` is updated to fill in the details about these windows
by making a call to `spi_flash_get_mmap_windows()` which is
implemented by the driver providing the boot media mapping device.

BUG=b:171534504

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I00ae33d9b53fecd0a8eadd22531fdff8bde9ee94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48185
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 22:56:09 +00:00
Meng-Huan Yu c9655468e8 libpayload: Provide API to expose MMU memery ranges for ARM64
Provide get_mmu_ranges() for ARM64 to let payloads could get
MMU ranges for all used memory regions.

BUG=b:171858277
TEST=Build in x86, arm, arm64.
  emerge-zork libpayload depthcharge
  emerge-nyan libpayload depthcharge
  emerge-asurada libpayload depthcharge

Signed-off-by: Meng-Huan Yu <menghuan@google.com>
Change-Id: I39b24aefc9dbe530169b272e839d0e1e7c697742
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-05 09:45:34 +00:00
Caveh Jalali 6de5bf6698 libpayload/usb: Add format string checking to usb_debug
This turns on the compiler's printf style format string checker.

BUG=b:167517417
TEST=enabled all USB controllers on volteer and fixed resulting
	compiler errors when USB_DEBUG is enabled.

Change-Id: Ic94ebcbafdde8a5f79278b5635111b99af40f892
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45025
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22 22:34:55 +00:00
Caveh Jalali 8079a6a558 libpayload/usb: Fix printf format string mismatches in debug messages
This fixes format string mismatch errors in the USB subsystem found by
the compiler's format string checker.

BUG=b:167517417
TEST=enabled all USB controllers on volteer and fixed resulting
	compiler errors when USB_DEBUG is enabled.

Change-Id: I4dc70baefb3cd82fcc915cc2e7f68719cf6870cc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-22 22:34:52 +00:00
Angel Pons 2687d37a3c payloads/external: Fix up SPDX license headers
Remove copyright notices and other unnecessary churn.

Change-Id: Ie69cc121d2b6eed95aa3cbaa7215d61880148858
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47815
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22 22:19:19 +00:00
Angel Pons 6d4de7eef9 payloads/external/Makefile.inc: Fix SeaBIOS option regressions
Commit 14ca740719 (Makefile.inc: Move adding SeaBIOS cbfs config files)
introduced various regressions that were not spotted during review.

TEST=Building with SEABIOS_THREAD_OPTIONROMS is working properly again.

Change-Id: I4de0b11747e3df8dd31a85160add129d8cc6bd8a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47814
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22 22:18:54 +00:00
Arthur Heymans 14ca740719 Makefile.inc: Move adding SeaBIOS cbfs config files
Using the INTERMEDIATE target this can be done in the proper dir.

Change-Id: Ie105231655ef4b49234f0944f638545fe79f07cb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-16 12:13:18 +00:00
Nico Huber 0748a87455 libpayload/i8042: Increase response timeout to 1.5s
The current timeout of 500ms is too low. For instance self-test
of the KBC integrated into IT8516E took almost 1s in tests. We
already check for presence of the KBC before the self-test. So
the timeout should only trigger on a hardware defect and we can
leave some margin.

Change-Id: I95f01a4e605a9c7deb894a71e102c3a881759bb1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-16 11:08:49 +00:00
Julius Werner 9c50462fd7 Delete mainboard/google/cheza
Work on this mainboard was abandoned and never finished. It's not really
usable in its current state, so let's get rid of it.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4cd2e2cd0ee69d9846472653a942fa074e2b924d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-12 01:43:09 +00:00
Thomas Heijligen e569e3e248 libpayload: storage.c: remove unneeded #if CONFIG()
Change-Id: I6e5679f66840105b3f9628071ac7aace9128107f
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-09 07:23:20 +00:00
Jacob Garber 85d93ffc0a libpayload: Make OHCI enums into types
The OHCI header file declares various enums as follows:

    enum { ... } enum_name;

Since the name is at the end, this is actually declaring a variable
called enum_name and *not* a type, which is causing a multiple
definition error in GCC 10. Move the enum_name before the opening brace
to prevent this.

Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I452c0a1b118990942aa53f1e7e77f5e8378e8975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-08 11:37:09 +00:00
Jacob Garber c98baa7a80 libpayload: Add compiler.h to compiler parameters
Headers in libpayload define various structs like so:

    struct struct_name { ... } __packed;

However, these header files do not include the compiler.h macro that
defines what __packed is, so they are actually defining a variable named
__packed and *not* declaring a packed struct. This leads to defining the
same variable multiple times, which was caught by GCC 10. Add compiler.h
to the compiler parameters so it is included in all files automatically.

Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ia67182520dc94149e06fe9e03a14b3fc2ee29973
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-08 11:37:04 +00:00
Jacob Garber 5e6c30bc42 coreinfo: Add support for link time optimization
This introduces a Kconfig option for compiling coreinfo with LTO.
This option can be used independently of LTO in libpayload, though will
benefit most if that is enabled as well. If both are enabled, the
final size of coreinfo.elf is reduced from 95 KiB to 92 KiB.

Tested in QEMU and on Thinkpad T500.

Change-Id: I6feacdb911b52b946869bff369e03dcf72897c9f
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38293
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 22:10:23 +00:00
Jacob Garber 04540f1549 libpayload: Add support for link time optimization
Link time optimization is a technique for whole-program optimization.
Instead of doing code generation during compilation, the compiler saves
its intermediate representation to the object files. During the final
linking step, it will then merge all the object files together and
perform optimizations on the entire program. This can often reduce the
final binary size, but also may increase the total compilation time.

This patch introduces a Kconfig option for enabling link time
optimization in libpayload. Since libpayload does no linking of its own,
its LTO archive files will contain only IR and no generated code.
Downstream projects will need to use LTO-aware tools when manipulating
the archives (eg. gcc-ar and gcc-nm), but otherwise do not need to use
LTO themselves -- the compiler will recognize which files are LTO and
which are not, so enabling this option should mostly be "drop in".

For example, when building coreinfo.elf using tinycurses libpayload:

		binary size	compilation time
default		114 KiB		11.49s
LTO		95 KiB		10.36s

In this case the total compilation time was actually shorter -- despite
the final linking step taking longer, this was offset by the shorter
compilation times for each individual file (since there is no code gen
until the very end).

Change-Id: I048f2ff6298ed0d891098942e1e8b29d35487b91
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38291
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 22:05:02 +00:00
Nico Huber bc2c12c728 libpayload/x86: Try to discover invariant TSC rate
We can skip the PIT-based TSC calibration if we can derive the invariant
TSC rate from CPUID/MSR data. This is necessary if the PIT is disabled,
which is the default, for instance, on Coffee Lake CPUs.

This implementation should cover all Intel Core i processors at least.
For older processors, we fall back to the PIT calibration.

Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-02 06:24:33 +00:00
Nico Huber 5c9d82bd73 libpayload/x86: Add enumeration of Intel family 6 models
The list is incomplete and only contains what we need in the follow-up
commit. It can be extended at will.

Change-Id: Ibf8ddaf510eb513ee74af3e78da46b04802a91b9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-02 06:24:10 +00:00
Tim Wawrzynczak e1a7a26f5e lib/libpayload: Replace strapping_ids with new board configuration entry
There are currently 3 different strapping ID entries in the coreboot
table, which adds overhead. The new fw_config field is also desired in
the coreboot table, which is another kind of strapping id. Therefore,
this patch deprecates the 3 current strapping ID entries (board ID, RAM
code, and SKU ID), and adds a new entry ("board_config") which provides
board ID, RAM code, SKU ID, as well as FW_CONFIG together.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1ecec847ee77b72233587c1ad7f124e2027470bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-30 15:25:28 +00:00
Patrick Georgi 6065f616eb .gitignore: Split into subdirectory files
There's no need for the global list of files to ignore, so use git's
ability to work with more local configuration.

Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 07:05:27 +00:00
Nico Huber e50f546e01 payloads/filo: Set stable tag to something that builds
Also rename the prompt to "tested" to make it more obvious that there
is no really stable version.

Change-Id: Ib719fe5c30783a53ddad2a2dc2d9ecda37a05ac2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-10-28 23:42:45 +00:00
Nico Huber d9e543a5f9 libpayload/keyboard: Use `bool` as return type
Use `bool` whenever `0` was used to indicate an error. The mixing of
different types for return values was mildly confusing and potentially
dangerous with the i8042 API close by that uses `0` for success.

Change-Id: I876bb5076c4921f36e3438f359be8ac4c09248cc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:57:47 +00:00
Nico Huber f56d65266c libpayload/curses: Use <stdbool.h>
Change-Id: I35ef7c55fc6bcfb9c51a711a8e238f0970fd4ad4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:57:21 +00:00
Nico Huber bfa46e25e0 libpayload: Add <stdbool.h>
Change-Id: I972c78c5da4136bc61e78fcbb52d7d162cc1b698
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:57:06 +00:00
Patrick Rudolph bc744f5893 drivers/smmstore: Implement SMMSTORE version 2
SMMSTORE version 2 is a complete redesign of the current driver. It is
not backwards-compatible with version 1, and only one version can be
used at a time.

Key features:
* Uses a fixed communication buffer instead of writing to arbitrary
  memory addresses provided by untrusted ring0 code.
* Gives the caller full control over the used data format.
* Splits the store into smaller chunks to allow fault tolerant updates.
* Doesn't provide feedback about the actual read/written bytes, just
  returns error or success in registers.
* Returns an error if the requested operation would overflow the
  communication buffer.

Separate the SMMSTORE into 64 KiB blocks that can individually be
read/written/erased. To be used by payloads that implement a
FaultTolerant Variable store like TianoCore.

The implementation has been tested against EDK2 master.

An example EDK2 implementation can be found here:
eb1127744a

Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-10-22 12:29:47 +00:00
Felix Singer 09917e10cb libpayload/storage/ahci: Use pci_dev struct in ahci_initialize()
Clean up ahci_initialize() by using pci_dev struct.

Change-Id: I2d5673c631d978d8ebd0c4a90962ab9cccaf40a2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20 20:39:30 +00:00
Felix Singer b4b73d4995 libpayload/storage/ahci: Use pacc pointer to read device class
The PCI bus gets already scanned while gathering system information.
Therefore, use the pacc pointer from sysinfo_t to read the device class
of PCI devices instead of rescanning the bus.

Change-Id: I4c79e71777e718f5065107ebf780ca9fdb4f1b0c
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20 20:35:47 +00:00
Felix Singer 9e5bc74cc7 libpayload/arch/x86: Introduce pacc pointer in sysinfo_t struct
Currently, the PCI bus gets scanned multiple times for various reasons
(e.g. to read the device class). Therefore, and in preparation to
CB:46416, introduce the pacc pointer in the sysinfo_t struct and scan
the PCI bus while gathering system information.

Change-Id: I496c5a3d78c7fb5d7c9f119a0c9a0314d54e729f
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20 20:35:24 +00:00
Felix Singer 6034b0f184 payloads/coreinfo: Rename pci_scan_bus()
Rename pci_scan_bus() since the name is already used in libpayload.

Change-Id: I9d4a842b77f418484e1fcf60a79723480a53e30d
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20 20:34:35 +00:00
Felix Singer e92c84050b libpayload/storage: Enable STORAGE_64BIT_LBA
32-bit LBA limits drives, that have or emulate 512B sectors, to 2TiB
capacity. Therefore, enable the 64-bit support.

Change-Id: I663029a2137c5af3c77d576fe27db0b8fa7488a9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-19 16:07:49 +00:00
Felix Singer 70d73a85bf libpayload/storage: Enable all AHCI controllers by default
Since the list of tested controllers is not actively maintained, enable
all AHCI controllers by default. Also, improve the readability of its
help text by adding a comma to it.

Change-Id: If30f58f8380ab599f8985e85c64510dc88e96268
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-19 16:07:13 +00:00
Felix Singer 4c9622a7d0 libpayload/libpci: Introduce device class attribute in pci_dev
The device class is read at different places and it is read from the
hardware directly. Therefore, and in preparation to CB:46416, introduce
the device class attribute in the pci_dev struct. With this, there is
only one interaction with the hardware and it's also more user friendly.

Change-Id: I5d56be96f3f0da471246f031ea619e3df8e54cfb
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46347
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17 16:33:55 +00:00
Felix Singer d2ec82d137 libpayload/libpci: Clean up pci_alloc()
Clean up pci_alloc() and return pointer to allocated memory directly.

Change-Id: Ib2ee8dbfaabbf7a824b4fd75ad7c779393af2900
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-17 16:33:06 +00:00
Nico Huber d32bb116f0 libpayload/x86: Add some more CPUID helpers
Change-Id: Ic88defd30c6d3791a51b78a14135aff55e89394d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-16 22:07:27 +00:00
Angel Pons e0ce60c744 lib and libpayload: Add popcnt functions
Add 32-bit `popcnt` and 64-bit `popcnt64` helpers.

Change-Id: I2e6a1007e475b662a85c067d96f81326e7f02905
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-15 19:01:51 +00:00
Tim Wawrzynczak 7ded1afe0a lib and libpayload: add 64-bit versions of clz, __ffs and log2
Add 64-bit versions of clz, __ffs & log2: `__ffs64`, `__clz64`,
and `log2_64`.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iefc6e6c51f5b20607c88e38660a499a4f77ce0d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-14 15:24:59 +00:00
Jeremy Compostella 612ae2ec7c libpayload: use PRIu64 type to print u64
The appropriate way to print a u64 variable regardless of the current
architecture is to use the PRI*64 macros.  libpayload is mostly used
in 32 bits but when ported to other projects and compiled in 64 bits
it breaks the compilation.

Change-Id: I479fd701f992701584d77d43c5cd5910f5ab7633
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-09-30 10:16:44 +00:00
Kyösti Mälkki a7a2784528 libpayload: Fix file permissions
Change-Id: Ibdc211d7f4ec0fbbefafb5eae4c1615c64c99280
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-27 13:12:33 +00:00
Zoltan Baldaszti be58923fed payloads/external: add support for BOOTBOOT payload
BOOTBOOT is a multi-platform, architecture agnostic boot protocol.
The protocol describes how to boot an ELF64 or PE32+ executable inside
an initial ram disk image into clean 64 bit mode. This version uses
libpayload to do that. Depending on the lib's configuration, initrd
can be in ROM as a cbfs file or a Flashmap partition; on disk a GPT
partition or a file on a FAT formatted ESP partition.
For more information see https://gitlab.com/bztsrc/bootboot

Change-Id: I8692cde0730338026a7760a293c1e37f66004bc0
Signed-off-by: Zoltan Baldaszti <bztemail@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-26 23:08:07 +00:00
Elyes HAOUAS 690b6bcb49 treewide/Kconfig: Drop unneeded empty lines
Change-Id: If8aa28a22625b7b2cf9b58958de87ee752f637f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21 16:30:14 +00:00
Elyes HAOUAS 3ff7bcf10e payloads: Drop unneeded empty lines
Change-Id: I6faeb7c783052edc4217d2d301dbb905e1fc6a19
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21 16:20:57 +00:00
Hsuan Ting Chen 8742e2a923 libpayload: free: Separate NULL check out for clarity
Separate the validity check of calling free(NULL) for clarity.

BUG=b:168441735
TEST=emerge-puff libpayload

Change-Id: I0dc355553410bbe59e658945fb40c05f5f709380
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-19 01:36:57 +00:00
Yu-Ping Wu 541f2f74a3 libpayload: cbgfx: Fix 'equals' counter for Lanczos resampling
The current initialization of the 'equals' counter is incorrect, so that
when 'equals >= SSZ * SSZ', the pixels in the sample array might not be
all the same, leading to a wrong pixel value being set in the
framebuffer.

The 'equals' counter stores the number of latest pixels that were
exactly equal. Within the for loop of 'ox', the sample array is updated
in a column-based order, and the 'equals' counter is updated
accordingly. However, the 'equals' counter is initialized in a row-based
order, which causes it to be set too large than it should be. Consider
the example where sample[sx][sy] are initially:

 [X X X A A A]  // sy = 0
 [X X X B B B]
 [X X X B B B]
 [X X X B B B]
 [X X X B B B]
 [X X X B B B]  // sy = SSZ

Then, the correct implementation will initialize 'equals' to be 15, with
last_equal being B. Suppose all of the remaining pixels are B. Then, at
the end of the 'while (fpfloor(ixfp) > ix)' loop when ix = 4, or
equivalently after 4 more columns of sample are updated, 'equals' will
be 15 + 6 * 4 = 39, which is greater than SSZ * SSZ = 36, but we can see
there are still 2 A's in the sample:

 [B B B B A A]
 [B B B B B B]
 [B B B B B B]
 [B B B B B B]
 [B B B B B B]
 [B B B B B B]

Therefore, we must also initialize the 'equals' counter in a
column-based order.

BUG=b:167739127
TEST=emerge-puff libpayload
TEST=Character 'k' is rendered correctly on puff
BRANCH=zork

Change-Id: Ibc91ad1af85adcf093eff40797cd54f32f57111d
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-18 01:35:35 +00:00
Jacob Garber 07201d7a0f coreinfo: Use SPDX license identifiers
- Remove copyright notices and add authors to AUTHORS
- Use SPDX license identifiers for all files
- Add coreinfo to the license header lint

Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ib0c5328a4027849b1eda4f57141a898335230726
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14 07:05:27 +00:00
Yu-Ping Wu aec3b1f7d7 libpayload: malloc: Fix realloc for overlapping buffers
The current realloc() works by freeing the origin buffer, allocating a
new one, and copying the data over. It's true that free() won't touch
the actual memory. However, the alloc() following it will potentially
modify the memory that belongs to the old buffer in order to create a
new free block (right after the newly allocated block). This causes 8
bytes (HDRSIZE) to be overwritten before being copied to the new buffer.

To fix the problem, we must create the header of the new free block
after the data is copied. In this patch, the content of alloc() is split
into two functions:

1. find_free_block(): Find a free block with large enough size, without
   touching the memory
2. use_block(): Update the header of the newly allocated block, and
   create the header of the new free block right after it

Then, inside realloc(), call memmove() call right after
find_free_block() while before use_block().

BUG=b:165439970
TEST=emerge-puff libpayload
TEST=Puff boots
TEST=Verified realloc() correctly copied data when buffers overlapped

Change-Id: I9418320a26820909144890300ddfb09ec2570f43
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-13 13:40:11 +00:00
Caveh Jalali b2280149c0 libpayload/xhci: Fix Slot State field width definition
According to the xHCI spec, the Slot State field in the Slot Context
Data Structure is 5 bits wide. So, fix the code to match.

ref. xHCI spec 1.2
section 6.2.2, Figure 6-2: Slot Context Data Structure

BUG=none
TEST=xHCI compiles

Change-Id: I0ae735af3d0840aeee846fa939c37af9aea3dff1
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45023
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-04 19:13:31 +00:00
Caveh Jalali d7468bfb27 xhci: Do not set the CRCR_CS bit
We do not need to set the CS (Command Stop) bit in the Command Ring
Control Register. CS is implied by CA (Command Abort). I'm not sure if
there is a defined execution order for these command bits, so it's
safer to only use the CA bit as it includes the CS function.

Ref: xHCI spec 1.2 (May 2019), Section 5.4.5, Table 5-24.

BUG=b:160354585,b:157123390
TEST=able to boot into recovery using USB stick on servo v2 on volteer
	as well as HooToo 8-1 hub

Change-Id: Iaeba98b6da8da49f529358ca6d68270440ea0f42
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-31 06:38:53 +00:00
Caveh Jalali 551216a4d1 xhci: Fix Abort command event handling
This fixes issues with how we handle events generated by the xHCI
"command abort" command. first, depending on the state of the xHCI
controller, the COMMAND_ABORTED may not be generated. If the
controller was between commands, only the COMMAND_RING_STOPPED event
will be generated. Second, do not adjust the command ring "cur"
pointer as that just confuses the controller.

BUG=b:160354585,b:157123390
TEST=able to boot into recovery using USB stick on servo v2 on volteer
	as well as HooToo 8-1 hub

Change-Id: I055df680d1797f35d9730e2bfdb4119925657168
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-31 06:38:47 +00:00
Hung-Te Lin d04b388381 libpayload: cbgfx: Support buffered I/O
For payloads with UI based on CBGFX, they usually start by calling
clear_canvas or clear_screen and then draw the UI elements. However,
that makes the screen flicker.

A typical solution is to identify and minimize the area to redraw.
However for payloads with complicated UI and do not care about latency,
an alternative is to enable buffered I/O.

The new enable_graphics_buffer() will redirect all graphics I/O
into an invisible working buffer. To flush (redraw) the buffer to the
real screen, call flush_graphics_buffer(). To stop buffering, call
disable_graphics_buffer().

BUG=None
TEST=Add the enable, flush and disable calls to payload 'depthcharge',
     built a firmware and boots into Chrome OS recover UI. No more
     flickering. The average rendering time on x86 platform is 1.2ms.

Change-Id: Id60a2824fd9e164feae16b92b68b003beabea8d3
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44654
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 21:40:58 +00:00
Julius Werner ae096be00c libpayload: memmove: Don't make expectations of architecture memcpy
default_memmove() calls memcpy() when (src > dst). This is safe for the
default_memcpy() implementation, but just calling memcpy() may invoke an
architecture-specific implementation. Architectures are free to
implement memcpy() however they want and may assume that buffers don't
overlap in either direction. So while this happens to work for all
current architecture implementations of memcpy(), it's safer not to rely
on that and only rely on the known implementation of default_memcpy()
for the forwards-overlapping case.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I7ece4ce9e6622a36612bfade3deb62f351877789
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24 09:24:06 +00:00
Nico Huber 4a7325228f libpayload: Cache physical location of strings
In the presence of self-relocating payloads, it's safer to keep
physical addresses in `libsysinfo`. This updates the remaining
pointers that are not consumed by libpayload code, all of them
strings.

Also update the comment that `libsysinfo` only containts physical
addresses.

Change-Id: I9d095c826b00d621201c34b329fb9b5beb1ec794
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24 09:13:35 +00:00
Nico Huber bea01e32b2 libpayload: Cache physical location of CBMEM entries
In the presence of self-relocating payloads, it's safer to keep
physical addresses in `libsysinfo`. This updates all the references
to CBMEM entries that are not consumed inside libpayload code.

Change-Id: I3be64c8be8b46d00b457eafd7f80a8ed8e604030
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-24 09:13:30 +00:00
Nico Huber 12faea3095 libpayload: Cache physical location of cb_table entries
In the presence of self-relocating payloads, it's safer to keep
physical addresses in `libsysinfo`. This updates all the references
to coreboot-table entries that are not consumed inside libpayload
code.

Change-Id: I95cb0af151e0707a1656deacddb8a5253ea38fc3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24 09:13:23 +00:00
Nico Huber 5e0db58533 libpayload: Cache copy of `cb_framebuffer` struct
Our AArch64 code supports dynamic framebuffer allocation which
makes it necessary to change the framebuffer information during
runtime. Having a pointer inside `libsysinfo` made a mess of it
as the pointer would either refer to the original struct inside
the coreboot table or to a new struct inside payload space. The
latter would be unaffected by a relocation of the payload.

Instead of the pointer, we'll always keep a copy of the whole
struct, which can be altered on demand without affecting the
coreboot table. To align the `video/graphics` driver with the
console driver, we also replace `fbaddr` with a macro `FB` that
calls phys_to_virt().

Change-Id: I3edc09cdb502a71516c1ee71457c1f8dcd01c119
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24 09:13:16 +00:00
Nico Huber be842cb72d libpayload: Cache physical location of serial-console struct
In the presence of self-relocating payloads, it's safer to keep
physical addresses in `libsysinfo`.

Change-Id: Icd30e95c6b8115d16dd793914fb01a1a9da1854f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24 09:13:09 +00:00
Nico Huber b2eafa666c libpayload: Cache physical CMOS option table location
In the presence of self-relocating payloads, it's safer to keep
physical addresses in `libsysinfo`.

Change-Id: I64a37bef263022edb504086c02a3fd22ce068ba4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-24 09:12:56 +00:00
Nico Huber 14adb7eaa9 libpayload: Cache physical cbmem console address
Same as with other consoles and drivers that cache an address
outside the payload (e.g. video/corebootfb), we should store the
physical address, so we can derive the virtual address on demand.
This makes it save to use the address across relocations.

As a first step in migrating `libsysinfo` to `uintptr_t`, we
also switch to the physical address there.

Fixes the default build of FILO, tested with Qemu/i440FX and Qemu/Q35.

Change-Id: I4b8434af69e0526f78523ae61981a15abb1295b0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-24 09:12:47 +00:00
Sam Lewis cb287987a1 arch/arm: Enable FIT payloads
Implements fit_payload_arch for the arm (aarch32) architecture, so that
FIT images can be used. The implementation is very similar to the
existing implementations for arm64 and riscv, and has mostly been
lifted from these other ports.

TEST: Booted Beaglebone Black (in progress port, to be submitted soon!)
with a FIT image containing a 5.4 kernel, dtb and initramfs.

Change-Id: I6b50c6f06b83c00a5b3622b5bbafe67130b6d233
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-19 07:16:59 +00:00
Nico Huber 31206c7156 payloads/nvramcui: Fix `make clean`
After `make clean` a new build should not be based on stale artifacts.
Hence we have to remove them.

Change-Id: I540a83a6c87b843b1c4c9c55990bf3e91fe90d79
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-18 10:24:01 +00:00
Nico Huber 3bc42efb45 payloads/coreinfo: Fix `make clean`
After `make clean` a new build should not be based on stale artifacts.
Hence we have to remove them.

Change-Id: I18292c674986078d991668124193b6aa31234d47
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-18 10:23:55 +00:00
Elyes HAOUAS ac66bda47c payloads/seabios: Update stable version to 1.14.0
see https://seabios.org/Releases

Change-Id: I20e57314b867581f41921178ff1ffcbaa50a0843
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2020-08-17 06:37:57 +00:00
Nico Huber 363cd1d886 libpayload/defconfig: Set default heap size to 1MiB
libpayload's drivers keep growing. With certain hardware/payload
combinations (last time witnessed with Kontron/bSL6 and FILO), the
default configuration runs out of memory.

As there is a lot enabled by default, also set a big default heap size.

Tested with FILO on QEMU/Q35.

Change-Id: I51a1514097aeb8b3c835a2387db66869b81d0bcc
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-08-17 06:10:49 +00:00
Yu-Ping Wu 7b54c15a67 libpayload: cbgfx: Add color mapping functionality
Similar to set_blend(), add set_color_map() for mapping background and
foreground colors of a bitmap. Also add clear_color_map() for clearing
the saved color mappings.

Note that when drawing a bitmap, the color mapping will be applied
before blending.

Also remove unnecessary initialization for static variable 'blend'.

BRANCH=puff
BUG=b:146399181, b:162357639
TEST=emerge-puff libpayload

Change-Id: I640ff3e8455cd4aaa5a41d03a0183dff282648a5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-13 22:25:18 +00:00
Patrick Georgi ae010c619f libpayload: Replace include/compiler.h with commonlib/bsd's version
This ensures that it's available under BSD license terms.

Change-Id: Ica13014b847473fee02516be0b27684c6cfb07bc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43964
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28 16:16:21 +00:00
Elyes HAOUAS c354599a53 payloads/libpayload/drivers/usb/usb.c: Remove whitespace before tab
Change-Id: Iba73ae4d89cef94f238e9a74300f6088669f355b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25 01:25:25 +00:00
Elyes HAOUAS 81bebc8374 payloads/libpayload/curses/menu/eti.h: Remove unneeded whitespaces
Change-Id: Ia77c5be4b22740f88fb9c11bff95036adbd8145f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25 01:25:16 +00:00
Elyes HAOUAS beaf9443aa payloads/libpayload/arch/arm/cpu.S: Remove whitespaces before tab
Change-Id: I2960f95937db23aa3a38ca64085728e6d10968f8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25 01:25:00 +00:00
Elyes HAOUAS e4d31061d7 payloads/external/tint/Makefile: Remove whitespaces before tab
Change-Id: Ie08e92778e029b962cf0ed5f95ab740458e82fc5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25 01:24:51 +00:00
Yu-Ping Wu b086728094 libpayload: cbgfx: Add draw_line()
Add a function draw_line() to draw either a horizontal or vertical line
segment.

Theoretically a horizontal line can also be drawn by calling
draw_rounded_box() with dim_rel.x being the line length and dim_rel.y
being the line width. However, due to the truncation in integer division
when converting relative coordinates to absolute ones, this will
potentially produce inconsistent line widths, depending on the value of
pos_rel.y.

It is guaranteed that draw_line() will produce consistent line widths,
regardless of the position of the line. Also, when the thickness
argument is zero, this function is able to draw a line with 1-pixel
width, which is not achievable by draw_rounded_box().

BRANCH=puff
BUG=b:146399181, b:161424726
TEST=emerge-puff libpayload

Change-Id: I2d50414c4bfed343516197da9bb50791c89ba4c2
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
2020-07-23 05:09:31 +00:00
Nico Huber 3c7888bf29 libpayload/xhci: Try harder to read 32-bit caps at once
With commit 287cf6c7d1 (lp/drivers/usb: Work around QEMU XHCI
register issue) we restructured our capability register accesses
because the compiler used the wrong access size. While we do use
only 32-bit types now, a compiler may still try to be clever and
optimize things in unexpected ways. So we add an explicit read32()
now.

For instance for the 8-bit MaxPorts field, in the most significant
bits of `capreg + 4`, our read + mask + shift

    ((cap)->hciparams1 & 0xff000000) >> 24

was turned into a single 8-bit read instruction by GCC on x86:

      31:   0f b6 52 07             movzbl 0x7(%edx),%edx

Change-Id: I76accd0ef718e70ca46807eb06a9177c3afd99f1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-21 15:14:48 +00:00
Ronald G Minnich a92a07d9c0 libpayload: allow nonblocking delay and more than one delay
Extend the local APIC timer delay so that it can be started,
and waited for, independently.

Add an EOI so that more than one APIC timer interrupt is possible.
Previous to this, because there was no EOI, the first timer
interrupt the CPU took was also the last it would take --
apic_delay would only work one time.

Change-Id: Ib11aeee5b7da81287166ac68fc327e7ae62d1b84
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-16 16:48:42 +00:00
Shelley Chen 31a3788739 cbgfx: Add blend functions to calculate transparency
Up until now we have no way of adding transparency into our firmware
screens.  Add set_blend() and clear_blend() functions to store alpha
value and rgb values to calculate alpha blending in
calculate_colors().

BUG=b:144969091,b:160839199
BRANCH=puff
TEST=dut-control power_state:rec
     press ctrl-d
     Ensure background is dimmed when dialog pops up

Change-Id: I95468f27836d34ab80392727d726a69c09dc168e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-15 20:23:07 +00:00
Michael Niewöhner 91323593f3 payloads/depthcharge: Makefile: resolve fail of concurrent build
Resolve missing dependency to fix concurrent building.

Resolves: https://ticket.coreboot.org/issues/271
Change-Id: Idbd9155e01fcc4571a61f1bba5b2b4a446036da0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-15 10:33:13 +00:00
Selma BENSAID a3a8ff97fb payloads/external: fix depthcharge build from source
Signed-off-by: Selma BENSAID <selma.bensaid@intel.com>
Change-Id: I17ae7450a9641268fe392bed0f24846abc8e6f56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43203
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12 19:41:24 +00:00
Benjamin Doron e51f030e62 payloads/tianocore: Don't recurse submodules
Upstream does not require it. From the repository readme:

"Note: When cloning submodule repos, '--recursive' option is not recommended.
EDK II itself will not use any code/feature from submodules in above submodules.
So using '--recursive' adds a dependency on being able to reach servers we do not
actually want any code from, as well as needlessly downloading code we will not use."

Change-Id: I0c5d6dd6e5070720870fc22b2476c6fe8dc7fd40
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-07-12 19:29:04 +00:00
Julius Werner 7f87812c30 libpayload: cbgfx: Replace bilinear resampling with Lanczos
This patch improves the image resampling (scaling) code in CBGFX to use
the Lanczos algorithm that is widely considered the "best" resampling
algorithm (e.g. also the first choice in Python's PIL library). It is of
course much more elaborate and therefore slower than bilinear
resampling, but a lot of the difference can be made up with
optimizations, and the resulting code was found to still produce
acceptable speeds for existing Chrome OS UI use cases (on an Arm
Cortex-A55 device, time to scale an image to 1101x593 went from ~88ms to
~275ms, a little over 3x slowdown). Nevertheless, if this should be too
slow for anyone there's also an option to tune it down a little, but
still much better than bilinear (same operation was ~170ms with this).

Example images (scaled up by a factor of 7):
Old (bilinear): https://i.imgur.com/ytr2n4Z.png
New (Lanczos a=3): https://i.imgur.com/f0vKluM.png

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Idde6f61865bfac2801ee4fff40ac64e4ebddff1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-07-09 00:32:17 +00:00
Julius Werner 96b00a50f1 libpayload: Add simple 32.32 fixed-point math API
struct fraction is slooooooooooow. This patch adds a simple 64-bit
(32-bits integral, 32-bits fractional) fixed-point math API that is
*much* faster (observed roughly 5x speed-up) when doing intensive
graphics operations. It is optimized for speed over accuracy so some
operations may lose a bit more precision than expected, but overall it's
still plenty of bits for most use cases.

Also includes support for basic trigonometric functions with a small
lookup table.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Id0f9c23980e36ce0ac0b7c5cd0bc66153bca1fd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-07-09 00:32:11 +00:00
Michael Walle 32b13131c1 libpayload: arm64: silence libpayload main entry
No other architecture in libpayload outputs anything in the main entry
routine. Let alone an exception test which looks like a real exception
to the normal user and is most likely really misleading. Silence the
startup code.

Change-Id: I6e49f24ad46ce578a4bb111c2d623ca4470a1866
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43126
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 07:25:38 +00:00
Michael Walle 492d55fa46 libpayload: arm64: fix OUTPUT_ARCH()
There is no bfd "arm64". The correct bfdname is "aarch64". Fix it. With
this change libpayload will build with the AArch64 GCC.

Change-Id: If7a6b14691107c5d4fc67c3cd3990ecc849d4af1
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-08 07:25:03 +00:00
Julius Werner 63358eaff6 libpayload: cbgfx: Fix add_fractions() overflow reduction
log2(1) is 0 and log2(0) is -1. If we have the int64_t 0xffffffff then
log2(0xffffffff >> 31) = log2(0x1) = 0, so the current reduction code
would not shift. That's a bad idea, though, since 0xffffffff when
interpreted as an int32_t would become a negative number.

We need to always shift one more than the current code does to get a
safe reduction. This also means we can get rid of another compare/branch
since -1 is the smallest result log2() can return, so the shift can no
longer go negative now.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib1eb6364c35c26924804261c02171139cdbd1034
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-06 06:14:57 +00:00
Yu-Ping Wu 373ae2e734 libpayload/cbgfx: Fix overflow in transform_vector()
Fix potential overflow when multiplying integers in transform_vector().
This issue is causing the absolute coordinate of the bottom right corner
of the box to be incorrectly calculated for draw_rounded_box(), which is
used in menu UI to clear the previous screen.

In addition, check the lower bound in within_box().

BRANCH=none
BUG=b:146399181, b:159772149
TEST=emerge-puff libpayload
TEST=Previous screen is cleared properly for menu UI

Change-Id: I57845f54e18e5bdbd0d774209ee9632cb860b0c2
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42770
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-28 21:52:18 +00:00
Yu-Ping Wu 59495543db libpayload: gdb: Condition video console init on LP_VIDEO_CONSOLE
With the stub video_console_init() removed from depthcharge in
CL:2241493, depthcharge will fail to compile:

 payloads/libpayload/gdb/stub.c:76: undefined reference to
 `video_console_init'

Since video_console_init() is meant to be implemented in
libpayload, libpayload should be consistent with itself by not calling
this function when it's not implemented (i.e., when !LP_VIDEO_CONSOLE).

Therefore, initialize video console only if LP_VIDEO_CONSOLE is set.

BRANCH=none
BUG=none
TEST=USE="menu_ui" emerge-gale depthcharge

Change-Id: Ic45f9073330258cb77301003484ec525b2404180
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42505
Reviewed-by: Joel Kitching <kitching@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22 12:24:42 +00:00
Angel Pons fa276862f2 payloads/external: s/PROMT/PROMPT/g
Change-Id: Id305d9edecac9e9cd305301e9dc5af6678ef7528
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-06 20:26:35 +00:00
Caveh Jalali 96f231ac4b usb/xhci: Fix timeout logic
This fixes a logic bug in how timeouts are reported back. In the
timeout case, the original code would return -1 instead of 0. All call
sites expect a return value of 0 as the timeout indicator.

Signed-off-by: Caveh Jalali <caveh@chromium.org>
Change-Id: I81a888aa0a1544e55e6a680be8f3b7f6e0d87812
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-06 09:26:02 +00:00