Commit Graph

4939 Commits

Author SHA1 Message Date
Felix Singer fa41fef557 util/docker/jenkins-node: Allow pip to install packages system-wide
Call pip3 with `--break-system-packages` allowing it to install packages
system-wide. This fixes building the Docker container.

Change-Id: Id093f2c69fec43556c434fbca7b36095a7e6bd97
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-04-25 05:36:03 +00:00
Felix Singer 98d7157a6d util/docker/jenkins-node: Merge package installations into first step
It's not necessary to have multiple steps for installing packages and
requirements. Just merge the two install steps to one.

Change-Id: Ibe620e5b20a5f1a5d4e1c4c98942c136f450f280
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74245
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-04-25 05:35:57 +00:00
Kyösti Mälkki a9dd3c3fae lib/version: Move board identification strings
These strings are now only expanded in lib/identity.c.

This improves ccache hit rates slightly, as one built object file
lib/version.o is used for all variants of a board. Also one built
object file lib/identity.o can become a ccache hit for successive
builds of a variant, while the commit hash changes.

Change-Id: Ia7d5454d95c8698ab1c1744e63ea4c04d615bb3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-22 16:20:49 +00:00
Karol Zmyslowski b2f5a22c4a util/inteltool: Add support for Jasper Lake
Tested on: Intel N5105 (Jasperlake Family, Intel Celeron processor)
Based on Intel Pentium Silver and Intel Celeron Processor Datasheet,
        vol. 2 of 2 revision 001 (DOC# 634545)

Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d
Signed-off-by: Karol Zmyslowski <karol.zmyslowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-04-21 15:22:21 +00:00
Elyes Haouas b68817d196 crossgcc: Upgrade CMake from version 3.26.2 to 3.26.3
Change-Id: Iab8d67632f97c596baa9b430228d4aae6fa48126
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-04-17 23:43:12 +00:00
Bill XIE cd3545556e util/cbfstool: Qualify struct e820entry as packed
In order to accord with grub (see include/grub/i386/linux.h) and
comments for offsets of members of struct linux_params,
struct e820entry should be defined as __packed, otherwise,
sizeof(struct linux_params) will become 4224 (0x1080).

Fortunately, the affected area is usually not occupied.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I09955c90e4eec337adca383e628a8821075381d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-04-16 14:04:32 +00:00
YH Lin d76beb8129 mb/google/rex: add variant gpio tables for variant creation
BUG=b:276818954
TEST=new_variant_fulltest.sh rex0
BRANCH=None

Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: Iebc098f8d480ac3e1835b00861fd844d97f281a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-13 17:40:26 +00:00
Julius Werner ea4d4c9c33 cbfstool: Add comment to define stability rules for cbfstool print -k
In CB:41119, I sort of made up a mechanism on the fly for how to make
the machine-parseable cbfstool print output extensible without breaking
backwards compatibility for older scripts. But I only explained it in
the commit message which is not very visible. This patch adds a comment
to the function that generates that output so that people who want to
change it can understand the intent.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I0d18d59e7fe407eb34710d6a583cfae667723eb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-04-13 00:43:23 +00:00
Arthur Heymans e84b095d3a util/sconfig: Remove unused ioapic and irq keywords
Ioapic information in the devicetree was only used to set up mptables
but this generic driver was removed (ca5a793 drivers/generic/ioapic:
Drop poor implementation).

This removes the unused remainders from mainboard devicetrees.
Remove ioapic setup from sconfig.

Change-Id: Ib3fef0bf923ab3f02f3aeed2e55cf662a3dc3a1b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-11 16:23:28 +00:00
Elyes Haouas af93336da3 ec/lenovo/pmh7/chip.h: Use 'bool' instead of 'int'
This to fix following error using Clang-16.0.0:
/cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:135:22: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
        .backlight_enable = 0x01,
                            ^~~~
/cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:136:23: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
        .dock_event_enable = 0x01,
                             ^~~~

Change-Id: Icd35224877fee355e1bbb8a8e838cb047604babb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-08 03:36:07 +00:00
Arthur Heymans fd4e676bb3 Revert "cbfstool/default-x86.fmd: Rename BIOS -> SI_BIOS"
This reverts commit 89b4f69746.

SI_BIOS is mostly used to indicate the BIOS region in Intel IFD. Not all
platforms are Intel platforms with an IFD, so revert this change. Also
tooling often depends on names not changing so renaming things should
not be done lightly. The default region should also be in sync with
non-x86 and made systematic across the tree.

Change-Id: I46f52494498295ba5e2a23d0b66b56f266293050
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74290
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-04-07 15:14:04 +00:00
Felix Singer 74b4bd0e92 tree: Replace `egrep` with `grep -E`
For compatibility reasons, egrep is just a wrapper around grep today.
Thus, replace it with `grep -E`.

Change-Id: Ief08a22e4cd7211a3fee278492c95d37f9e058fa
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-06 19:54:44 +00:00
Arthur Heymans 5196aacb98 util/lint/stable-017: Update full config pattern matching
CONFIG_ARCH gives false positives for CONFIG_ARCH_X86_64_PGTBL_LOC so
use a different string: 'CONFIG_MAINBOARD_DIR'.

Change-Id: Ie5d4fc4693bc303afb16884c53c9ca4d1778a5cb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74220
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-06 15:11:44 +00:00
Karthikeyan Ramasubramanian 9e45e32420 util/spd_tools: Add support for Phoenix platform
Update spd_gen and part_id_gen utilities to accommodate Phoenix platform
so that SPD can be generated for the memory parts used in that platform.
SPD requirements for Phoenix and Mendocino platforms are identical.

BUG=b:273383819
TEST=Run spd_gen and ensure that both Mendocino and Phoenix platforms
share the platform manifest for LP5 memory parts.

Change-Id: I7a12f73065864f08db8922c1a69eb503865a25b1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-04-05 10:01:15 +00:00
Felix Singer 3a5507fd31 util/crossgcc/buildgcc: Allow bootstrapping CMake with multiple threads
The main build process already runs multi-threaded, when requested.
Apply the same setting to the bootstrap / configure step.

Change-Id: I89d6728a0985946b702f83770bedf767afb12690
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74156
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-03 13:22:21 +00:00
Elyes Haouas 3453c313ac crossgcc: Upgrade CMake from version 3.25.2 to 3.26.2
Change-Id: I62078257fd84a64c699a7f930bc306e38d2f4058
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73791
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-02 02:28:09 +00:00
Felix Singer 0686c69802 util/crossgcc: Update binutils from 2.37 to 2.40
Change-Id: I34a20a999f7ea624c1add4750fcd116166953dd8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-04-01 20:17:39 +00:00
Felix Singer 0fb774024d util/docker/coreboot-sdk: Remove Python 2 package
Debian removed Python 2 from their Sid repository and so it needs to be
removed from the Dockerfile as well.

Built and tested the Dockerfile with Python 2 removed. Still works.

Change-Id: If4e298dc275c1dfaf57cd4c3f8e5f89410318ec0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-01 11:01:07 +00:00
Maximilian Brune 60c6a5a6fe util/cbfstool: Add usage information about verbose output
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ica512d21d1cef8ccffbc093016c7a3bfcf901b14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73488
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-28 13:28:15 +00:00
Maximilian Brune 89b4f69746 cbfstool/default-x86.fmd: Rename BIOS -> SI_BIOS
Currently ifdtool --validate will not correctly validate the FMAP
against the IFD regions, since it will compare the IFD bios region with
an FMAP region called SI_BIOS.

It's probably a good idea to define default name for the BIOS FMAP
region like we have for 'COREBOOT' or 'FMAP' FMAP region.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I55eddfb5641b3011d4525893604ccf87fa05a1e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-28 13:27:57 +00:00
Maximilian Brune 347596ae6e util/ifdtool: Add option to create FMAP template
On systems that do not provide their own *.fmd (Flashmap) file, we
fall back to a default flashmap file. That file however does not contain
the blobs (ME, GBE ...), that are usually placed below the BIOS Flashmap.
It can therefore easily happen that the placement of the blobs collides
with the placement of the BIOS region (e.g. if CBFS_SIZE is big enough).
The fmaptool can't catch that, since it does not know of the blobs
placement.

This patch basically maps the regions described in the IFD (Intel
Firmware Descriptor) to the default Flashmap.

Test: Build and see that build/fmap.fmd contains all blobs now (on intel
systems that are supported by the ifdtool)

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I82cb252fff456773af69943e188480a4998736fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-28 13:27:50 +00:00
Zheng Bao 8dd34bd674 amdfwtool: Clean up table buffers before combo loop
Keep clean copies of PSP and BIOS table. Refresh the working tables
before they are filled with file names and other information at each
iteration.

Change-Id: Ie8339a4d66c38e02180cbf99e13914bfff66dc0f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-24 14:07:21 +00:00
Zheng Bao e3ebc4fe31 amdfwtool: Add missing help information for --combo-config1
Change-Id: I6b69965991daadaf8b4148b06d0715b087021c9b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-24 14:05:49 +00:00
Zheng Bao c25d5935d3 amdfwtool: Call wrapper funtion to write file
Don't call system call directly.

Change-Id: I6da31723bc2bfc1197fc31962053671c84ccc397
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-24 14:05:27 +00:00
Zheng Bao f080cd5463 amdfwtool: Move some funtions to other categorized source files
To reduce the size of amdfwtool.c which is already too big.

Change-Id: Ib80eeb42f59a3dda04402b2feaadc1d178ed989e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-24 14:04:31 +00:00
Felix Held c5c7fa494b util/amdfwtool: remove unused union from embedded_firmware struct
Since commit 2f6b7d557d ("amdfwtool: Move the filling of table headers
into functions"), the combo_psp_directory union element in the
embedded_firmware is unused and the new_psp_directory element is used in
all places, so replace the union of new_psp_directory and
combo_psp_directory with just the new_psp_directory struct element.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I35d339b3084ec8f93210095c233f5e68296d0013
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-21 18:02:47 +00:00
Felix Singer 0e2fc554a7 util/liveiso: Move NixOS configs to subdirectory
Move the NixOS configuration into a subdirectory so that configurations
for other distros can be added as well.

Change-Id: I0462c1a6541878c973be4302c5c5e9e9bfaed2a6
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-03-17 19:27:31 +00:00
Zheng Bao 3e7008df95 amdfwtool: Print which combo entry is being processed
Change-Id: I9e83a3ac56d5c42d8d6839cc4d961adf0b656fb5
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73725
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-16 14:58:49 +00:00
Zheng Bao a7731cc0c9 amdfwtool: Remove meaningless double parentheses
Change-Id: I4a9192c55d63531621dd7bc49f1ead7f58dff893
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73648
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-16 14:40:16 +00:00
Zheng Bao 17551ae865 amdfwtool: Check combo_index before checking the combo_config
Otherwise Checking combo_config[++combo_index] causes Out-of-Bounds
access.

Change-Id: I50d466ee98edfb18c01fc7ba43e929640b33c7c1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73647
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-16 14:40:02 +00:00
Zheng Bao 7391722c40 amdfwtool: Add asserting before accessing array combo_config
Change-Id: Ia98fdbee4c4005562662313ebe2478d0aeb879bc
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73724
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-16 14:39:41 +00:00
Martin Roth 6bb6ed9467 util/amdfwtool: Update config parser to accept full paths
This allows individual components to be placed in a location other than
what is specified by the FIRMWARE_LOCATION line.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3a83e52d081a5909d54eacc575dd2b40b09e4038
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-03-15 19:35:54 +00:00
Karthikeyan Ramasubramanian 8d88561235 util/amdfwtool: Support not passing recovery/backup APCB
If Recovery/Backup APCB is not passed, then AMD_BIOS_APCB_BK entry is
not populated. But PSP expects that bios directory entry to be
populated. Also on mainboards where both APCB and recovery APCB are same
(eg. Skyrim), 2 copies of the same APCB are added to amdfw*.rom. Update
amdfwtool to support not passing recovery/backup APCB. If the recovery
APCB is not passed, then populate AMD_BIOS_APCB_BK entry and make it
point to the same offset as AMD_BIOS_APCB entry.

BUG=b:240696002
TEST=Build and boot to OS in Skyrim. Ensure that the device can enter
recovery mode. Perform multiple suspend/resume cycles.

Change-Id: I031ba817573cd35160f5e219b1b373ddce69aa6b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73661
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15 17:30:15 +00:00
Karthikeyan Ramasubramanian 225b4b3279 amdfwtool: Remove the initial alignment on newer SoCs
On newer SoCs the initial alignment is not required. So skip initial
alignment. This saves 64 KiB flash space on each firmware slots. This
also saves ~5 ms while loading amdfw.rom

BUG=b:240696002
TEST=Build and boot to OS in Skyrim.

Change-Id: I27cbfde2d7d58b62a4c0039c60babc3fb3bd95fa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73654
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-15 17:30:12 +00:00
Fabian Groffen 6e04d8570f util/inteltool: Fix build on musl-libc systems
use __linux__ instead of __GLIBC__ guard for Linux-specific includes

Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: Ifbf4552591c0df7811c5b37a9207c0901b6fd68f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73666
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-12 11:42:48 +00:00
Fabian Groffen 318ddb8aab util/superiotool: Fix build on musl-libc systems
- use __linux__ instead of __GLIBC__ guard for Linux-specific includes
- use POSIX ioperm instead of deprecated iopl

Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: I99613007aa9feddcb1041f31085cdeb195ff7a68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-12 11:42:38 +00:00
Zheng Bao 994ff52464 amdfwtool: Remove the option --list which nobody uses
It was used for printing the dependencies which is now taken by macro
DEP_FILES in soc/amd/common/Makefile.inc.

TEST=binary identical test on google/guybrush amd/chausie

Change-Id: I1b86df2cb2ed178cf0a263c50ccb3e2254a3852b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73627
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-10 16:14:12 +00:00
Zheng Bao 4b6aa195b4 amdfwtool: Move PSP FWs padding into a loop for combo
Move main body of PSP padding into a loop which can add a new combo
entry. In the loop, get the FW files from each fw.cfg, create new pack
of PSP, and fill the combo header. Currently Feature COMBO is still
not fully functional. But the non-combo case will not be affected for
sure.

The real changes are
1. Add a do-while loop.
2. Remove a "TODO" comment.
All other changes are re-indenting and re-filling.

Change-Id: I351192a4bc5ed9ec0bfa3f2073c9633b8b44246d
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58554
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-10 16:12:45 +00:00
Zheng Bao 0e3d18b130 amdfwtool: Add combo index and combo config table
For now, combo index is 0, and only the first entry in config table is
used. The index will grow when there are more combo entries.

Add a command parameter to give fw.cfg for combo index 1. Process the
combo config in the future loop.

Change-Id: I00609d91defc08e17f937ac8339575f84b1bd37c
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-10 13:41:16 +00:00
Zheng Bao 39cae56c41 amdfwtool: Add a wrapper function to open and process config file
And move the additional processing to this new function.

Change-Id: Id101d63e4d30a6e57ac1aa79665a4ba22b2956f1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73509
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-10 13:40:21 +00:00
Zheng Bao 9bb62cb364 amdfwtool: Add HW IPCFG file whose subprog is 1
And rename PSP_HW_IPCFG_FILE to PSP_HW_IPCFG_FILE_SUB0

Change-Id: Ia1ab8482074105de367905be2b4b0418066823d2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-10 13:39:23 +00:00
Karthikeyan Ramasubramanian bd9dd420d7 util/amdfwtool: Add option to indicate uncompressed BIOS binary
amdfwtool always assumes that the PSP BIOS binary (type 0x62 BIOS
directory entry) is always compressed. On boards using vboot, sometimes
PSP BIOS binary is uncompressed - specifically when CBFS verification is
enabled and verified boot starts in bootblock. Add an option to indicate
PSP BIOS binary is uncompressed.

BUG=b:261792282
TEST=Build Skyrim BIOS with x86 verstage and CBFS Verification enabled.
Boot to OS.

Change-Id: I4d56c0ba451b194043ebb5cdb0f2b27482beef1f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-03-09 21:41:31 +00:00
Maximilian Brune ab0e680c8e util/ifdtool/ifdtool.c: Clean up
- Remove functions that are only called in one place.
- Add warning if user doesn't supply a platform, since that can lead to
  dumps/layouts that do not include all IFD regions without the user
  even reliazing it.
- Inform the User if IFD or Flashmap is not found.
- Inform the User if there is not a single match between FMAP and IFD
  region
- Avoid printing usage if not specifically asked by the user.
  It tends to obfuscate the original error message.
- Keep indentation consistent throughout the file.
- Remove typedefs (coreboot coding style)

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7bbce63ecb2e920530394766f58b5ea6f72852e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-09 19:36:32 +00:00
Nikolai Vyssotski bfc9ca7f55 amdfwtool: move FW_MPIO to PSP Dir Level 2 where it belongs
Type 0x5d (MPIO Firmware) was mistakenly placed to PSP Level 1 directory.
It should be in Level 2 PSP directory instead.

Change-Id: Ic5ea00859f1055e0c91600c5f941c5d3acca36e2
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-09 15:20:18 +00:00
Fred Reitberger 75191be8d4 amdfwtool: Support multiple inst entries
Use the inst field when adding entries to the psp tables. Otherwise,
entries that differ by the inst field will appear as duplicates with an
inst of 0.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I4a84a0730976f4c65902b5c24ed13e21e95b03bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-09 12:19:44 +00:00
Zheng Bao 84fb9eac96 amdfwtool: combo: Add combo feature for BIOS table
It is similar to PSP combo.

Change-Id: If0523a4a0e1f31969e4bbaa6062dcc0f2d6da420
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08 12:59:50 +00:00
Zheng Bao 35cdffd6ea amdfwtool: Separate two cases of combo and non-combo clearly
If combo is used, fill the EFS header with address of COMBO header.
If not, fill with address of PSP header.

The old code fills with PSP headers all the time.

Change-Id: I0057165aea553d9dc8e4e719e2804557229a0002
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66855
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-08 12:56:37 +00:00
Zheng Bao b2ae6a5a3a amdfwtool: combo: Create the combo header earlier
There will be a loop to set up the combo layout. The combo header only
needs to be created once. This change is actually to move the creation
of combo header outside of the loop.

Change-Id: If6ba3d10dfc598133b9adbbb2b6658f356455608
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66854
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-08 12:55:15 +00:00
Zheng Bao 2f6b7d557d amdfwtool: Move the filling of table headers into functions
It is easier to understand what these statements are about.

Change-Id: Ib02c68c9f2ea84020b12682c41fb1a6f8f93d725
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66852
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-08 12:49:07 +00:00
Martin Roth 57f1162363 util/lint: Ignore braces around single line statements
In a recent coreboot leadership meeting, the decision was made to allow
(but not require) braces around single line statements if the author
wishes to put them in.

This patch removes the checks for single line statement blocks, while
still checking for other issues in braces.

Just because they're allowed now, please do not reformat the entire
codebase to add them. coreboot has a policy of not making widespread
changes to the entire codebase unless something actually violates the
style guidelines.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I137b10889ec880959c4c1b035dc54bf8ebf32488
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73515
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-07 21:34:11 +00:00
Maximilian Brune b3a7c64532 lint/lint-stable-003-whitespace: Fix excludelist
Remove the last slash '/' from directories in excludelist, so that they
will be correctly filtered by grep.

Fixes:
grep: util/goswid: Is a directory
grep: util/nvidia/cbootimage: Is a directory

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I90cc2cff9a98bbd0af344156332b970bfd6430b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-03-04 19:38:30 +00:00
Zheng Bao cd25ca09f0 amdfwtool: Remove the limit of spliting EFS and body
To support 32M flash, the non-vboot also need to split amdfw. Just as
the deleted comment says, we need this feature now.

This is one of series of patches to support 32/64M flash.
BUG=b:255374782

Change-Id: Ic058cfaeebd1a947227cfa9be2db4eb22702aa28
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-02 20:18:00 +00:00
Zheng Bao 69ea83c3c5 amdfwtool: Change .rom.efs to .rom and .rom to .rom.body
To support 32M flash, the non-vboot also need to split amdfw.

The amdfw.rom is the default filename added to CBFS.
Keep the default filename and then we don't have to change all the
CBFS definition.

This is one of series of patches to support 32/64M flash.
BUG=b:255374782

Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-02 20:17:33 +00:00
Wojciech Macek 9edaccd922 util/cbfstool/eventlog: Use LocalTime or UTC timestamps
Add a new flag "--utc" to allow the user to choose if
elogtool should print timestamps in Local Time or in UTC.
It is useful for generating automated crash reports
including all system logs when users are located in
various regions (timezones).

Add information about timezone to timestamps printed
on the console.

Signed-off-by: Wojciech Macek <wmacek@google.com>
Change-Id: I30ba0e17c67ab4078e3a7137ece69009a63d68fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-03-02 13:05:35 +00:00
Zheng Bao fd51af6286 amdfwtool:combo: Move the filling of field "lookup" into function
This filling does not need to be done separately.

Change-Id: I53051349923dce40f4fc3f747ab41a93a3798823
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-01 13:25:13 +00:00
Zheng Bao c91867af13 amdfwtool: Remove the hints of flag --combo-capable
A few references to "--combo-capable" were left after commit 4bfb36ed68

Change-Id: I6f425db2a8b86d7ad928baee6bc7b07e5190ba37
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73281
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-01 13:24:32 +00:00
Zheng Bao 6095cd1501 amdfwtool: Clean up the logic sequence of pointer growing
When the EFS data is being packed, the pointer should be at EFS
header.
After that, it should be at body location.

TEST=binary identical test on amd/birman amd/chausie amd/majolica
amd/gardenia pcengines/apu2 amd/mandolin

Change-Id: Ia81e2bdf9feb02971723f39e7f223b5055807cd8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-01 13:01:34 +00:00
Zheng Bao 9770df1e9d amdfwtool: Check the validation of EFS & body relative address
We need to considering the case the EFS header is given as a relative
address and the other, body location, is given as an absolute one. So
we convert both of them to relative and check the validation.

For relative address case, the location should be between
0 and data size.

Change-Id: I7898bfbca02f5eb1c0fb7c456dc1935bddf685b1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-28 13:03:46 +00:00
Zheng Bao da43c41f98 amdfwtool: Fill the address in EFS header as "relative to BIOS"
If ctx.address_mode is "physical", it will keep as "physical".
If ctx.address_mode is "relative to table", it will be changed as
"relative to BIOS".

Because the "current table" is the whole flash, the code worked well.

TEST=Binary identical test on amd/birman amd/chausie amd/majolica
amd/gardenia pcengines/apu2 amd/mandolin

Change-Id: I9acb54cc5de149d8a705bb05bf351c44b7d3ced1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-28 12:54:03 +00:00
Zheng Bao 7c5ad88887 amdfwtool: Add universal cleanup function
Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-27 18:01:27 +00:00
Zheng Bao c38f76410b amdfwtool: Add missing parentheses in macro definition
Change-Id: I1b43dbb8cdc748960f25d7b0629aa81528a2a476
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-24 23:09:31 +00:00
Zheng Bao c26108f603 amdfwtool: Change the growing pointer with cautions
Changing the pointer outside the function is not allowed.
Check if it overflows everytime it changes.

TEST=Binary identical on amd/birman amd/chausie amd/majolica
amd/gardenia pcengines/apu2 amd/mandolin

Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-24 23:09:02 +00:00
Zheng Bao 71e752b934 amdfwtool: Remove the useless variable "rom"
Now we use ctx.rom. Remove the wrong statement releasing null
pointer.

Change-Id: I134335ed741dc067e232621106f2057e50ba6a1a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-24 13:42:23 +00:00
Elias Souza 17d9d897f0 crossgcc: Replace binutils no-bfd-doc patch with configure option
It is not more necessary to patch binutils, we can
pass an argument during build time to not build docs.
Regenerate binutils-2.37_no-makeinfo.patch.

Change-Id: If600f0bb46db5f84956940683a7adc83eaca01e5
Signed-off-by: Elias Souza <eliascontato@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73115
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-19 16:08:26 +00:00
Kyle Lin 05d6f5a488 util/spd_tools/src/spd_gen/lp5.go: Support LP5X 8533Mbps
Add support for LP5X 8533Mbps in SPD tool.

BUG=b:263189532
TEST=None

Change-Id: I72b02514f68647dda996822f910db8bc93f61ca4
Signed-off-by: Kyle Lin <kylelinck@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marx Wang <marx.wang@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-18 16:00:06 +00:00
Felix Singer 36847977cb util/crossgcc: Update GCC from 11.2 to 11.3
While the work on updating GCC to version 12 is still WIP, update it
to the latest minor release 11.3.

Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I8810bbb238b01985774ff8da1e246ab1b192e663
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70221
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-17 15:01:48 +00:00
Elyes Haouas 2ed4b0bd7c lint/checkpatch.pl: Remove check for keyword 'boolean' in Kconfig
We can not use 'boolean' since commit 53ea1d44 "util/kconfig: Uprev to Linux 5.13's kconfig".
This also reduce difference with upstream.

Change-Id: Iff9fbde46784547c07726816d2fdd71967e0595e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17 14:50:29 +00:00
Martin Roth 60f367a473 util/release: Update build-release script
- Make variables for the release name and the tarballs instead of
writing them out every time.
- Skip some more unnecessary files when creating the tarballs.
- Remove unnecessary check for the commit ID. It's now a required field.
- Correctly get and save the time of the last release for use in
creating the tarballs.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I56cd5e2dcf01ee55e5d45e837db2f89904b06ddd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-15 13:08:45 +00:00
Zheng Bao 4bfb36ed68 amdfwtool: use SoC ID info instead of misleading comboable flag
Since it actually depends on the SoC type whether the old PSP
directory table pointer or the new comboable PSP directory table
pointer is used in EFS, get this information from the SoC ID instead
of passing the comboable flag for the SoCs that need to use the new
comboable PSP directory table pointer.

TEST=Binary identical on amd/majolica, pcengines/apu2, amd/gardenia

Change-Id: I0c3f21065939d1b13c2607aba16cbef74dd8d389
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-14 18:24:08 +00:00
Zheng Bao 6a1af48c58 amdfwtool: Remove command line option soc-name
5/5
of split changes of https://review.coreboot.org/c/coreboot/+/58552/28

Change-Id: Iba2ebd5d0310538e04c07493d28039509ad02321
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-13 13:46:43 +00:00
Iru Cai 9874b1a7de util/autoport: Fix the typo of ehci2 in bd82x6x.go
This corrects the word "echi2" to "ehci2".

Change-Id: Id8911de147538f4614627cfca449bad528ab6780
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-13 05:45:23 +00:00
Zheng Bao 010cc99896 amdfwtool: Put soc name setting to fw.cfg from command line
The fw.cfg should combine the SOC name.
This is for future combo feature. Each entry in combo has its own
fw.cfg.
The soc_id in struct cb_config can only be available after the fw.cfg
is processed.
Some functions which take soc_id as a parameter can be simplified.

3/5 (and the key one with same change ID)
of split changes of https://review.coreboot.org/c/coreboot/+/58552/28

Change-Id: Ib0eead1f2156542ea03d58145f5ad67683bf9b52
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-11 12:58:17 +00:00
Matt DeVillier 554c13dc2c util/chromeos/extract_blobs: allow passing dest dir as arg
Allow user to pass the output dir for the extracted blobs as the 2nd
argument to the script; if not provided, fall back to the existing
default.

Change-Id: I0f120b69e0b6d14c2763b9a3b2a622e77c4fe0d4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-10 14:53:58 +00:00
Zheng Bao 4bf6f49d12 amdfwtool: Move soc_id to cb_config
Save the soc_id into a global struct.

Change-Id: I2a0f04a09635086e3076a97b535df8a19d0693ce
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72450
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-10 12:45:00 +00:00
Fred Reitberger c4f3a33e49 util/amdfwtool: Add UMSMU blob support
Add PSP blob Type 0xA2 uMsmu support.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ib38ec03bf20f46774f7438b21d18704cc1ec57fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-09 20:43:36 +00:00
Zheng Bao 29063fbd7d amdfwtool: Parse the line with SOC_NAME
We need to put soc name to fw.cfg for future combo feature.
We skip for now when SOC_NAME is found.

1/5
of split changes https://review.coreboot.org/c/coreboot/+/58552/28

Change-Id: I2b8d7154d22db13675ff57b6abe61c747604c524
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-09 13:45:51 +00:00
Zheng Bao 3d7623ffc9 amdfwtool: Add SOC family definition for Carrizo
For Carrizo, the soc name was set as UNKNOWN.

The change is supposed to be binary unmodified, except the SPI
settings. According to the spec, the Stoneyridge and Carrizo have the
same definition of SPI setting in EFS.

Change-Id: I9704a44773b2f541f650451ed883a51e2939e12a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-09 13:44:39 +00:00
Zheng Bao 4e8fb3503c amdfwtool: Allow the location to be a relative address
When the BIOS size is more than 32M, the physical address of EFS
header will be complicated, like 0xfe020000 or 0xfc020000. So we make
it simpler to allow to use relative address.

This CL works with https://review.coreboot.org/c/coreboot/+/69852

TEST=Result image is binary same on
amd/birman amd/majolica amd/gardina amd/mandolin

Change-Id: I4308ec9ea05a87329aba0b409508c79ebf42325c
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-09 13:04:08 +00:00
Martin Roth 0363561a30 util/testing: Allow scanbuild test to be skipped
This is currently killing the jenkins builds.  This patch allows it to
be disabled until the reason is found.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I16dba80a88953aa95f7f647ba12b2ec3297ab81f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-08 19:15:40 +00:00
Zheng Bao 7c7294fa27 amdfwtool: Report the address of EFS header and body
The address mode is an internal mode which AMD FWs use. Regular
developers don't have to know that. Just report the relative address
every time. For the cases head and body are split, the address of body
is also reported.

Change-Id: I77d9aac0b3d996363341c1d2dae049ec344b39aa
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-08 12:26:37 +00:00
Martin Roth 1b74898395 util/abuild: Add flags to allow abuild to skip boards
This change adds 2 command line parameters, --skip_set and --skip_unset
that allows abuild to skip boards with particular Kconfig values either
set or not set.

Note that it only works on BOOL type variables.

This can be set on the abuild command line, or the JENKINS_ABUILD_OPT=
variable on the make command line.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I43336484cf25f83065ec7facf45c123d831024b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-07 23:33:39 +00:00
Alexander Goncharov 893c3ae892 tree: Drop repeated words
Found-by: linter
Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-07 04:37:31 +00:00
Martin Roth 0cbc3528e5 util/docker: Add libgpiod-dev to coreboot-sdk for flashrom
Flashrom needs libgpiod-dev to build the new bitbanging programmer
driver for Linux libgpiod.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I88f7e11fab115487cc44d4b89b3eab4745ad058d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2023-02-06 12:44:31 +00:00
Zheng Bao 4044e85938 amdfwtool: Add phoenix and glinda in get_psp_fw_type
Change-Id: If80cc5396703cef41cc615008c9f0dac0b7bbb09
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-02-06 12:28:06 +00:00
Zheng Bao 1d7fa216ba amdfwtool: Remove useless printing out
Change-Id: I819633d8d6d1886b48d53e73923add444ca032e4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72724
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-05 01:10:46 +00:00
Zheng Bao 7db7642a85 amdfwtool: Add a function to make the calling stack less deep
And make less levels of indentations in the code.

Change-Id: Ib8cae386eace4f423bde9c252992625e1ff3c690
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-05 01:08:55 +00:00
Martin Roth 4bd2325802 util/scripts/testsoc: Pass arguments to abuild
This allows the user to pass one or more arguments through the testsoc
script to abuild.

Example:
testsoc -K SOC_AMD_CEZANNE -a "--skip_unset BOARD_GOOGLE_NIPPERKIN"

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic2bc8d656022560ed1eebf6eee0512d3633ebe84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72766
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-05 00:51:38 +00:00
Felix Held 9f5a5eefc3 util/amdfwtool: add comment about reused PSP firmware type 0x5f
On family 15h and 16h processors with PSP, the PSP firmware type 0x5f
corresponds to AMD_FW_PSP_SMUSCS, while on family 17h and 19h this
corresponds to AMD_FW_TPMLITE. Add comments to those two enum values to
clarify this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia5c125ec6a0eb548f58a457f9040278391d2101c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-04 03:15:37 +00:00
Arthur Heymans bc3261f828 util/autoport: Use chipset.cb references
TESTED with x220 logs.

Change-Id: I89023b6c6dd5d985168331fbb12b2fc36fb65dc3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-04 01:42:43 +00:00
Zheng Bao 85ee1fd571 amdfwtool: Add entry RIB whose subprog equals 1
For the PHX, it uses subprog 0.
For the PHX2, it uses subprog 1.

Change-Id: Ib013f264fc9940ad95e559fe19bba72c06a19625
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-04 01:42:13 +00:00
Fred Reitberger abce429dac util/scripts/testsoc: Only select mainboards
The testsoc script was pulling in odd results when the -K option matched
options in sources, Makefiles, and device trees.  Adding another grep to
limit the list to just Kconfig matches ensures that only actual
mainboards are built.

TEST="./util/testsoc -K PICASSO" no longer tries to build mainboard "0"

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I3860df4520a5594fb9c1a06e75487520b7d5d275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72655
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-03 13:57:07 +00:00
Tarun Tuli 5044dc48f3 util/cbfstool: Add eventLog support for ELOG_TYPE_FW_EARLY_SOL
In order to support logging events for when we show early signs
of life to the user during CSE FW syncs and MRC trainings add
support for the ELOG_TYPE_FW_EARLY_SOL type.

BUG=b:266113626
TEST=verify event shows in eventlog CSE sync/MRC training

Change-Id: I3913cb8501de9a2605266cf9988a7195576cb91d
Signed-off-by: Tarun Tuli <tarun.tuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71296
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-02-02 21:44:13 +00:00
Zheng Bao cc132038e2 amdfwtool: Set the level of RIB file as level 2
It is about AB recovery layout which only has level 2.

Change-Id: I836f11ca0bf5ad37e5093419465244a5c83318cb
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-02 13:43:59 +00:00
Patrick Rudolph ef5ebdb5bb ifdtool: Introduce region_name_fmap
Instead of directly accessing the region_name array use a helper
function. This allows to move the region name array to a separate
file.

Change-Id: Ifc810da1628cebd2728d0185502c462ff9428597
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-02 13:22:00 +00:00
Patrick Rudolph 1920900baa ifdtool: Add missing chipset_name
Add denverton soc chipset name.

Change-Id: I0fd8494123490d6ccc21af2ed30c30d50ddb4e8e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68693
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-02 13:21:07 +00:00
Patrick Rudolph 09b136cfe8 ifdtool: Drop chipset without IFD
Drop unused chipsets that do not use an IFD.

Change-Id: I999e5e5d2063b8d33819fb22296ed486e1194cbb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-02 13:20:19 +00:00
Patrick Rudolph be25f96c2d ifdtool: Cleanup IFDv1 detection
Change https://review.coreboot.org/c/coreboot/+/54305 "util/ifdtool:
Use -p platform name to detect IFDv2 platform and chipset" made
the '-p' argument mandatory for IFDv2 platforms.

Drop the IFDv2 platform CHIPSET_C620_SERIES_LEWISBURG from IFDv1
detection.

Change-Id: If29f8718b7aa696cdc07deef4c98be9a68c66f10
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68680
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-02 13:19:36 +00:00
Patrick Rudolph 16598745b8 util/ifdtool: Add Wellsburg support
Wellsburg is IFDv2 compatible in most fields, but not in all.
It only has 8 regions and the flash master bits match the defines for
IFDv1 and thus has an "IFDv1.5" descriptor.

Add a new enum for IFDv1.5 descriptor and use them to properly operate
on this IFD.

The 'SPI programming guide' is inconsistent and mentions 6 regions
in one place, but 7 regions in another chapter. Tests showed that it
actually supports 7 regions.

Add support using the -p argument to specify Wellsburg platform.

The previous patch made sure that only 8 regions are used and that no
corruption can happen when operating in IFDv2/IFDv1.5 mode.

Tested on Intel Grangeville.

Documents used:
Intel Document Id: 516552
Intel Document Id: 565117

Change-Id: I651730b05deb512478d059174cf8615547d2fde4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Co-developed-by: Julian Elischer <jrelis@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-02 13:19:11 +00:00
Zheng Bao 7c558d0cfa amdfwtool: Remove the duplicated entry RIB
It should be PSP_RIB_FILE which is already there.

Change-Id: Ie7471489bd34554e357510b04473102d002f9988
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72506
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-01 13:44:02 +00:00
Elyes Haouas b63eb4d172 crossgcc: Upgrade LLVM version 15.0.6 to 15.0.7
Change-Id: I3198b065316b98f2d26360c4e65055e7460ea707
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-01 06:06:36 +00:00