Commit Graph

41200 Commits

Author SHA1 Message Date
Angel Pons 88f94a9635 lynxpoint/broadwell: Rename LP GPIO config global
Do not use the same name as the non-LP GPIO config. This allows checking
at build-time that a mainboard uses the correct GPIO config format.

Without this commit, there are no build-time errors when using the wrong
format of GPIO config, but there would be undefined behavior at runtime.

Tested by trying to build asrock/b85m_pro4 and hp/folio_9480m after
toggling the `INTEL_LYNXPOINT_LP` Kconfig option (and trimming down the
USB config arrays for asrock/b85m_pro4). In both cases, building failed
because the necessary GPIO config global is not defined, as expected.

Change-Id: Ib06507ef8179da22bdb27593daf972e788051f3a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51661
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 11:26:22 +00:00
Frank Wu d12d24b039 mb/google/zork: Enable SSFC as upper 32 bit of fw_config
To append SSFC to top 32 bits of fw_config.

BUG=b:177971830
BRANCH=firmware-zork-13434.B
TEST=Build coreboot and get the value of SSFC.

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Iab1596f1cc8fbbf45e6a9269351bf422a43f3583
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51655
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 11:25:48 +00:00
Sugnan Prabhu S 31f383686a mb/google/brya: Enable S0ix
This change enables S0ix for brya platform.

BUG=b:181843816
TEST=Built image and booted to kernel.

Change-Id: Idc6f7fce9779ef4458375becebf5dc65b228abeb
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51526
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 11:25:26 +00:00
Patrick Rudolph 9f5261e5fa device/azalia_device.c: Switch to stopwatch
Use timer.h helpers instead of open-coding timeout handling in polling
loops. The 25-microsecond delay in `wait_for_valid` looks odd, and may
be removed in subsequent commits. For now, preserve existing behavior.

Change-Id: Id1227c6812618597c37408a7bf53bcbcae97374a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50789
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 11:22:39 +00:00
Zanxi Chen d92966b610 mb/google/dedede/var/storo: Add USB Port Configuration
Add USB Port configuration into devicetree for storo

BUG=b:177389444
BRANCH=dedede
TEST=built firmware and verified USB3.0 function is OK

Change-Id: I1527c7178ffac9b2322eb65aab6e2086d949e47c
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-22 11:22:06 +00:00
Jakub Czapiga 61fcb7e965 acpi/acpigen.h: Add more intuitive AML package closing functions
Until now every AML package had to be closed using acpigen_pop_len().
This commit introduces set of package closing functions corresponding
with their opening function names. For example acpigen_write_if()
opens if-statement package, acpigen_write_if_end() closes it.
Now acpigen_write_else() closes previously opened acpigen_write_if(),
so acpigen_pop_len() is not required before it.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Icfdc3804cd93bde049cd11dec98758b3a639eafd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-22 11:21:55 +00:00
Eric Lai 7f4c30c1d5 mb/google/zork: Move max98357a out of baseboard
Not all of dalboz variants support the this amp. Thus, move out of baseboard.

BUG=b:182815488
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If708574f5fb18dd3b4f2ef978529a16a40d5dc0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-22 03:51:23 +00:00
Karthikeyan Ramasubramanian 8f7fca5370 mb/google/guybrush: Enable AP <-> H1 communication
Configure H1 I2C and Interrupt GPIOs during the early initialization.
Add devicetree configuration for H1 device and enable the required
config items.

BUG=b:180528902
TEST=Build Guybrush mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I040a5e6101bab0c7425d7b6cc6fbed3b479a5a44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-22 03:50:08 +00:00
Karthikeyan Ramasubramanian 699a709bdc mb/google/guybrush: Add initial I2C configuration
Add I2C peripheral reset configuration required during early init.
Enabled I2C generic and HID drivers. I2C GPIOs are configured as
required in CB:50091.

BUG=b:180531661
TEST=Build guybrush mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I67690fbd25639879a730260aaca4cddb5e47bbc7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-22 03:49:18 +00:00
Zheng Bao 7b13e4ef2a soc/amd/cezanne: Initialize I2C
Add I2C initialization in romstage and ramstage.

TEST=To test the I2C connection on Majolica, which doesn't have SPD
connection, call the function below after i2c_soc_init is called.
     i2c_read_bytes(2, 0x4d, addr, data, 1);/* Read out 1 byte one time */
It can get the register values of TMP432B.

Or
     /* Override EC port in ec.h */
     #define EC_DATA	0x662
     #define EC_SC	0x666
     ec_write(0xA9, 0x40);
     i2c_read_bytes(1, 0x10, addr, data, 2);/* Read out 2 bytes one time */
It can get the register values of CM32181A3OP(ALS).

Change-Id: I3a2a1494b44b68e8d8204fba0c90e769e0256e6f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51029
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 03:44:30 +00:00
Zheng Bao b0f00ed426 soc/amd/cezanne: Get I2C specific code for cezanne
Add macros, settings and callbacks to support I2C for cezanne.

Change-Id: Ic480681d4b7c6fb8591e729090e4faeb5fccf800
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-22 03:43:25 +00:00
Zheng Bao 7a0b9c5e73 trivial: Fix the tab and rearrange the lines
Change-Id: I1ded9fcec9594977b9b9c8d3c105f9998c0ee2bc
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51656
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 03:41:25 +00:00
Zheng Bao 16e1fd5ae9 mb/amd/majolica: Set IOMUX to enable I2C2 & I2C3
Change-Id: I142c06c150214d58acc04b8c6b3b027fff0256db
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-03-22 03:40:53 +00:00
Karthikeyan Ramasubramanian 4f87ae1d4a soc/amd/common/block/i2c: Move SoC agnostic parts into common
The logic behind I2C bus initialization, I2C MMIO base address getter
and setter, I2C bus ACPI name resolution are identical for all the AMD
SoCs. Hence moving all the SoC agnotic parts of the driver into the
common driver and just configure the SoC specific parts into individual
I2C drivers.

BUG=None
TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C
peripherals are detected as earlier in Dalboz. Verify some I2C
peripheral functionality like trackpad and touchscreen.

Change-Id: Ic9c99ec769d7d8ad7e1e566fdf42a5206657183d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51509
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 03:40:42 +00:00
Karthikeyan Ramasubramanian 0dbea48d46 soc/amd/common: Introduce I2C driver common to all AMD SoCs
I2C driver is replicated in each generation of AMD SoCs. Introduce a
common I2C driver that can be used across all the AMD SoCs. To begin
with, peripheral reset functionality is moved into this common driver.
SoC specific I2C driver passes the SCL pin configuration in order for
the common driver to reset the peripherals. More functionality can be
moved here in subsequent changes.

Also sb_reset_i2c_slaves() is renamed as sb_reset_i2c_peripherals() as
an effort towards using inclusive language.

BUG=None
TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C
peripherals are detected as earlier in Dalboz.
localhost ~ # i2cdetect -y 0
Warning: Can't use SMBus Quick Write command, will skip some addresses
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:
10:
20:
30: -- -- -- -- -- -- -- --
40:
50: 50 51 -- -- -- -- -- -- 58 59 -- -- -- -- -- --
60:
70:
localhost ~ # i2cdetect -y 1
Warning: Can't use SMBus Quick Write command, will skip some addresses
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:
10:
20:
30: -- -- -- -- -- -- -- --
40:
50: UU -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60:
70:

Change-Id: I9f735dcfe8375abdc88ff06e8c4f8a6b741bc085
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-22 03:40:23 +00:00
Tinghan Shen 1a5d279120 soc/mediatek/mt8192: devapc: Add SCP domain setting
Configure SCP domain from 0 to 3 and lock it to prevent
changing it unexpectedly.

BUG=b:163300760
TEST=emerge-asurada coreboot
BRANCH=asurada

Change-Id: Idccb001f0cf58492f7f1655203106470637b9b82
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-22 01:51:37 +00:00
Marc Jones 4de7610b32 soc/intel/xeon_sp/cpx: Set PCU locks
Set the PCU locks as indicated by the BWG.

Lock the following:
 P_STATE_LIMITS
 PACKAGE_RAPL_LIMIT
 SAPMCTL
 DRAM_PLANE_POWER_LIMIT
 CONFIG_TDP_CONTROL

Change-Id: I5f44d83e2dd8411358a83b5641ddb4c370eb4e84
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51505
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20 16:48:33 +00:00
Marc Jones 52e14f78ba soc/intel/xeon_sp/: Fix SMI_LOCK setting
Move the SMI_LOCK to post SMM setup. Also, use the correct access
method for SMI_LOCK. GEN_PMCON_A is in PCI config space and not
in MMIO space on this PCH.

Change-Id: Ibbb183ef61ca7330198c1243ecfc2d4df51e652b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51452
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20 16:48:24 +00:00
Marc Jones f332e47f56 mainboard/: Register chipset_lockdown on xeon_sp mainboards
Set chipset_lockdown in devicetree for recommended security settings.

Change-Id: Ie27450dd32463243b1456932a1d39d40afa81da1
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51388
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20 16:00:54 +00:00
Angel Pons f479c85227 soc/intel: Drop unused `GPIO_NUM_GROUPS` macro
This macro is unused and its value is often wrong. Drop it.

Change-Id: Id3cfaa4d2eef49eddc02833efbe14e0c5c816263
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51662
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20 12:29:19 +00:00
Matt DeVillier 4c3851afbf mb/purism/librem_cnl: Add new board/variant Librem 14
Add support for the CometLake-U based Librem 14 laptop.

Change-Id: I24a2a92091cc272638ecaf8ea23a896cab8a7153
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51549
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20 12:22:21 +00:00
Kevin Chiu 4490689d88 google/trogdor: Add new variant Marzipan
This patch adds a new variant called Marzipan that is identical to Lazor
for now.

BUG=b:182181519,b:182018606
BRANCH=master
TEST=make

Change-Id: I92b667c63b0a06255d1e9511d7486293d8b4426a
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-20 01:31:06 +00:00
xuxinxiong 8f11d24038 mb/google/trogdor: Add support for SPI_FLASH_GIGADEVICE
Add support SPI_FLASH_GIGADEVICE for some project.

BUG=b:182246432
BRANCH=trogdor
TEST=emerge-strongbad and test with power on.

Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Change-Id: I6ab948909f4e17b4b992be6d699646f7a62bef7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-20 01:11:51 +00:00
Kevin Keijzer 51b1b2a0c4 mb/lenovo/x200: Fix boot-time docking state
The X200 would undock itself when waking up from S3, requiring a
physical reconnection before the dock would work again.

Similar to 4611ad8, this reintroduces h8_mb_init() for the X200. A hook
function h8_mb_init() will be called at the end of h8_enable(), in place
of the ancient h8_mainboard_init_dock().

This should fix the regression the X201 and T410 also suffered from for
the X200.

Change-Id: Icb6dd145e56b90e0e04133810c5e9ac7b641ad68
Signed-off-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51123
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19 17:18:37 +00:00
Angel Pons da12ca98c9 doc/mb/lenovo/montevina: Update link within page
Commit c4aa24fc12 (doc/mb/lenovo/montevina: Clarify use of bincfg)
renamed a section, and the link referencing it by its old title no
longer works. Update the link, and remove the `a completely new one`
part from it as well, for consistency with the aforementioned commit.

Change-Id: I22e8b3237dafb3397bc901804a57e905f806839d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-19 12:46:06 +00:00
Julien Viard de Galbert b3e504c310 mb/scaleway/tagada: Don't change FIAMUX when Security Override is set
This will not enable M.2 SATA drive if the ME config was lost
(For instance after flashing a full flash factory image)

This is required so that the system can boot without FIA MUX error
during flash update procedure.

Change-Id: I55a8bcdc30bc67af2d3e9ccb8844eac599727108
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19 11:36:27 +00:00
Arthur Heymans 7e4ad26b95 3rdparty/intel-sec-tools: Update submodule pointer
This includes the bg-prov tool.

Change-Id: Iba8efe3bcb67694da76ef78abaa0562d47f7850b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-03-19 11:35:13 +00:00
Arthur Heymans 2390754982 security/intel/cbnt: Make CBNT compatible with CMOS option table
Make sure the bytes in RTC cmos used by CBNT don't collide with the
option table. This depends on what is set up in the BPM, Boot Policy
Manifest. When the BPM is provided as a binary the Kconfig needs to be
adapted accordingly. A later patch will use this when generating the
BPM.

Change-Id: I246ada8a64ad5f831705a4293d87ab7adc5ef3aa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-19 11:35:07 +00:00
Arthur Heymans 9036bd7cb1 cpu/x86/mp_init.c: Drop unnecessary preprocessor usage
Change-Id: If67bcbf0c8ffbd041e2e4cab8496f4634de26552
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19 11:33:51 +00:00
Arthur Heymans 41b078f8ae cpu/x86/mp_init.c: Don't overwrite the global variable per CPU
Global variables are located in .bss and not on the CPU stack.
Overwriting them a per CPU case is bound to cause race conditions. In
this case it is even just plainly wrong.

Note: This variable is set up in the get_smm_info() function.

Change-Id: Iaef26fa996f7e30b6e4c4941683026b8a29a5fd1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19 11:33:43 +00:00
Arthur Heymans 1e1d5d60f7 cpu/x86/smm_module_loaderv2.c: Remove noop stack size check
The argument provided to the function was always the same as the one
computed inside the function so drop the argument.

Change-Id: I14abf400dce1bd9b03e401b6619a0500a650fa0e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19 11:33:35 +00:00
Arthur Heymans 478f3d8f5e cpu/x86/mp_init: Allow stub sizes larger than the save state size
The permanent handler module argument 'save_state_size' now holds the
meaning of the real save state size which is then substracted from the
CPUs save state 'top' to get the save state base.

TESTED with qemu Q35 on x86_64 where the stub size exceeds the AMD64
save state size.

Change-Id: I55d7611a17b6d0a39aee1c56318539232a9bb781
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19 11:33:28 +00:00
Arthur Heymans ad0116c032 cpu/x86/smm_loaderv2: Remove unused variables
Remove variables that are either constants or are just assigned but
not used.

Change-Id: I5d291a3464f30fc5d9f4b7233bde575010275973
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19 11:33:17 +00:00
Arthur Heymans 1afe20b1b2 cpu/x86/smm/smm_module_loaderv2.c: Constify setup_stub()
Change-Id: I6648d0710bc0ba71cfbaaf4db7a8c1f33bbc9b35
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19 11:33:08 +00:00
Arthur Heymans 64d9e85681 cpu/x86/smm_module_hander: Set up a save state map
With the smm_module_loaderv2 the save state map is not linear so copy
a map from ramstage into the smihandler.

TESTED on QEMU q35: Both SMMLOADER V1 and V2 handle save states properly.

Change-Id: I31c57b59559ad4ee98500d83969424e5345881ee
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19 11:32:59 +00:00
Arthur Heymans dfff5c2d19 cpu/x86/smm_loaderv2: Fix when only 1 CPU is present
Move out smm_create_map as this was not run if concurrent_save_states
is 1. The cpus struct array is used in the smm_get_cpu_smbase()
callback so it is necessary to create this.

TEST: run qemu/q35 with -smp 1 (or no -smp argument)

Change-Id: I07a98bbc9ff6dce548171ee6cd0c303db94087aa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19 11:31:17 +00:00
Arthur Heymans 50e849fc9b cpu/x86/smm_stub.S: Drop smm_runtime from the stub
The parameters that the permanent handler requires are pushed directly
to the permanent handlers relocatable module params.

The paremeters that the relocation handler requires are not passed on
via arguments but are copied inside the ramstage. This is ok as the
relocation handler calls into ramstage.

Change-Id: Ice311d05e2eb0e95122312511d83683d7f0dee58
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-19 11:30:47 +00:00
Arthur Heymans 6f9b1a9049 cpu/x86/smm.h: Remove smm runtime pointer from smm_loader_params
struct smm_loader_params is a struct that is passed around in the
ramstage code to set up either the relocation handler or the permanent
handler. At the moment no parameters in the stub 'smm_runtime' are
referenced so it can be dropped. The purpose is to drop the
smm_runtime struct from the stub as it is already located in the
permanent handler.

Change-Id: I09c1b649b5991f55b5ccf57f22e4a3ad4c9e4f03
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19 11:29:37 +00:00
Arthur Heymans 1dfa46ecfd cpu/x86/mp_init.c: Copy the stub parameter start32_offset into ramstage
Keep a copy of start32_offset into ramstage to avoid needing to pass
arguments, calling from assembly. Doing this in C code is better than
assembly.

Change-Id: Iac04358e377026f45293bbee03e30d792df407fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50765
Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19 11:29:20 +00:00
Arthur Heymans 823b1a8270 cpu/x86/smm_module_handler: Add relocatable module params
Instead of passing on parameters from the stub to the permanent
handler, add them directly to the permanent handler.

The parameters in the stub will be removed in a later patch.

Change-Id: Ib3bde78dd9e0c02dd1d86e03665fa9c65e3d07eb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19 11:29:10 +00:00
Arthur Heymans c9aecb4440 cpu/intel/fit: Reserve the FIT pointer using a .c file
No need to do this assembly anymore.

Change-Id: I69b42c31e495530fe96030a5a25209775f9d4dca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-19 11:23:59 +00:00
Arthur Heymans eeacd8349c cpu/intel/fit: Add the FIT table as a separate CBFS file
With CBnT a digest needs to be made of the IBB, Initial BootBlock, in
this case the bootblock. After that a pointer to the BPM, Boot Policy
Manifest, containing the IBB digest needs to be added to the FIT
table.

If the fit table is inside the IBB, updating it with a pointer to the
BPM, would make the digest invalid.
The proper solution is to move the FIT table out of the bootblock.

The FIT table itself does not need to be covered by the digest as it
just contains pointers to structures that can by verified by the
hardware itself, such as microcode and ACMs (Authenticated Code
Modules).

Change-Id: I352e11d5f7717147a877be16a87e9ae35ae14856
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50926
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19 11:23:21 +00:00
Arthur Heymans e9e4e54e27 util/ifittool: Add an option to set the FIT pointer a CBFS file
The purpose of this is to eventually move the FIT table out of the
bootblock, generate it separately as a cbfs file and then have the FIT
pointer point to that cbfs file.

TESTED: extracted a FIT table using dd, added it as a cbfs file and see
that the FIT pointer correctly points to it. Also test that trying to
add a non valid FIT cbfs file results in an error.

Change-Id: I6e38b7df31e6b30f75b0ae57a5332f386e00f16b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-03-19 11:22:55 +00:00
Angel Pons 6ca3375c08 soc/amd/picasso/soc_util.c: Fix typo in macro name
Change-Id: I3225fa4e53a75c2bf6fe0dcea85db57efe489482
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51615
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19 11:22:32 +00:00
Wisley Chen 0afecd8d08 mb/google/volteer/var/elemi: Config GPP_B7/GPP_B8 as NC
elemi does not use the GPP_B7/GPP_B8, so config to NC.
Currently, there is no functional impact.

BUG=b:182981460
TEST=emerge-volteer coreboot, boot into OS, and suspend/resume
successfully.

Change-Id: I7b491fd595b0e77e6dcce08e3172dbe592f63c37
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-03-19 11:22:17 +00:00
Derek Huang 8056187e4e soc/intel/tgl: Add configurable value for PmcUsb2PhySusPgEnable
PmcUsb2PhySusPgEnable is enabled by default. Expose devicetree
parameter to disable

Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: Ibd54a10c57d39bb8762b705ef0d6ff4cd47f0d89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-03-19 11:22:07 +00:00
Matt DeVillier 9e82bf36c8 mb/purism/librem_cnl: drop MAX_CPUS from Kconfig
No need to restrict this further than the platform default,
and will be problematic with the addition of the upcoming
6C/12T Librem 14 board.

Change-Id: I1913992ec12578e1ad3bf6bf679d1a35a46d7370
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19 11:21:23 +00:00
Angel Pons 747a2fc90e mb/{clevo/cml-u,system76/lemp9}: Clarify `gen2_dec` use
This I/O range is for a PM channel on the EC, not the PCH PMC.

Change-Id: I64422e537c1edcd0673cf87f16139fb117b10e75
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51604
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19 11:21:12 +00:00
Angel Pons 90ae08922d nb/intel/haswell: Consolidate memory-down SPD handling
Mainboards do not need to know about `pei_data` to tell northbridge code
where to find the SPD data. Adjust `mb_get_spd_map` to take a pointer to
a struct instead of an array, and update all the mainboards accordingly.

Currently, the only board with memory-down in the tree is google/slippy.
Mainboard code now obtains the SPD index in `mb_get_spd_map` and adjusts
the channel population accordingly. Then, northbridge code reads the SPD
file and uses the index that was read in `mb_get_spd_map`, and copies it
to channel 0 slot 0 unconditionally. MRC only uses the first position of
the `spd_data` array, and ignores the other positions. In coreboot code,
`setup_sdram_meminfo` uses the data of each SPD index, so `copy_spd` has
to account for this.

Tested on Asrock B85M Pro4, still boots and still resumes from S3.

Change-Id: Ibaed5c6de9853db6abd08f53bbfda8800d207c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51448
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19 11:20:06 +00:00
Angel Pons afc6c0ae12 mb/google/slippy: Correct memory-down SPD handling
MRC only uses the SPD data for the first index, and ignores the rest.
Moreover, index 1 corresponds to the second DIMM on the first channel,
which does not exist on ULT (only one DIMM per channel is supported).

Copy the SPD to the first DIMM on channel 1 instead. Adjust northbridge
code to retrieve the serial number from the correct SPD data block.

Tested on Google Wolf, both channels are still correctly detected.

Change-Id: Ic60ff75043e6b96a59baa9e5ebffb712a100a934
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-19 11:19:51 +00:00