Commit Graph

105 Commits

Author SHA1 Message Date
Zheng Bao ba3af5e2ff amdfwtool: Change the flag value to type bool
Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05 12:56:19 +00:00
Zheng Bao edd1e360f4 amdfwtool: Fix the parameter point to NULL instead of integer
Change-Id: Iaeeec7a7e2de7847bfcefa5b7ff3f259f86533d4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05 12:55:35 +00:00
Zheng Bao 33351336f8 amdfwtool: Change the definition of level to a bitwise form
Change-Id: Icca393f0d69519cc1c3cb852a11dd7006cf72061
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05 12:55:29 +00:00
Zheng Bao eb0404e8bf amdfwtool: Add PSP ID for combo and ISH header for A/B recovery
Nobody calls the function until combo or A/B is added, so suppress the
warning for now.

Test=Majolica (Cezanne)

Change-Id: I3082b850fb3fd2d7ae83a1c4dfd89eb7e1bd0f97
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-29 14:26:22 +00:00
Felix Held ad68b07d45 util/amdfwtool: rename PSP related embedded_firmware struct elements
The element at offset 0x14 in the embedded_firmware struct is the
pointer to the combo PSP directory header, so rename it from comboable
to combo_psp_directory to clarify that this is not a flag, but a pointer
to a data structure. Also rename psp_entry to psp_directory since it
points to the PSP directory table.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic6149c17ae813f4dcea71c308054849a1a2e4394
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-10-19 12:35:08 +00:00
Zheng Bao b1fb8cebf8 amdfwtool: Add an optional column of level
The value of level defined in table is the default one. We now give an
extra option in config file to change this value so some FWs can be
dropped in a more optimized way.
For the non A/B recovery mode, The value could be L1, L2, Lb or Lx,
which are level 1, leve 2, level both and using default value. If it
is empty or Lx, left the level in table unchanged.

Give a redundant field [12bxBX] in regular exprssion for A/B recovery
which will be done later.

Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-23 06:26:47 +00:00
Zheng Bao 2079589999 amdfwtool: Detect the flag multilevel to decide the actual value
To save the space for FW, some of the FWs are going to be defined as
LVL2 entries. To be compatible to "flattened" layout, we still drop
the LVL2 entry to level1 if there is only one level.

Change-Id: Ibe8cdd5c14225899352b02bb19aae6059d56d428
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-17 14:48:30 +00:00
Zheng Bao 535ec536ea amdfwtool: Add new SOC mendocino
Change-Id: I54492600dd954a5585ce3b1d842d264a4a50907a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-15 16:50:44 +00:00
Zheng Bao 481661e313 amdfwtool: Add flag for multi FW level to the struct amd_cb_config
This change can make the code be more flexible. And later we will use
amd_cb_config to transfer parameters.

Change-Id: Ic726aa9fc5f67803210af71d3e9cf2438b7e2a9b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31 15:06:03 +00:00
Zheng Bao dac446165e amdfwtool: Copy string in a safer way
The issue is reported by Coverity. Using strcpy or strcat copying
string without checking length may cause overflow.

BUG=b:188769921

Reported-by: Coverity (CID:1438964)
Change-Id: I609d9ce405d01c57b1847a6310630ea0341e13be
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54946
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31 15:05:48 +00:00
Kangheui Won 275ade9539 Revert "amdfwtool: Use relative address for EFS gen2"
This reverts commit 0fc87e31e0.

Reason for revert: Breaks psp_verstage in guybrush

BUG=b:182477057

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ie50cba4aaf31425ef8fee848c098a826f55c98da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56131
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 20:45:10 +00:00
Zheng Bao ec5a5d7abf amdfwtool: Fix the NULL pointer in parameters
Change-Id: Ia2c65013d48fc1ad88d3caf6ef59824745c992de
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55550
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08 18:52:00 +00:00
Zheng Bao 0fc87e31e0 amdfwtool: Use relative address for EFS gen2
The second generation EFS (offset 0x24[0]=0) uses
"binary relative" offsets and not "x86 physical
MMIO address" like gen1.

Chips like Cezanne can run in both cases, so no problem
comes up so far.

BUG=b:188754219
Test=Majolica (Cezanne)

Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-08 16:04:09 +00:00
Zheng Bao b035f58940 amdfwtool: Null check the pointers before using them
BUG=b:188769922

Reported-by: Coverity (CID:1438963)
Change-Id: Ia520e33c9e4065236478665fb0ef047fa47c9b81
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54999
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14 05:52:40 +00:00
Zheng Bao addf340adf amdfwtool: Add missing license header
Change-Id: Id466e733d421602cfe0403ead95e417f0bb37eb4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-09 05:17:25 +00:00
Zheng Bao 6be1ab67e2 amdfwtool: Move EFS related definitions to header file
EFS: Embedded Firmware Structure

These structs and macros are defined in PSP specs(#55758).
They are supposed to be used by all C sources.

Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-09 05:17:18 +00:00
Zheng Bao 826f1c4610 amdfwtool: Print the entry type when dumping the firmwares
Change-Id: I07bf10e16a42a2b2ab784ee6ac4a4465b7412da6
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-07 17:11:43 +00:00
Zheng Bao e8e6043489 amdfwtool: Set the region_type as 0 for entry "BIOS level 2"
This region_type is actually not used. But we need to set it
explicitly as a known value.

We can refer "PSP spec #55758" or the link below:
   https://doc.coreboot.org/soc/amd/psp_integration.html

Change-Id: I8b914f9f02beecce707aba86248826cd9208e6c0
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-07 17:11:24 +00:00
Nikolai Vyssotski 1965f650ea amdfwtool:cezanne: use correct bootloader binary for whitelist support
PSP whitelist bootloader (PSPBTLDR_WL_FILE) should be copied to type
0x73 entry and not type 0x01 (stage1 bootloader). We will also need to
change WHL BL filename (Type0x01->Type0x73) in a separate CL.

BUG=b:181135622

Change-Id: I71539a2065546547edc8a2621474cd1388b6434b
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-18 10:00:13 +00:00
Zheng Bao 806892a347 amdfwtool: Remove the misleading option characters
Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-05-18 05:56:55 +00:00
Zheng Bao 6f0b361aee amdfwtool: Cleanup the message of help
1. Wrap the long lines.
2. Align the message.
3. Add new SOC name, Cezanne.
4. Fix the cases.

Change-Id: Id537d7c9b77641289274c1b2b6f606e2be37ac6b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-30 23:15:26 +00:00
Martin Roth d509076044 util/amdfwtool: Clean up Makefile
- Add method to disable warnings as errors
- Add help target
- Add phony targets to .PHONY

BUG=None
TEST=make all; make help; make all WERROR=""

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Icd0cfd3e2579c9016ebb616e371d1076a5a171b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-16 08:10:23 +00:00
Martin Roth 90baf6a403 util/amdfwtool: Enable warnings as errors
BUG=None
TEST=Build

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I7746430c24dd052c435561236454b456bc597517
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-16 08:10:12 +00:00
Martin Roth a8e31caee8 util/amdfwtool: Fix all warnings
Fixes these warnings:

warning: alignment 1 of 'struct _psp_directory_table' is less
than 16 [-Wpacked-not-aligned]

warning: alignment 1 of 'struct _psp_combo_directory' is less
 than 16 [-Wpacked-not-aligned]

In function 'find_register_fw_filename_bios_dir':
warning: implicit conversion from 'enum _amd_fw_type' to
'amd_bios_type' {aka 'enum _amd_bios_type'} [-Wenum-conversion]

BUG=None
TEST=Build and verify binaries are identical.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I761d9893ac6737b42af96c4b2a57c5a4fc61ab05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-16 08:09:35 +00:00
Zheng Bao b993cb2d6c amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73)
Change-Id: Ie3577b403c1de7f20b6d5bcf9e1a5d47450266fe
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-03 13:48:51 +00:00
Patrick Georgi d92d7cb515 util/amdfwtool: Add "all" target to Makefile
The test-tools make target requires it.

Change-Id: I20819f8d587e6b3a472cdc32751e9edf505d5ba6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28 09:27:46 +00:00
Felix Held e862a004d7 util/amdfwtool,post: add missing distclean target
Without this target some spurious errors occurred when running make
distclean at the top level of coreboot.

Change-Id: I3d3061b386fc5b4a043cfc7ff8fd3c0da33c0e83
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49227
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 21:10:51 +00:00
Idwer Vollering 93df1d9cfa util/amdfwtool: portability fixes for FreeBSD
Add the stdint.h header, and drop the GLIBC section from amdfwtool.h to build this tool on FreeBSD as well as Linux.

Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I295fd308b0f5e2902931f02c9455823a614976de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48977
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-31 16:06:58 +00:00
Zheng Bao bf29a0d21f amdfwtool: Add support of cezanne and renoir
Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21 02:34:15 +00:00
Zheng Bao 5caca947b2 amdfwtool: Register APCB and APCB_BK respectively
We took the assumption the APCB(0x60) and APCB_BK(0x68) are the
same file. For picasso, they are. For later programe, they are not.

Change-Id: Idea7847691c2b511b489c306f04a8cb8945fd057
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-11 20:04:02 +00:00
Marshall Dawson 13ec029145 util/amdfwtool: Fix EFS generation polarity
The DWORD used to indicate the Embedded Firmware Structure's generation
uses 1 to indicate a first-gen structure, e.g. a SPI device's erased
value of 0xffffffff.  A 0 in bit 0 is how Client PSPs will interpret
the structure as designed for second-gen.

This change and the original addition should have no effects on
any current products as none interpret offset 0x24.

BUG=b:158755102
TEST=inspect EFS in coreboot.rom

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: If391f356a1811ed04acdfe9ab9de2e146f6ef5fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-11 19:36:23 +00:00
Felix Held ea3417b5eb util/amdfwtool: add missing zero-initialization for local variable
Change-Id: Ib156b16b874f74f58bd816071db3a7acf33c5aaf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47817
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-21 19:40:33 +00:00
Zheng Bao 5014373edd amdfwtool: Move the MP2CFG checking to category of BIOS data
Change-Id: Iaaf9c96dd0ed8c31bb50350d37646ca08a1bbff0
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-17 08:07:12 +00:00
Zheng Bao 3384e4a709 soc/amd: Change FIRMWARE_LOCATE to FIRMWARE_LOCATION
Change-Id: I3a3d187fc24ab752dfe61893c15561a92d009fe2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 09:42:18 +00:00
Zheng Bao 77a2c67dfe amdfwtool: Change all error output to fprintf stderr
Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 09:42:04 +00:00
Zheng Bao 9e90807b40 amdfwtool: Add an option to show debug message
Change-Id: I3e3bcc2c9e1b3edfed1ce845c1603b2a9a2bb044
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-04 09:41:58 +00:00
Patrick Georgi 8aa087ece6 .gitignore: Ignore .test/.dependencies globally
These were originally ignored only inside util/ but these files
shouldn't be tracked anywhere.

Change-Id: Ie0846bd8bdd6e52f420f9dd2e72a8a922102ff90
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-31 18:21:36 +00:00
Zheng Bao c5e28abaf8 amdfwtool: Take a config file instead of command line parameters
To verify the consistency, see if timeless builds with and without
this patch result in identical coreboot.rom files.

BUG=b:154032833
TEST=Build & boot on mandolin

Change-Id: Icae73d0730106aab687486e555ba947796e5e757
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-30 12:10:04 +00:00
Patrick Georgi 6065f616eb .gitignore: Split into subdirectory files
There's no need for the global list of files to ignore, so use git's
ability to work with more local configuration.

Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 07:05:27 +00:00
Zheng Bao 9c8ce3e423 amdfwtool: Remove the assumption of ROM_SIZE
Every platform passes (and need to) the --flashsize to the command
parameter, so we remove the macro definition about a built-time
romsize defined in Makefile.

Change-Id: I894e833ed23a7da38b36986b624e7dcdf1f4090c
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-05 08:37:46 +00:00
Zheng Bao 473969163d amdfwtool: Use a variable to get the return value of write
New Jenkins complaint about the original code that return
value gets to nowhere. Fix that with a new variable.

Change-Id: I8099b856ccb751dc380d0e95f5fe319cc3e2c6cc
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45812
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 08:37:37 +00:00
Zheng Bao 7698a55202 amdfwtool: Clean up the Makefile of amdfwtool
Add Makefile.inc to compliant with other tools.
Makefile is kept for building amdfwtool by typing make
in the folder.

Change-Id: I3688d93de4459f5f838955892086b4b9bf30a9b8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-05 08:37:28 +00:00
Zheng Bao 6d402acbc0 amdfwtool: Fix the gcc warning about sign comparison
New (maybe) compile tool complains the warning below.
warning: comparison between signed and unsigned
integer expressions [-Wsign-compare]
Fix all of them.

Change-Id: I59624326233284e6c3595df49625563254949c45
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-02 16:01:45 +00:00
Martin Roth b1f648fc5c util/amdfwtool: Add PSP verstage signature entry
Add the field for the PSP verstage signature entry.  This adds the
public key signing token to the PSP Directory table to verify the signed
PSP verstage binary

BUG=b:166100797
TEST=Build in a file and verify that it's present with the correct ID.
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7525045d8746b6857979d07b02758ab4d4835026
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03 16:30:14 +00:00
Martin Roth eca423b44f util/amdfwtool: Fix warning taking address of packed struct member
GCC9 introduced a new warning [-Waddress-of-packed-member].  This
is giving the following warning when building amdfwtool: warning: taking
address of packed member of ‘struct _bios_directory_entry’ may result in
an unaligned pointer value. Looking at the definition of the struct, it
looks like this is probably true.

Since the function being called doesn't read from the values, zeroing
them out in the beginning of the function, the code just passes pointers
to the temporary variables without initializing them.

BUG=None
TEST=Build & use AMD firmware table.
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I2f1e0aede8563e39ab0f2ec6daed91d6431eac43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03 16:25:40 +00:00
Martin Roth 48dd9fe21f util/amdfwtool: Refactor APOB_NV requirements
amdfwtool currently assumes that we MUST have an apob_nv area if we
have an aopb.  This is not required, so if neither the apob_nv size or
base are specified, just move on.

BUG=b:158363448
TEST=Build an image with no APOB_NV region.  Dump regions to show that
it's not there.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibaeacd3dcdfd73f690df61c2a19d39bbb9dcc838
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44045
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21 18:46:58 +00:00
Matt Papageorge be4376c6c6 util/amdfwtool: Add support for EFS SPI values for F17h and F15h
The Embedded Firmware Structure contains various SPI parameters for
the PSP to program. This change adds support to amdfwtool for
populating these values as well specifying SOC Family and Model.

BUG=b:158755102
TEST=Read EFS values at appropriate offsets using a hex editor. Boot
test on Tremblye and Morphius.

Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9
Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:06:10 +00:00
Martin Roth 9455474f1b util/amdfwtool: Add option for setting PSP/FW shared memory location
This tells the PSP where in main memory to copy the vboot workbuf.

BUG=b:152576063
TEST=Build sharedmem destination into AMDFW, verify shared memory
gets placed at that location.

Signed-off-by: Martin Roth <martin@coreboot.org>
Original-Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2148830
Original-Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42044
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08 14:19:24 +00:00
Martin Roth 37305e78fc util/amdfwtool: update to allow building in any location
For the verstage-on-PSP implementation, we need 2 additional copies
of the AMD firmware tables at non-standard locations.  These are
for RW-A & RW-B fmap regions.  This change allows us to build the
AMD firmware tables into those regions.

BUG=b:148767300
TEST=boot with psp_verstage, verify boot location

Signed-off-by: Martin Roth <martin@coreboot.org>
Original-Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Change-Id: I2b591b50e9b179fdfaead46ff93722fa2a155e9c
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2144534
Original-Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: I7f841db8617b953dc671a9c12576145f85263581
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-08 14:08:20 +00:00
Rob Barnes 30ce0f383f util/amdfwtool: Fix MAX_PSP_ENTRIES value
Had to increase MAX_PSP_ENTRIES to accommodate the 16 APCBs we have
the ability to add.

BUG=b:150862063
TEST=Boot Trembyle
BRANCH=None

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I64eccfa28839768788f53327caf187a564842162
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2090323
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41580
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21 22:30:27 +00:00