Commit Graph

18762 Commits

Author SHA1 Message Date
Furquan Shaikh 0d9cd92efb chromeos: Clean up elog handling
1. Currenty, boot reason is being added to elog only for some
ARM32/ARM64 platforms. Change this so that boot reason is logged by
default in elog for all devices which have CHROMEOS selected.

2. Add a new option to select ELOG_WATCHDOG_RESET for the devices that
want to add details about watchdog reset in elog. This requires a
special region WATCHDOG to be present in the memlayout.

3. Remove calls to elog add boot reason and watchdog reset from
mainboards.

BUG=chrome-os-partner:55639

Change-Id: I91ff5b158cfd2a0749e7fefc498d8659f7e6aa91
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-28 00:40:03 +02:00
Furquan Shaikh c66a02634c google/urara: Provide dummy implementations of rec/dev functions
This is required to enable elog support in ChromeOS by default.

BUG=chrome-os-partner:55639

Change-Id: I9c97143d794de4bf220ddf67c0ca2eac2f7a326d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15896
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-28 00:39:20 +02:00
Furquan Shaikh faf07a8fab qualcomm/gale: Add required files to enable elog in ramstage
BUG=chrome-os-partner:55639

Change-Id: Idbad4f8763be18002907a62be755b2fdf7e479ec
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15895
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-28 00:38:44 +02:00
Furquan Shaikh a7f11b8ecf qualcomm/storm: Add required files to enable elog in ramstage
BUG=chrome-os-partner:55639

Change-Id: Ie859ec3ff682e91a4d7d38d3c3cd6badf7385431
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15894
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-28 00:38:25 +02:00
Furquan Shaikh 01ac811b08 i2c/ww_ring: Add ww_ring files to ramstage
These files are required by storm and gale boards for enabling elog
support in ramstage.

BUG=chrome-os-partner:55639

Change-Id: I2bbfee2acf2bfe2f896a8619b1276dcea1b87f16
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-28 00:38:09 +02:00
Furquan Shaikh 18b02c5630 google/chromeos: Use vboot bootmode functions for elog add boot reason
BUG=chrome-os-partner:55639

Change-Id: I3ac2b256862758bb5c9e6c2f1311972af474e8f6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15870
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28 00:36:48 +02:00
Furquan Shaikh 0325dc6f7c bootmode: Get rid of CONFIG_BOOTMODE_STRAPS
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and
developer mode check functions to vboot. Thus, get rid of the
BOOTMODE_STRAPS option which controlled these functions under src/lib.

BUG=chrome-os-partner:55639

Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15868
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28 00:36:22 +02:00
Furquan Shaikh 2a12e2e8da vboot: Separate vboot from chromeos
VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use
of verified boot library without having to stick to CHROMEOS.

BUG=chrome-os-partner:55639

Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15867
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 00:36:00 +02:00
Furquan Shaikh af8ef2a810 drivers/intel/fsp2_0: Update MRC cache with dead version in recovery
If the system is in recovery, store the newly generated MRC data using a
dummy version which is not legit. This ensures that on next normal boot,
new MRC data will be generated and stored.

BUG=chrome-os-partner:55699

Change-Id: Ib13e8c978dc1b4fc8817fab16d0e606f210f2586
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15828
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-27 23:53:13 +02:00
Furquan Shaikh c31973760f soc/intel/common: Store MRC data in next available slot in the cache
Currently, coreboot performs an erase of the entire MRC cache region on
flash if there is a version mismatch for the MRC data. Instead of doing
that, store the new MRC data in the next available slot, if there is
enough space available in the cache region.

BUG=chrome-os-partner:55699

Change-Id: Ib24a94f0a47c79941ed9f60095360ae3aad5540b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15915
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-27 23:53:03 +02:00
Aaron Durbin bc24b85e6a mainboard/google/slippy: remove unobtainable mainboard
The slippy board was a proof of concept device that has never
made it out in the wild. Moreover, I don't think any of these
boards exist any longer.

Change-Id: I24fb08d9be35b2367e7aa64520ce5778ab861535
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15902
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-27 21:25:23 +02:00
Aaron Durbin 139314bffd mainboard/google/bolt: remove unobtainable mainboard
The bolt board was a proof of concept device that has never
made it out in the wild. Moreover, I don't think any of these
boards exist any longer.

Change-Id: I5ca055d448659a2b8e2eafcfc2114a6b8f8a56a4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15901
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-27 21:25:06 +02:00
Bora Guvendik 60cc75df83 soc/intel/apollolake: Disable monitor mwait
The monitor/mwait is broken on Apollolake. So use ACPI legacy
mwait IO redirection as a work around

BUG=chrome-os-partner:55110

Change-Id: I2e1834130d9586b4310466d3549d19bf427ffe24
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/15890
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-27 19:36:01 +02:00
Paul Kocialkowski 46114517d7 Rename VB_SOURCE to VBOOT_SOURCE for increased clarity
This renames the VB_SOURCE variable to VBOOT_SOURCE in the build system,
providing increased clarity about what it represents.

Since the submodule itself is called "vboot", it makes sense to use that
name in full instead of a very shortened (and confusing) version of it.

Change-Id: Ib343b6642363665ec1205134832498a59b7c4a26
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/15824
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-27 17:26:05 +02:00
Paul Kocialkowski 94938fb2a8 chromeec: Use CHROMEEC_SOURCE with fallback instead of hardcoding path
This introduces a CHROMEEC_SOURCE variable used for indicating the CrOS
EC source path, with a fallback to 3rdparty/chromeec.

This allows specifying an external path for the CrOS EC source path.

Change-Id: I9792c7f21597127a385b961b65a00d44cfa37146
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/15765
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-27 17:25:49 +02:00
Lee Leahy 5f4b4c4296 arch/x86: Add bootblock and postcar support for SOC MTRR access
Quark does not support the rdmsr and wrmsr instructions.  Use SOC
specific routines to configure the MTRRs on Quark based platforms.
Add cpu_common.c as a build dependency to provide access to the routine
cpu_phys_address_size.

TEST=Build and run on Galileo Gen2

Change-Id: I43b7067c66c5c55b42097937e862078adf17fb19
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15846
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-27 13:50:39 +02:00
Lee Leahy ae738acdc5 cpu/x86: Support CPUs without rdmsr/wrmsr instructions
Quark does not support the rdmsr and wrmsr instructions.  In this case
use a SOC specific routine to support the setting of the MTRRs.  Migrate
the code from FSP 1.1 to be x86 CPU common.

Since all rdmsr/wrmsr accesses are being converted, fix the build
failure for quark in lib/reg_script.c.  Move the soc_msr_x routines and
their depencies from romstage/mtrr.c to reg_access.c.

TEST=Build and run on Galileo Gen2

Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15839
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-27 13:50:11 +02:00
Damien Zammit 7c2e5396a3 nb/intel/x4x: Fix CAS latency detection and max memory detection
Now hardcode maximum memory frequency capability to 800MHz, as
all chipsets in x4x family support PC2-6400 according to the datasheet.
CAS latency detection also relies on this, and has been cleaned up.

Ram initialization does not work with FSB 1333MHz / DDR2 800MHz combination,
so disable this combination for now, and reduce to 667MHz instead.
Still don't know why this is the case, but FSB1333/667 works.

These changes should now allow existing configurations to continue working,
while providing support for previously unworking configurations, due to
previous buggy CAS latency detection code.

TESTED: on GA-G41M-ES2L
CPU: E5200 @ 2.50GHz (FSB 800MHz)

2x 1GB 667MHz hynix	worked @ 667
1x 2GB 800Mhz ARAM	worked @ 800
1x 1GB 667Mhz StarRam	worked @ 667
2x 2GB 800Mhz (generic)	worked @ 800

Change-Id: I1ddd7827ee6fe3d4162ba0546f738a8f9decdf93
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/15818
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-27 11:40:33 +02:00
Aaron Durbin 40d93494c3 device: include devicetree in bootblock stage
Allow bootblock to get access to the static device tree like
other early stages. device_romstage.c was renamed to
device_simple.c to better articulate the usage since it's not
just being used in romstage.

BUG=chrome-os-partner:55357

Change-Id: I3d63d2754c737cc738c09a3e3b3b468362fb78d1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15837
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins)
2016-07-27 00:40:05 +02:00
Aaron Durbin 9cbc90a1f6 soc/nvidia/tegra124: remove cache_policiy option
All mainboards (nyans) utilizing the cache_policy option
has it set to DCACHE_WRITETHROUGH. This option is for setting
the framebuffer's cache attribute. However, this option is
reliant on an architecture-specific enumeration. Just remove
the option and use DCACHE_WRITETHROUGH across the board. If
someone wants to reconfigure it at a later date one can
introduce a non-architecture specific option.

Change-Id: I6a0848231f5e28d36ec2d56b239bed67619fe5a7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15838
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-07-27 00:39:48 +02:00
Lee Leahy aa3e8a8124 drivers/intel/fsp2_0/header_util: Convert UPD headers
Convert the FSP 2.0 UPD headers from typedef to struct:
* FSP_UPD_HEADER
* FSPM_ARCH_UPD

TEST=Build and run on Galileo Gen2

Change-Id: Iab241ea07c955e95ff988a4a30103d2a112179b6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15856
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26 23:23:31 +02:00
Martin Roth c7dfbe26fd google/oak: dsi: set mipi pin driving control on
We set this driving control to prevent signal attenuation caused by
LVDS DRV termination.

When DA_LVDSTX_PWR_ON is not set, LVSH has no power and LVDS DRV
termination status is unknown(floating). This creates a chance that MIPI
output would be influenced. The DSI's LP signal will be half voltage
attenuation. There will be no display on panel.

When DA_LVDSTX_PWR_ON is set, LVSH and LVDS DRV termination are
effective and termination is fixed OFF. The DSI won't be influenced.

We only need to set this register once, so we set it here to prevent
repeat setting in the kernel when the system goes to recovery mode.

BUG=chrome-os-partner:55296
BRANCH=none
TEST=build pass elm and show ui

The original commit in the cros repo combined the chipset and mainboard
code changes.  This has been split for the push to coreboot.org

Change-Id: I733bdd115950b71493856220414ac0dd75d28122
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0d25a27f300acc4b65a894110d3ee0cc9676cd12
Original-Change-Id: Ie71f9cc41924787be8539c576392034320b57a49
Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/360850
Original-Commit-Ready: jitao shi <jitao.shi@mediatek.com>
Original-Tested-by: jitao shi <jitao.shi@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15808
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-26 17:48:56 +02:00
Jitao Shi 700b03962b meditek/mt8173: dsi: set mipi pin driving control on
We set this driving control to prevent signal attenuation caused by
LVDS DRV termination.

When DA_LVDSTX_PWR_ON is not set, LVSH has no power and LVDS DRV
termination status is unknown (floating). This creates a chance that
MIPI output would be influenced. The DSI's LP signal will be half
voltage attenuation. There will be no display on panel.

When DA_LVDSTX_PWR_ON is set, LVSH and LVDS DRV termination are
effective and termination is fixed OFF. The DSI won't be influenced.

We only need to set this register once, so we set it here to prevent
repeatedly setting in the kernel when the system goes to recovery mode.

BUG=chrome-os-partner:55296
BRANCH=none
TEST=build pass elm and show ui

Change-Id: Ie3ccf6fb611dd5a1e2c02b7825d42a92e61268c0
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0d25a27f300acc4b65a894110d3ee0cc9676cd12
Original-Change-Id: Ie71f9cc41924787be8539c576392034320b57a49
Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/360850
Original-Commit-Ready: jitao shi <jitao.shi@mediatek.com>
Original-Tested-by: jitao shi <jitao.shi@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15807
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-26 17:48:38 +02:00
Lee Leahy 4cfde2a389 arch/x86: Generate a map file for the postcar stage
Place a map file for the postcar stage and place it into
build/cbfs/fallback.

TEST=Build and run on Galileo Gen2

Change-Id: I349c06e3c610db5b3f2511083208db27110c34d0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15845
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26 16:16:37 +02:00
Lee Leahy 99f1b2f755 arch/x86: Organize ramstage to match other stages
Move the ramstage files to the beginning of the section.  Eliminate
duplicate conditionals.

TEST=Build and run on Galileo Gen2

Change-Id: I461a5b78a76bd0d2643b85973fd0a70bc5e89581
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15892
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26 16:15:24 +02:00
Lee Leahy e82b5057e3 arch/x86: Move romstage files into romstage section
Move the romstage files into the romstage section of the file.
Eliminate duplicate conditional statements.

TEST=None

Change-Id: Ie2d65cef3797a2c091c0cd76b147b30a765332ad
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15891
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-26 16:14:53 +02:00
Lee Leahy a7491502dc arch/x86: Move postcar stage commands into place
Move the postcar commands to in between romstage and ramstage.  Add the
stage header.

TEST=Build and run on Galileo Gen2

Change-Id: I530da6afd8ccbcea217995ddd27066df6d45de22
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15844
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26 16:14:15 +02:00
Aaron Durbin 49d233006b drivers/elog: put back 4KiB limit
The removal of ELOG_FLASH_BASE and ELOG_FLASH_SIZE resulted
in the FMAP region for the eventlog to be honored. However,
certain systems seem to have a large eventlog region that
wasn't being used in practice. Because of the malloc() in the
eventlog init sequence a large allocation was now being requested
that can exhaust the heap. Put back the 4KiB capacity until
the resource usage is fixed.

BUG=chrome-os-partner:55593

Change-Id: Ib54b396b48e5be80f737fc3feb0d58348c0d2844
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15835
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-26 15:35:37 +02:00
Kyösti Mälkki dc4820baed intel car: Use MTRR WRPROT type for XIP cache
XIP cachelines contain the executable to run, we never want
that to get modified. With the change such erronous writes
are ignored and next cacheline miss will fetch from boot
media (SPI / FWH flash).

Change-Id: I52b62866b5658e103281ffa1a91e1c64262f3175
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15778
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26 12:38:01 +02:00
Kyösti Mälkki 9551bed306 intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
Match the definition and use of these variable with haswell, such that
DCACHE_RAM_MRC_VAR_SIZE is not included in DCACHE_RAM_SIZE.

Change-Id: I5af20f63cd0cb631d39f7c7fe0e2a99ebd3ce986
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15761
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26 07:09:24 +02:00
Lee Leahy d950f5191d lib: Don't require ULZMA compression for postcar
The build fails during postcar when ULZMA compression is not selected.
Fix cbfs.c to support LZ compression for ramstage as well.

The build error is:
build/postcar/lib/cbfs.o: In function `cbfs_load_and_decompress':
/home/lee/coreboot/public/src/lib/cbfs.c:116: undefined reference to
`ulzman'
make: *** [build/cbfs/fallback/postcar.debug] Error 1

TEST=Build and run on Galileo Gen2

Change-Id: I7fa8ff33c0d32e0c5ff5de7918e13e6efb1df38e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15841
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26 04:53:33 +02:00
Lee Leahy 27cd96a661 drivers/intel/fsp2_0: Enable XIP romstage with loaded FSP-M
Separate NO_XIP_EARLY_STAGES from loading FSP-M into cache-as-RAM.
Quark executes romstage directly from the SPI flash part (in-place),
but loads FSP-M into ESRAM.  This split occurs because ESRAM is too
small to hold everything while debugging.

Platforms executing FSP-M directly from the SPI flash need to select
FSP_M_XIP.

TEST=Build and run on Galileo Gen2.

Change-Id: Ib5313ae96dcec101510e82438b1889d315569696
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15848
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26 01:21:58 +02:00
Lee Leahy e2422e38ce src/lib: Enable display of cbmem during romstage and postcar
Enable the display of cbmem during romstage and postcar.  Add a Kconfig
value to prevent coreboot images from increasing in size when this
feature is not in use.

TEST=Build and run on Galileo Gen2

Change-Id: Ib70ad517ebf7d37a7f46ba503b4432c7c04d7ded
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15842
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26 01:18:09 +02:00
Lee Leahy 3eabe6e9ec drivers/uart: Enable debug serial output during postcar
Build the UART drivers for the postcar stage.

TEST=Build and run on Galileo Gen2

Change-Id: I8bf51135ab7e62fa4bc3e8d45583f2feac56942f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15843
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 23:28:32 +02:00
Furquan Shaikh b8257df83b intel/skylake: Select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
This allows the board to save the recovery request in case of unexpected
reboots caused by FSP.

With recovery module in vboot handling the saving of recovery reason
across reboots, there is no need to have special fsp reset handling
under soc.

BUG=chrome-os-partner:55431

Change-Id: I0b7ce14868a322072d3e60c1dae43f211b43fdbf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15804
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 18:58:38 +02:00
Furquan Shaikh 7c7b291e55 intel/apollolake: Select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
This allows the board to save the recovery request in case of unexpected
reboots caused by FSP.

BUG=chrome-os-partner:55431

Change-Id: If71802d2cba52a426f4c2db90d6c5384ed03ce68
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15803
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-25 18:58:03 +02:00
Lin Huang 9dc00ef625 rockchip/rk3399: set CA drive strength to 48ohms
As shown in testing, if CA use 34.3ohms drive strength, it leads
to an overshoot. To fix this, change the drive strength to 48 ohms.

BRANCH=none
BUG=chrome-os-partner:54871
TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass

Change-Id: I8666474fc18391da14a3338611f962f2f08f36d0
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: fbc1c13f9ab808fc907b2e3f9bde1d09f92980f1
Original-Change-Id: I231f5b1bd45ff262686fbacbaf119a8a57fad27b
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/358761
Original-Commit-Ready: Dan Shi <dshi@chromium.org>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15811
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-25 18:57:55 +02:00
Julius Werner de110ee07d google/gru: Change UART _Static_assert() condition to #if
_Static_assert() gets evaluated even when the code path it's in is
unreachable (e.g. inside an if (0) block). Unfortunately, Kconfigs that
depend on a disabled Kconfig are always 0, meaning that
CONFIG_CONSOLE_SERIAL_UART_ADDRESS on Gru cannot evaluate to UART2 when
CONFIG_CONSOLE_SERIAL (which it depends on) is disabled. Switch the
condition it is wrapped in to a preprocessor #if so that the
_Static_assert() is not evaluated when building without serial support.

BRANCH=None
BUG=None
TEST=Built and booted Kevin without serial

Change-Id: I391325fcc4b7d64b4866a7fce4444e2f28365b7d
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: f5e5cf0644154eca5b347ea381df3f6b28287524
Original-Change-Id: I33d51d4ef09b218c14173d39a12795f0cef6bb40
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/361581
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15810
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-25 18:57:32 +02:00
Furquan Shaikh 85aa135326 google/chromeos: Add support for saving recovery reason across reboot
On some x86 platforms (skylake, apollolake), we observe reboots at
different steps during the FSP initialization. These additional reboots
result in loss of recovery request because vboot_reference library
clears recovery request on vbnv once verification is complete and it has
made a decision about which boot path to take(normal/dev, slot-a/slot-b,
recovery).

Provide a way to allow mainboards/chipsets to inform recovery module in
vboot2 to save recovery reason to survive unexpected reboots. The
recovery reason is set in vbnv after vboot_reference library completes
its verification and clears the reason in vbnv while jumping to
payload.

BUG=chrome-os-partner:55431

Change-Id: Ie96be9aeb42c8209d8215943409e6327d6a8bf98
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15802
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 18:57:15 +02:00
Kan Yan 041bc76386 google/gale: Fix board ID and GPIO config.
Fix the board ID handling.
Recovery switch and WP status GPIO has been reassigned in board rev3.
Configure related GPIOs based on Board ID.

BUG=chrome-os-partner:55320
TEST=Verified GPIO assignment for Rev.1 board.
BRANCH=None

Change-Id: Id8e1ba1c039f8b5b503f0da038e5cfc84b72678f
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: d295ab514e31d9ebd1b77e0af9b769e64cbf567e
Original-Change-Id: I6d3d5df2e9017f7845edc3cd0b2c19ad7c58a97c
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/361393
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/15809
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-25 18:56:58 +02:00
Furquan Shaikh 8edfc1c512 lib/bootmode: Use newly-add recovery module
Use the newly added check recovery request function from recovery module
in vboot2 to check for a pending recovery request.

BUG=chrome-os-partner:55431

Change-Id: I354cc094f1e5d0044cf13e5bc28246f058d470c6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15801
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-25 18:56:06 +02:00
Furquan Shaikh 6d448e3aa6 google/chromeos: Add recovery module in vboot2
Add recovery module in vboot2 that checks if a recovery request is
pending and returns appropriate reason code:
1. Checks if recovery mode is initiated by EC.
2. Checks if recovery request is present in VBNV.
3. Checks if recovery request is present in handoff for post-cbmem
stages.
4. Checks if vboot verification is complete and looks up selected region
to identify if recovery is requested by vboot library.

BUG=chrome-os-partner:55431

Change-Id: I31e332a4d014a185df2434c3730954e08dc27281
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15800
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-25 18:55:51 +02:00
Furquan Shaikh a6c5ddd595 vboot: Clean up vboot code
1. Remove unused functions/structures.
2. Add checks for NULL return values.
3. Change prefixes to vb2 instead of vboot for functions used internally
within vboot2/
4. Get rid of vboot_handoff.h file and move the structure definition to
vboot_common.h
5. Rename all functions using handoff structure to have prefix
vboot_handoff_*. All the handoff functions can be run _only_ after cbmem
is online.
6. Organize vboot_common.h content according to different
functionalities.

BUG=chrome-os-partner:55431

Change-Id: I4c07d50327d88cddbdfbb0b6f82c264e2b8620eb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-25 18:55:35 +02:00
Furquan Shaikh 610a33a7f4 skylake: Move CHROMEOS config to SoC
All the mainboards share the same config options for CHROMEOS. Instead
of duplicating those in every mainboard, move the CHROMEOS config to SoC
and make it dependent on MAINBOARD_HAS_CHROMEOS.

BUG=chrome-os-partner:55431

Change-Id: Iafabb6373dfe16aaf0fe2cbc4e978952adeb403e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15822
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-25 18:55:21 +02:00
Furquan Shaikh 87b1bcc4af apollolake: Move CHROMEOS config to SoC
All the mainboards share the same config options for CHROMEOS. Instead
of duplicating those in every mainboard, move the CHROMEOS config to SoC
and make it dependent on MAINBOARD_HAS_CHROMEOS.

BUG=chrome-os-partner:55431

Change-Id: I2d54ff6beac9fca7596a8f104e3c1447cada5c05
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15821
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-25 18:55:01 +02:00
Furquan Shaikh b1b465f093 intel/amenia: Add chromeos.c to verstage
BUG=chrome-os-partner:55431

Change-Id: I94fe54c12d7438a71f81a9053cc9785c0aa1e6cf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15823
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 18:54:50 +02:00
Daisuke Nojiri 5dd6a910da google/jecht: Increase RO coreboot size on flash
Bitmap images have been moved to CBFS from GBB. This patch adjusts the flash
size accordingly for jecht.

BUG=chromium:622501,chromium:628494
BRANCH=none
TEST=emerge-jecht chromeos-bootimage
CQ-DEPEND=CL:361380

Change-Id: I941df04b4999d35bd652e4ee1664c032cb550b29
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: c859ce04d2df5f21c47a164cabbc9ef6dec61818
Original-Change-Id: I50a9ade2e90237b0a7c277bffd7b540132415f13
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/361370
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15806
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-25 18:54:01 +02:00
Subrata Banik 168eb6ad6f Makefile: Add uCode binary to FIT
Currently, on Intel Skylake the uCode binary is added to
CBFS based on the config option CBFS_EXTERNAL_HEADER. But
the entry is missing into the Firmware Interface Table, so
add it there.

BRANCH=none
BUG=chrome-os-partner:55403, chrome-os-partner:53077
TEST=built and verified FIT table has ucode entry.

Change-Id: I7dd7459ff7d2468f0aff66eb3ee9c2e3d7eda501
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15783
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-24 00:09:14 +02:00
Duncan Laurie 1e4c091e9b google/reef: Enable PS/2 keyboard driver by default
This device has a built-in keyboard that should be enabled by default
or it will not work in firmware.  This was tested to ensure that TAB
(display info) and Ctrl+D (enter developer mode) are functional at the
Chrome OS recovery screen.

BUG=chrome-os-partner:55549

Change-Id: I60156f1fc001b88deac69e03e02e9d8277fbc38d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15782
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-24 00:08:51 +02:00
Aaron Durbin 2c29d34b37 soc/intel/apollolake: ensure usb port 0 is in host mode
The controller for device mode USB is not plan of record
on apollolake. However, one still needs to configure the
one port to be host mode by default such that the devices
work as expected when plugged into the board.

BUG=chrome-os-partner:54581,chrome-os-partner:54656
TEST=Enabled xdci controller. Used USB type C->A dongle to
     check that a mass storage device worked on port 0 on
     reef.

Change-Id: Ia9ec5076491f31bc5dc3d534e235fb49f7b2efac
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15781
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-24 00:08:22 +02:00