Commit Graph

40691 Commits

Author SHA1 Message Date
Patrick Rudolph 52ef869b94 mb/prodrive/hermes/mb: Update SoC config in PRE_DEVICE
As one option is consumed by MPinit, update the soc config even earlier.

Tested on Prodrive hermes:
Turbo can be disabled and cores won't exceed their base frequency.

Change-Id: I9f444c3b91d2ee1a613ebac1922f1e6b60363c0b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-24 11:27:03 +00:00
Arthur Heymans e1152c401a mb/lenovo/x220: Increase MMIO space
With an external GPU connected via the expresscard slot this is
required.

Change-Id: I154721ff2c712cfe7eb79b8bf8943182c8c36548
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-24 10:41:51 +00:00
Kyösti Mälkki 813b2f030d mb/amd,google: Rename static functions to mainboard_enable
Let's not have 7 boards of all use a different name for
the .enable_dev function in mainboard chip_operations.

Change-Id: I07f3569e6af85f4f1635595125fe2881ab9ddd43
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-24 10:00:21 +00:00
Kyösti Mälkki 32b99169a5 mb/amd,google/zork: Move init_tables() call
The semantics of pirq_setup() from previous platforms was to
only setup the global pointers for PIC and APIC tables, not
to create or modify the tables themselves.

Change-Id: Iaa7c31eed21432dc2b3fe6b32803bd2658fd5e2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-24 10:00:02 +00:00
John Zhao 2c7842407a soc/intel/tigerlake: Remove polling for Link Active Status at resume
Tigerlake TBT only has SW CM support. The polling for "LA == 1" is not
applicable for SW CM platform at the resume sequence. This change
removes the pollng for "LA == 1" to improve resume performance.

BUG=b:177519081
TEST=Boot to kernel and validated s0ix on Voxel board.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I886001f71bf893dc7eda98403fa4e1a3de6b958e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-23 22:14:04 +00:00
Angel Pons 83e6c15b0e Doc/releases/checklist.md: Clarify tag push command
Change-Id: I0a6d1ed014c6454c4bde390283351c19fe097201
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47813
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-23 17:25:59 +00:00
Jakub Czapiga eb4bb6f563 tests: Add lib/memcpy-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I00464ec2db23867712cd2efd7f6cad92e3ee361a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-02-23 17:12:52 +00:00
Jakub Czapiga 168b38bbb3 tests: Add acpi/acpigen-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Icc128212c1f72beb50caca671b4bada3507d3a1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-23 17:10:10 +00:00
Kevin Chiu 5b3e995710 mb/google/zork: update USB 3 controller phy Parameter for gumboz
Recommendation from SOC to config IQ=8 for U3 port0,
vboost for all U3 ports for passing ESD pin test.

BUG=b:173476380
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. run U3 SI/ESD pin test => pass

Change-Id: I0e6414f686a995536a0fd8aa0f6f70e5a36718a3
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50992
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-23 15:43:28 +00:00
Kevin Chiu dfd52bd466 mb/google/zork: Adjust Gumboz H1 I2C CLK
Adjust H1 I2C CLK:
404kHz -> 391 kHz

BUG=b:179753353
BRANCH=zork
TEST=1. emerge-zork coreboot chromeos-bootimage
     2. power on proto board successfully
     3. measure i2c freq by scope is close to 400kHz

Change-Id: Iedd47dd6fc4f7ac7f0aac480d63ddbdf85a84ec2
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-02-23 15:42:45 +00:00
Ian Feng 5273322f73 mb/google/dedede: Export EC_IN_RW GPIO to payload
Set up EC_IN_RW GPIO in coreboot.

BUG=b:180686277
TEST=Verified that EC_IN_RW signal is read correctly in depthcharge.

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Ic41012d3d4843dcab0f6dd9c28396cb9d5c49f08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-23 15:38:48 +00:00
Kyösti Mälkki 85a967f248 AGESA fam16 boards: Drop obsolete picr_data and intr_data
Change-Id: I367f6f17fff3d10be19a83d63e927959068408dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-23 07:46:25 +00:00
Kyösti Mälkki 10de874e9f sb/amd/common: Drop dummy variable assigment
Change-Id: I9b523bda2332859074d2e12c5cb70df68e18063d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-23 07:46:11 +00:00
Kyösti Mälkki 5e82d443aa sb/intel/lynxpoint: Refactor some GNVS
Change-Id: I9524a44f8f4b8e286229d81d10704438f11c4580
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23 05:58:18 +00:00
Aamir Bohra 01ae4a7706 intel/fsp2_0: Fix the mp_get_processor_info
FSP expects mp_get_processor_info to give processor specfic apic ID,
core(zero-indexed), package(zero-indexed) and thread(zero-indexed) info.
This function is run from BSP for all logical processor, With current
implementation the location information returned is incorrect per logical
processor. Also the processor id returned does not correspond to the
processor index, rather is returned only for the BSP.

BUG=b:179113790

Change-Id: Ief8677e4830a765af61a0df9621ecaa372730fca
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50880
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-23 03:39:54 +00:00
Aamir Bohra d192590e29 intel/common/block/cpu: Add APIs to get CPU info from lapic ID
Add support to get core, package and thread ID from lapic ID.
Implementation uses CPUID extended topology instruction to derive
bit offsets for core, package and thread info in apic ID.

BUG=b:179113790

Change-Id: If26d34d4250f5a88bdafacdd5d56b8882b69409e
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-23 03:39:47 +00:00
Kyösti Mälkki c92c5e5450 nb/intel/ironlake: Drop redundant clear of SLP_TYP
Bits are already cleared in southbridge_detect_s3_resume().

Change-Id: If8bb85abacd59c7968876906e126300c9e4314e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23 02:37:09 +00:00
Kyösti Mälkki 3051a9ecfa nb/intel/x4x: Use a variable for s3resume
This helps towards unified chipset_power_state.

Change-Id: I8f152dc9f1e0f26e4777489913e9fb2c9cd3dac0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23 02:36:55 +00:00
Kyösti Mälkki b33c6fbfd5 nb/intel/x4x,sandybridge: Move INITRAM timestamps
Let's not have CBMEM hooks in between the different
INITRAM timestamps.

Change-Id: I46db196bcdf60361429b8a81772fa66d252ef1a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23 02:36:36 +00:00
Kyösti Mälkki 4ce0a07f06 nb/intel/x4x,sandybridge: Move romstage_handoff_init() call
Change-Id: I6356bb7ea904ca860cbedd46515924505d515791
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23 02:35:53 +00:00
Kyösti Mälkki b6fc13b3db nb/intel/haswell: Use cbmem_recovery()
For consistency with other nb/intel rename variable from
wake_from_s3 to s3resume.

Change-Id: If94509c4640f34f2783137ae1f94339e6e6cf971
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23 02:35:34 +00:00
Kyösti Mälkki 74cb3e7869 soc/intel/broadwell: Use cbmem_recovery()
For consistency with other soc/intel add s3resume variable,
this helps towards unified chipset_power_state.

Change-Id: I34a123f9fc13bd86264317c7762bf6e9ffd0f842
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23 02:35:21 +00:00
Kyösti Mälkki c5c3e3c594 soc/intel/baytrail: Use cbmem_recovery()
For consistency with other soc/intel add s3resume variable,
this helps towards unified chipset_power_state.

Change-Id: Ida04d2292aabb5a366f3400d8596ede0dee64839
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23 02:35:08 +00:00
Kyösti Mälkki 6ceec167f5 soc/intel/baytrail: Use a variable for s3resume
This helps towards unified chipset_power_state.

Change-Id: I532384ad6c5b2e793ed70f31763f2c8873443816
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23 02:34:47 +00:00
xuxinxiong cdb5b56303 mb/google/oak: Add new DRAM modules K4E6E304EC-EGCG-4GB
Samsung  K4E6E304EC-EGCG-4GB   # 1011

BUG=b:179455694
BRANCH=oak
TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge,
update FW to DUTs,these DUTs can pass stress test under run-in.

Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Change-Id: I02cc34157fd03edb7d715a23ed404abc40ef8ccc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50978
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-23 02:27:35 +00:00
Felix Held a09559501c drivers/intel/fsp2_0/memory_init: check if UPD struct has expected size
If the UPD size in coreboot sizes mismatches the one from the FSP-M
binary, we're running into trouble. If the expected size is smaller than
the UPD size the FSP provides, call die(), since the target buffer isn't
large enough so only the beginning of the UPD defaults from the FSP will
get copied into the buffer. We ran into the issue in soc/amd/cezanne,
where the UPD struct in coreboot was smaller than the one in the FSP, so
the defaults didn't get completely copied.

TEST=Mandolin still boots.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia7e9f6f20d0091bbb4abfd42abb40b485da2079d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-23 01:32:14 +00:00
Kane Chen ca5ed4879f mb/google/zork/var/shuboz: Adjust GPIO settings
1. GPIO_4 to NC

BUG=b:179333669
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I4342b2beb7fc755bee47ee4fad0023d7a6592c4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50277
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-23 01:14:58 +00:00
Nick Vaccaro 202b1899dc soc/intel/tigerlake: Enable end of post support in FSP
Send end of post message to CSME in FSP, by selecting EndOfPost
message in PEI phase. In API mode which coreboot currently uses,
sending EndOfPost message in DXE phase is not applicable.

BUG=b:180755397
TEST=Extract and copy MEInfo tool from CSME Fit Kit to voxel, execute
  ./MEInfo | grep "BIOS Boot State"
and confirm response shows BIOS Boot State to be "Post Boot".

Change-Id: I1ad0d7cc06e79b2fe1e53d49c8e838f4d91af736
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51012
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 23:20:32 +00:00
Ritul Guru 3e945f1a23 mb/amd/bilby: updating EC FW specific options for bilby
EC does not exist in Bilby platform, so removing EC size from board.fmd
and updating bilby fmap size to 0xfef000.
Removing unused EC FW config options MANDOLIN_HAVE_MCHP_FW and
MANDOLIN_MCHP_FW_FILE.

Change-Id: I9ca4e421b0d80d041ed4046fa20cc16e24a776d0
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-22 16:00:41 +00:00
Kyösti Mälkki c79fc4737d mb/emulation: Drop cbmem_recovery(0) call in ramstage
Calling cbmem_recovery(0) late in ramstage would appear
to remove all CBMEM entries created so far.

Change-Id: I2abb079844c4b41be09354d603ad36e4a56ea2e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50841
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 07:39:39 +00:00
Angel Pons 70243cd801 Revert "lynxpoint: Fix SerialIO ACPI compile issue with recent IASL"
This reverts commit 1a25c9cdfd.

Reason for revert: No longer necessary.

Change-Id: I8adeeebd6e841ef2c878622559dcd15848969842
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46955
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 07:37:26 +00:00
Angel Pons 3b8ddee47f configs/config.asrock_b85m_pro4...: Build-test ASan
This build-tests ASan support for both romstage and ramstage, because
the Haswell northbridge selects the HAVE_ASAN_IN_ROMSTAGE option. x86
Kconfig selects the HAVE_ASAN_IN_RAMSTAGE option, and Haswell is x86.

Change-Id: I892881d2315c09aa6d9d80903a8399d0f4d648e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-22 07:33:11 +00:00
Angel Pons cf0cd65038 nb/intel/sandybridge: Remove stale FIXME about ECC support
Change-Id: Id0c45ff1ee4a2dc4c0f9a82f6a311f7acac156fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-22 07:32:37 +00:00
Tim Wawrzynczak 052e439318 mb/google/brya: Fix chip driver and HID for Cr50 TPM
ChromeOS does not compile in CONFIG_OF, so PRP0001 will not successfully
register the device with its driver. Change to GOOG0005 to match other
ChromeOS devices with I2C-connected Cr50 TPM.

BUG=b:180657076
TEST=abuild

Change-Id: Ic1d4eb5e12ea7f7e693f1ffd3848e59668ac2deb
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50920
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 07:32:06 +00:00
Jakub Czapiga cc7acb82c0 tests: Add lib/memchr-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Idcc824bfd9ca950f377c8f6a5916ffaba450fe73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-02-22 07:31:06 +00:00
Raul E Rangel d75ee46d3c soc/amd/picasso/acpi: Change PCI0 BAR window
Picasso currently declares the BAR region between TOM and IO_APIC_ADDR.
This region includes MMCONF. We don't want to map any PCI BARs in this
region. This also matches what intel does.
See soc/intel/braswell/acpi/southcluster.asl for an example.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9474fd6ac75a7245b3c35151c38186e913219bb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-22 07:29:41 +00:00
Raul E Rangel 0b123dd72e soc/amd/cezanne/acpi: Add pci0.asl
This differs slightly from picasso. The PCI BAR region is between TOM1
and CONFIG_MMCONF_BASE_ADDRESS. This matches what the Intel platforms
are doing. It also matches what linux derives from the e820 tables:

> [mem 0xd0000000-0xf7ffffff] available for PCI devices

Picasso currently declares the region between TOM and IO_APIC_ADDR.
This region includes MMCONF. We don't want to map any PCI BARs in this
region.

TEST=Boot majolica and check logs
pci_bus 0000:00: root bus resource [io  0x0000-0x0cf7 window]
pci_bus 0000:00: root bus resource [io  0x0d00-0xffff window]
pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff]
pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff]
pci_bus 0000:00: root bus resource [mem 0xd0000000-0xf7ffffff]
pci_bus 0000:00: root bus resource [bus 00-3f]

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4ff02012795e2166e3a4197071b1136727089318
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50893
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 07:29:31 +00:00
Raul E Rangel 58a8ad1661 soc/amd: Move root complex SSDT TOM1/TOM2 generation function
This will also be used for cezanne. Stoney also has a similar function,
but it hard codes the scope path. I didn't have a device setup to test
if switching to this function was a no-op. So I left it.

TOM2 isn't used by any ASL, so we could remove it later.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7c8f476a7735fea61a3244b97988e3ead3b42e79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-22 07:29:19 +00:00
Raul E Rangel bde284b585 soc/amd/cezanne/acpi/soc.asl: Add platform.asl
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I01adba010bfad1bb4fdf20a8d0ab22aeeebeb10a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-22 07:29:09 +00:00
Raul E Rangel 980721b3ed soc/amd/cezanne/acpi: Add MMIO devices
The devices were copied from picasso with the following modifications:
* UART{2,3} were deleted
* I2C{0,1} were added
* eMMC was removed since it hasn't been validated

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iddfb975e9292785d0951dd7bb31c1997d2185abd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-22 07:29:01 +00:00
Mathew King 1156acbb7e mb/google/guybrush: Enable console UART
BUG=b:180530492
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I468d76d0e061431bc819ec12978203614bfe72b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50919
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 07:28:37 +00:00
Mathew King 86a2324ee0 mb/google/guybrush: Enable guybrush variant
Enable the building of guybrush variants and configure the first variant
also called guybrush.

BUG=b:180419462
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I3bed620378f9152277b4943ead1017f61a21ea82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50845
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 07:28:26 +00:00
Mathew King 5d47887965 mb/google/guybrush: Enable ACPI tables
BUG=b:180419454
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I1e724e78b5ef378d474063417aa2b7e57a00886f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-22 07:28:18 +00:00
Subrata Banik 40f53f4b87 mb/intel/adlrvp: Add support for LP5 SKU with boardid 0x17
Change-Id: I4f17f9d58d2c07264d7d8e83a6fce832c9304c24
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-22 07:26:14 +00:00
Wisley Chen cbcae2744a mb/google/dedede/var/drawcia: Configure IRQ as level triggered for elan_ts
Follow elan's suggestion to configure IRQ as level trigger.

BUG=b:180570924
BRANCH=dedede
TEST=emerge-dedede coreboot

Change-Id: I292670580b4c2c18ed0c20a9fbb4ad4289f4eca6
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-22 07:25:50 +00:00
Angel Pons a3868296ce nb/intel/ironlake: Do not call `collect_system_info` twice
Move wait for TXT and early ME init out of `collect_system_info`, and
then drop the first call to it. Also drop a useless register read.

Tested on out-of-tree HP 630, still boots.

Change-Id: I9b167f44cbd96864bf1e8b616576af19cbbfd90c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49581
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 07:25:37 +00:00
Angel Pons e9fa37894e soc/intel/xeon_sp: Define all SMI_STS bits
As per document 336067-007US (C620 PCH datasheet), add macros for all
bits in the SMI_STS register. These will be used in common code.

Change-Id: I1cf4b37e2660f55a7bb7a7de977975d85dbb1ffa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50915
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 07:25:09 +00:00
Angel Pons 12e2e0e609 arch/arm/armv7/thread.c: Remove stale file
This file is never built. Plus, `CONFIG_STACK_BOTTOM` does not exist.

Change-Id: I111b20e3443dca701ee8666d44261a00a161d83f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-02-22 07:24:26 +00:00
Angel Pons 5276c34654 mb/amd/padmelon: Drop unnecessary `PADMELON_SOC_IN_USE` option
The SoC can be selected in the corresponding option choices directly.

Change-Id: I226c500dd7370f4610b0117a9e70d727f1d66951
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-22 07:24:12 +00:00
Angel Pons 3d695d2e6a mb/google/oak: Clean up TPM Kconfig
Rowan was the only Oak variant that used TPM2. However, it was removed
in commit 0aa1f9e905 (google/oak: Delete rowan). Since the other three
variants use TPM1, remove now-unnecessary Kconfig options from Oak.

Change-Id: If19df00463f63f1101475f59b5ecea5a9724a9ab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-02-22 07:23:58 +00:00