Bring from coreboot v1 support for initializing L2 cache on Slot 1
Pentium II/III CPUs, code names Klamath, Deschutes and Katmai.
Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with
Pentium III 600MHz, Katmai core.
Also add missing include of model_68x in slot_1, to address a
similar problem fixed for model_6bx by r5945.
Also change Deschutes CPU init sequence to match Katmai.
Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: http://review.coreboot.org/122
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ib6cd82badeb6401e065ee14c2a04c78f61a87dd4
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/130
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
crossgcc also needs lzma support as w32api is distributed in .tar.lzma
Change-Id: Ia1938fa30262fe0c8bd655a08f9dc731a02e46ba
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/120
Tested-by: build bot (Jenkins)
We test for the presence of a couple of tools and even print an error.
But the tool didn't stop there.
Change-Id: I40dcf7894408ea7b24d5f68c76df4b7541f469bd
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/111
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This change adds xhci and ahci bios rom handling that
is similar to the vgabios rom handling in the arch/x86
Makefile.inc to the Persimmon and Torpedo mainboards.
It also adds the basis for AHCI BIOS rom handling to
the Persimmon Kconfig.
Change-Id: I527a906323ae483cfa2ca0785f3adb43e88fd84b
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/109
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This set adds support for the SuperMicro H8QGI mainboard.
It is a publicly available 4 socket board using AMD Family
10 cpus and AMD SR5650 and SB700 bridges.
Change-Id: I196704f79db4c45382559c5ee0619dc8d96ff140
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/108
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
This change separates out changes that were initially found
in the commit for XHCI and AHCI changes to "arch/x86/Makefile.
inc". It also corrects a comment. The SSE3 dependent code
adds a pair of CR4 access functions and a blob of code that
re-sets CR4.OSFXSR and CR4.OSXMMEXCPT.
Change-Id: Id97256978da81589d97dcae97981a049101b5258
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/113
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes. The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements. This particular change
affects all mainboards that use the SB700, and their changes are
include herein. These mainboards are:
Advansus a785e,
AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
Asrock 939a785gmh,
Asus m4a78-em, m4a785-m,
Gigabyte ma785gm,
Iei Kino-780am2-fam10
Jetway pa78vm5
Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.
Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
If you would try download FILO via svn, then you probably
get error message about libpayload install. This enables
manually installing libpayload in legacy style :)
Change-Id: I9f52be939303c5913611f21477d681e11d286382
Signed-off-by: Tadas Slotkus <devtadas@gmail.com>
Reviewed-on: http://review.coreboot.org/102
Tested-by: build bot (Jenkins)
Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Change-Id: I419fcb16e0b10dee9195072e0e6befa6c9e61a69
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/105
Tested-by: build bot (Jenkins)
Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change adds the AMD Family 10 cpu support to the
cpu folder. It also updates the makefiles of the Families
12 and 14 to take advantage of a pair of shared files that
are moved to the cpu/agesa folder.
Change-Id: Ibd3a50ea7a3028bd6a2d2583f021506b73e2fce2
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/97
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This change adds the AMD Family 10 cpu support to the northbridge
folder. The northbridge/amd/agesa Kconfig and Makefile.inc are
changed as well.
Change-Id: Id76e9fa388c79ac469a673aaedaa4f1bfd7619d9
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/98
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Neither do we publish coreboot via svn, nor is git-svn a useful indicator
anymore. Instead, fetch a shortened commit id.
Change-Id: I1b990384553209a7d39ecf7f5e8a2db7c7e34d0b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/110
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
I have observed two separate EHCI host bridges that do not tolerate
using C bit-fields to directly manipulate the portsc_t register. The
reason for this is that the EHCI spec says that port_enable must go
to 0 at the time that port_reset goes to 1. Naturally this cannot be
done using direct bit-field manipulation. Instead, we use a temporary
variable, change the bit-fields there, then atomically write the new
value back to the hardware.
Signed-off-by: Steven A. Falco <sfalco@coincident.com>
Change-Id: If138faee43e0293efa203b86f7893fdf1e811269
Reviewed-on: http://review.coreboot.org/101
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
We use LDTSTOP# to trigger the FID/VID change on K8M890, because the
FID/VID SMAF is blocked by not yet configured internal VGA.
The memory controller is enabled later, nor the workaround makes any
harm to non-affected CPUs.
This update unbreaks compilation by declaring the tmp variable.
Change-Id: Icf5d126b8c8cd9ece6af41d3129315a777c8cef2
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/69
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Define INT_MAX, EOF and make sure size_t is available.
Change-Id: I1b4b717d2545ea8312ec52339300307a5bd68f8a
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/104
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change officially adds the Agesa code for the AMD Family 10
cpus. This code supports the G34 and C32 sockets.
Change-Id: Idae50417e530ad40a29fb6fff5b427f6b138126c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/95
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The Intel E6XX Atom processor reports an unknown USB controller type (in
addition to the standard EHCI and OHCI ones). Add a default case to
print a warning when an unknown controller type is detected.
Change-Id: I885d0ccec4c46fd212cceac599290e9bf85edbbb
Signed-off-by: Steven A. Falco <sfalco@coincident.com>
Reviewed-on: http://review.coreboot.org/100
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Move the AMD SB800 early clock setup code that is needed for early
serial port operation from mainboard/romstage.c to sb800/bootblock.c.
This prevents code duplication and simplifies porting.
Change-Id: I615cfec96c9f202d9c154dc6674ec7cbcf4090c3
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/96
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Other USB drivers set the bus_address field. EHCI should do this too.
Signed-off-by: Steven A. Falco <sfalco@coincident.com>
Change-Id: Ic4274c6744951ef7fa0cb135caf8b9f177d8bcaf
Reviewed-on: http://review.coreboot.org/99
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Finally the SMI routines are in good shape on AMD, lets enable this and later
implement ACPI on/off SMI commands.
Change-Id: I9848a7be908780353eead30c16fd2df8ea48f77e
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/83
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Move the SMM MSR init to a code run per CPU. Introduce global SMM_BASE define,
later all 0xa0000 could be changed to use it. Remove the unnecessary test if
the smm_init routine is called once (it is called by BSP only) and also remove
if lock bit is set becuase this bit is cleared by INIT it seems.
Add the defines for fam10h and famfh to respective files, we do not have any
shared AMD MSR header file.
Tested on M2V-MX SE with dualcore CPU.
Change-Id: I1b2bf157d1cc79c566c9089689a9bfd9310f5683
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/82
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The previous code does a full flush of the uart after every character.
Unfortunately, this can cause transmission delays on some serial
ports.
This patch changes the code so that it does a flush at the end of
every printk instead of at the end of every character. This reduces
the time it takes to transmit serial messages (up to 9% on my Asrock
e350m1 board). It also makes the transmission time more consistent
which is important when performing timing tests via serial
transmissions.
Change-Id: I6b28488b905da68c6d68d7c517cc743cde567d70
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Reviewed-on: http://review.coreboot.org/90
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Sven Schnelle <svens@stackframe.org>
It's taken from OpenBSD and thus appropriately licensed (and reasonably
tested).
Change-Id: I5767600c9865d39e56c220b52e045f3501875b98
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/88
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
ec byte 0x03, bit 2 seems to be only used on the X60s for USB switch
initialization. Don't touch it on T60.
Change-Id: Icb89a514757a0e06ccea200fde62a778fa8c268e
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/92
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
On installing/starting Windows (tested with Win7 Ultimate)
the system crashes with a Blue Screen of Death, reporting an ACPI BIOS error.
From Scott Duplichan:
To avoid the Windows BSOD, the uninitialized value TOM1 in the SSDT
must be corrected. The attached patch does this. It uses the older
patching method, and not the (possibly preferred) AML generation
method. To simplify the patching operation, I moved the AML item
'TOM1' to the start of the SSDT. The patch also includes code to
confirm the AML variable TOM1 is at the expected offset before patching.
Also tested & working with Linux.
Change-Id: I59cedc366e09d98f690b093d6a21fc0c864559c3
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/91
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Applying Scott Duplichan's fix for memory >=4GB
Adjusted it to the new directory structure (agesa_wrapper was renamed to
just agesa).
Boot-tested and confirmed to work, on my board Linux can now access the
whole RAM.
Change-Id: I31d66a488a7811d214d84653860b3e0116f67d19
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/48
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
wborder didn't provide default characters to draw a border.
Change-Id: Ib746ed16be341598fd9fa1f1b7577606d1abd9e5
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/84
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
That lint test requires some Kconfig defaults and uses allyesconfig
for that. Unfortunately that also draws in ccache and scanbuild support,
which significantly change the behaviour of the toplevel Makefile.
Notably, the ccache support breaks if no ccache is installed.
Change-Id: I17cbb7974be33fc077e5cbd5fb616a5b00a47d97
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/80
Tested-by: build bot (Jenkins)
This allows coreboot to compile without Internet connectivity
Change-Id: I969471e44e417f127fdc8744e868211500acee3e
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/11
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Align the spinlock to the 4 byte boundary (CPU will guarantee atomicity of XCHG).
While at it add the PAUSE instruction to spinlock loop to hint the CPU we are just
spinlocking. The rep nop could not be used because "as" complains that rep is used
without string instructions.
Change-Id: I325cd83de3a6557b1bee6758bc151bc81e874f8c
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/81
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
- its Makefile is part of the libpayload project
- fix conversion bug in powerpc's Makefile.inc
Change-Id: I84f2da092c3733ea7d0f232cb3768078cf13dfd5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/79
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
libpayload's license is more liberal than coreboot's. If we are to
use the coreboot build system for libpayload (bringing a couple of
new features to libpayload), we should adopt it for this shared part
even if not strictly necessary.
Change-Id: I1349616861e193b3e01407debbec3d82e09e72c2
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/70
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
To avoid using untrusted network to download code, copy the
relevant file to the repo and adapt "make gitconfig" to copy
from there.
Change-Id: I21f0b58d59250aa5d795cf289267ad93bd8d74db
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/73
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
Tested-by: build bot (Jenkins)
The new build system uses quite a few more -W flags for the compiler by
default than the old one. And that's for the better.
Change-Id: Ia8e3d28fb35c56760c2bd0983046c7067e8c5dd6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/72
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
This change makes building coreboot related projects more unified.
Change-Id: I0f1181e2fffde1e03675523f7dc9eef3119052c3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/71
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
for the transmit clock driving control. Unfortunately this is not enough
to make the HT1000 work reliably, therefore blacklist this for now in CPU
HT code. If ever anyone figure out what is wrong, it could be removed. The
downgrading now makes the board work on HT800, which is certainly better than
not at all with a HT1000 CPU.
Change-Id: I949bfd9b0b48ee12bd0234c2fb1deaaa773bd235
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/68
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The Aaeon PFM-540I RevB SBC is a PC104 SBC using a AMD Geode LX800 CPU.
More infomation about the board available at www.aaeon.com.
Change-Id: Ia8a3caacdc9ff1820a6c0a13a9a7ee758b929dfd
Signed-off-by: Mark Norman <mpnorman@gmail.com>
Reviewed-on: http://review.coreboot.org/30
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
My Thinkpad appeared dead. After investigation, it turned out
that the RTC Alarm was triggering an RTC PM1 SMI, but the SMI
handler didn't read the status register, so it was triggered again.
This is a really nasty situation, as it means you have to dissemble
your Notebook just to unplug the RTC battery.
Change-Id: I5ac611e8a72deb5f38c86486dbe0693804935723
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/67
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Libpayload shouldn't count on coreboot or other payloads to clear memory. This fixes problems with payloads being loaded after or on top of each other.
Change-Id: I30303d47e465e8921f47acab667c7998ba79fca7
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/66
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
sb800 pci bridge SHOULD enabled by default according to the chipset document,
but actually not enabled on some mainboard.
enable sb800 pci bridge when told to enable in devicetree.cb.
tested on ibase persimmon mainboard.
Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/63
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Keith Hui