Commit Graph

41190 Commits

Author SHA1 Message Date
Xi Chen b8f03fd0ca vendorcode/mt8192: fix fast-k gating PI P1 initialization
In RX Gating flow, PI P1 delay is missing, so re-add the initialization.

Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: Ic72ccecd205062ee79f6928993fac772fc10f880
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-16 03:50:05 +00:00
Xi Chen 995eed9fef vendorcode/mt8192: limit fast-k frequency count from 7 to 3
For bootup faster, fast-k elapsed time is improved by ~400ms.

Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: Ifa945012aa66df4433fe63aab75a1e785d343d9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51406
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16 03:49:09 +00:00
Hung-Te Lin 46d05bcc4e mb/google/asurada: fix boot failure when reading SKU ID
The SKU IDs also need mapping table when reading voltages.

BUG=None
BRANCH=asurada
TEST=emerge-asurada coreboot

Change-Id: Ice91961d6c33cfa27254221663edca1547c9ddcc
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-16 03:48:27 +00:00
Mathew King 00b490dd59 mb/google/guybrush: Add initial fch irq routing
BUG=b:181972598
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I1abb070324254e21b03bfe00d6eee3b70120564c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-16 02:33:38 +00:00
Mathew King 447cb44696 mb/google/guybrush: Enable eSPI VW SCI events
Guybrush does not have a dedicated SCI pin so it uses VW.

BUG=b:181134664
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I12fb7c23718ad2350478b89b321e9f0aa099e53b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51238
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 16:20:45 +00:00
Karthikeyan Ramasubramanian 913824c910 mb/google/dedede/var/magolor: Fix DPTF passive and critical policies
Some of the temperature sensors defined in baseboard do not exist in
magolor. With the format the DPTF policies are defined in magolor, all
the entries from the baseboard are included and then the overrides
applied. This causes the non-existent DPTF devices to be exported in
the ACPI table and in turn OS reading invalid temperatures. Fix the
format for DPTF passive and critical policies.

BUG=None
BRANCH=dedede
TEST=Build and boot to OS in magolor. Ensure that the DPTF entries look
correct in both static.c and SSDT tables i.e. passive and critical
policies for applicable devices only are present.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I43f0b188e49e24657db055ce898ce159d499a22e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-15 16:08:43 +00:00
Karthikeyan Ramasubramanian ab8961e7be mb/google/dedede/var/madoo: Fix DPTF passive and critical policies
Some of the temperature sensors defined in baseboard do not exist in
madoo. With the format the DPTF policies are defined in madoo, all the
entries from the baseboard are included and then the overrides applied.
This causes the non-existent DPTF devices to be exported in the ACPI
table and in turn OS reading invalid temperatures. Fix the format for
DPTF passive and critical policies.

BUG=b:182513022
BRANCH=dedede
TEST=Build and boot to OS in madoo. Ensure that the DPTF entries look
correct in both static.c and SSDT tables i.e. passive and critical
policies for applicable devices only are present.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Idc5d0b357d61b9346b4d20ec8322b124c9655b4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-15 16:08:22 +00:00
Alexander Couzens 1295fa218f mb/supermicro/x11-lga1151-series: add support of X11SSH-LN4F to X11SSH-F
The X11SSH-LN4F and X11SSH-F are very similiar. They both use the same
PCB and use the same Supermicro BIOS ID. The X11SSH-LN4F has 4 NICs in
difference to the X11SSH-F which only has 2 NICs. The two additional
NICs aren't populated on the X11SSH-F. Enable the PCIe root ports
connected to the two additional Intel NICs.

Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: Id4e66be47ceef75905ba760b8d5a14284e130f63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-03-15 09:45:23 +00:00
Patrick Rudolph 1d242799c2 mb/prodrive/hermes: Drop AZALIA_PLUGIN_SUPPORT
Already selected by SoC.

Change-Id: I1d941881f50350b6b581416a2e722ea2e7485a1c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-15 06:32:00 +00:00
Tao Xia b01a4c5757 mb/google/dedede/var/sasukette: Add USB2 PHY parameters
This change adds fine-tuned USB2 PHY parameters for sasukette.

BUG=180753635
TEST=Built and verified USB2 eye diagram test result

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I5612e7dcca15b340763dee1475e979ee551a2146
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-15 06:30:59 +00:00
John Zhao f3a8bf13cb soc/intel/alderlake: Drop 100ms delay and do not poll Link Active
Drop the 100ms delay in the _PS0 method because kernel already adds this
100ms. This change also drops polling TBT PCIe root ports Link Active
State because this scheme is not applicable for SW CM.

BUG=None
TEST=Built Alderlake coreboot image successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51191
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:30:52 +00:00
Kevin Chang 80273918d5 mb/google/volteer/variant/lindar: Disable SA GV for Samsung memory with wrong date code MB
Disable SA GV, because factory used Samsung memory with wrong date code.
So we need to use board version to identify build MB phase to disable SA GV.
Disable SA GV when board version equal one.

BUG=b:179747696
BRANCH=firmware-volteer-13672.B
TEST=Built and booted into OS.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I51f4adcf0dd8dbf1cf39d8aec6e4303565551e5f
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15 06:30:35 +00:00
Johnny Lin 30cb21811b vc/intel/fsp/fsp2_0/cooperlake_sp: Update memory map hob for WW06 FSP
Change-Id: Id534e1b73e73bbb9d944c988d1ef66bc1f463eff
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50867
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Deomid "rojer" Ryabkov <rojer9@fb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:30:05 +00:00
Bora Guvendik 9d4d2d014c mb/intel/tglrvp: Enable RTD3 for WWAN
Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root
Port 4 and provide the reset GPIO / src clk pin.

BUG=none
TEST=Boot to OS, verify the link is in L2 state during S0ix.

Change-Id: I669e02bd02e3af878648a6f3cf4fbb4d06c9857f
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2021-03-15 06:29:56 +00:00
chenzanxi 011e1b3fbc mb/google/dedede/var/storo: Support LTE module
Add LTE module support into devicetree and associated GPIO configuartion.

BUG=b:177955524
BRANCH=dedede
TEST=LTE function is OK

Change-Id: I9aff9608e08eae00ab5ac8547f63bc83b62fea78
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-15 06:28:59 +00:00
chenzanxi 46ee366216 mb/google/dedede/var/storo:Add P-sensor for storo
Add P-sensor into devicetree for storo according to
configuration information provided by the vendor.

BUG=b:177392203
BRANCH=dedede
TEST=built storo firmware and verified P-sensor function

Change-Id: Iced4ab7d94b38ef8b1807955cbb887454accb1e8
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
2021-03-15 06:28:46 +00:00
chenzanxi f8aa8dc248 mb/google/dedede/var/storo: Add codec and speaker amplifier support
Add audio codec and speaker amplifier support into devicetree

BUG=b:179057895
BRANCH=dedede
TEST=audio function is OK

Change-Id: Ia864ac47223adb80463966209f6ff3640b715378
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51003
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:28:32 +00:00
chenzanxi c4691ab754 mb/google/dedede/var/storo: Add camera support
To support mipi camera.
1. enable DRIVERS_INTEL_MIPI_CAMERA/SOC_INTEL_COMMON_BLOCK_IPU
2. add IPU/VCM/NVM/CAM1 into devicetree
To support usb camera.
add camera support in devicetree and associated GPIO configuration.

BUG=b:177393430, b:177388006
TEST=Build and boot to OS. Camera function is OK.

Change-Id: I98d5708d1955406c2e46db972903057bb3d12dcc
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50995
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:28:18 +00:00
Da Lao e325a4d0dc mb/lenovo/t440p: update VBT to version 2179
Update T440p's VBT from version 1215 to version 2179. Extracted
using VBiosFinder (https://github.com/coderobe/VBiosFinder)
from the latest bios update file:
https://download.lenovo.com/pccbbs/mobiles/gluj42us.iso

The new version solves the problem that DP output was broken
under Windows.

Test: boot t440p with both SeaBIOS and Tianocore payloads,
verify dp output and backlight control all works under both
Linux and Windows.

Signed-off-by: Da Lao <dalao@tutanota.com>
Change-Id: If8669b8de6fa0801e261138651b8b2cf50432a70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jamal Wright <Crabstorage@getbackinthe.kitchen>
2021-03-15 06:28:12 +00:00
Benjamin Doron 234f8e0405 security/intel/stm/Makefile.inc: Fix typo
In both the Kconfig and Makefile in this directory,
"STM_TTYS0_BASE" is used. Therefore, fix the typo.

Change-Id: Ie83ec31c7bb0f6805c0225ee7405e137a666a5d3
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51206
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:27:30 +00:00
Cliff Huang 172d2d140d soc/intel/tigerlake: Remove obsolete CNVi Bluetooth PCI device
There is no PCI host interface for this version of CNVi BT.
CNVi BT on Tigerlake is an USB device.

Change-Id: Ib71a827c36dfac55c3e5ce586b00a26fc6264464
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50900
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:27:15 +00:00
Cliff Huang 3663fb36ec mb/intel/tglrvp/variants: Disable non-existing BT PCI interface and add BT flag
Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface
in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is
enumerated.

Change-Id: I8de5615235f24e6169bf67dbbadb92e69437bc4e
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50899
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:26:37 +00:00
Cliff Huang 2eee6c3a7d mb/google/volteer/variants: Disable non-existing BT PCI interface and add BT flag
Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface
in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is
enumerated.

Change-Id: Ic700021d7a09be63ffc2715f31992257e2e893af
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50898
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:26:25 +00:00
Kenneth Chan 285f20a7f0 mb/google/hatch: Update DPTF parameters for genesis
update the DPTF parameters received from the thermal team.

BUG=b:181627614
TEST=emerge-ambassador coreboot

Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ied6b71d9285662a70446af2e781b630e184c3b19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joe Tessler <jrt@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-15 06:25:29 +00:00
Cliff Huang 81f70a9fdf soc/intel/alderlake: Remove obsolete CNVi Bluetooth PCI device
There is no PCI host interface for Cnvi BT in Alderlake.
CNVi BT on Alderlake is an USB device.

Change-Id: I3e08c6d6f00e81267dc28c9b37b2dfff5cd75db1
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51352
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:25:20 +00:00
Cliff Huang 9b725cf311 mb/google/brya: Remove BT PCI interface and add BT flag
Remove the CNVi BT PCI config and add Bt flag.
There is no PCI host interface in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS.

Change-Id: I7e8ca1bb6a57721a72478137612d7a9c391ca0b2
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15 06:25:14 +00:00
Cliff Huang b1a128fc88 mb/intel/adlrvp: Disable non-existing BT PCI interface and add BT flag
Remove the CNVi Bt PCI config and add Bt flag.
There is no PCI host interface in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS.

Change-Id: I17c3e2761f91fb397d140d1954b6d4b451c4c603
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15 06:24:56 +00:00
Cliff Huang bc1941f178 soc/intel/alderlake: Add CNVi Bluetooth flag at devicetree entry
This change adds the corresponding CNVi BT Core enabling flag.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS.

Change-Id: Iecc10c8946a450350adb34b984cf48ad988097ca
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51350
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:24:48 +00:00
Cliff Huang b34be4d4bb soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry
FSP has added the Cnvi BT Core enabling in addition to the existing
CnviMode. This change adds the flag at the soc config side (i.e.
soc_intel_tigerlake_config for devicetree). Also, there is no longer PCI host
interface for BT. Therefore, BT core should not use the pci port status to turn
on/off.

TEST: BT enumeration is checked using 'lsusb -d 8087:0026' from OS to make
        sure BT is turned on.

Change-Id: I71c512fe884060e23ee26e7334c575c4c517b78d
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15 06:24:14 +00:00
Ravi Kumar Bokka ce97bca09c sc7180: make symbols common accross multiple targets.
making the symbols common accross targets to avoid duplicates for each soc.

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: Ic60f46891dfadc7db5ece02756cb449aacdd63c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-03-15 06:23:06 +00:00
Eric Lai 8da56e6e75 drivers/generic/alc1015: Change HID name for driver
From ALSA reviewer suggest to change the name to RTL1015.
Details in below threads:
https://www.spinics.net/lists/alsa-devel/msg123395.html

BUG=b:177971830
TEST=: ALC1015P driver can probe properly.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2762852bdc3164346e3618c373aa4d3336415653
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-15 06:21:20 +00:00
Eric Lai d8e6d3e230 drivers/generic/alc1015: Fix missing _DSD and correct property name
Missing acpi_dp_write and correct the name from sdb to sdb-gpios for
driver.

BUG=b:177971830
TEST: ALC1015P driver can get sdb-gpio properly.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2728a7dad695d5c97e85c5d86b1effea1595da65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51379
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:20:55 +00:00
Bryant Ou f6efeae66c mb/ocp/deltalake: Override uart base address via VPD variable
Use VPD of "coreboot_uart_io" to select uart io if
OVERRIDE_UART_FOR_CONSOLE is selected.

Tested=On OCP Delta Lake, console messages correctly output to uart
port which is defined in VPD.

Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com>
Change-Id: I55a85d6f137ef1aba95466e7b094740b685bf9bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-03-15 06:18:39 +00:00
FrankChu f8b2d32ad9 mb/google/volteer: Create collis variant
Create the collis variant of the volteer reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:182227204
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_COLLIS

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ibcf8b59b38d02517cea0a3ee474ff82fc0a2a958
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-03-15 06:18:27 +00:00
Meera Ravindranath 8dffc38f6e mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
Add support to pick the right vbt from cbfs according to
SKU-ID.

Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15 06:16:50 +00:00
Tim Chu e82aa2238d mb/ocp/deltalake: Override SMBIOS type 2 feature flags
Override SMBIOS type 2 board feature flags. For Delta Lake, board is
replaceable and is a hosting board.

Tested=Execute "dmidecode -t 2" to check info is correct.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I4469360ec51369dbf8179b3cbac0519ead7f0382
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-03-15 06:12:40 +00:00
Eric Lai 4f4e86ec5e mb/google/mancomb: Configure non-native function GPIOs
Follow 20210308 schematic.

BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib259f3defc606c373f5ccac5f022d93e9a5c1469
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-15 06:11:54 +00:00
Eric Lai 0b18296ca0 mb/google/mancomb: First pass GPIO configuration
Follow 20210308 schematic.

BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1720ea8fec004d3ed3b3faaffa3b37dfcd710241
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-15 06:11:41 +00:00
Zhuohao Lee e6f12d0d50 rammus: get cbfs sar table name based on the sku id
This patch overrides the get_wifi_sar_cbfs_filename()
to return different sar table according to the sku id.

BUG=b:173465272
TEST=checked bios log and the correct sar table was loaded.

Change-Id: Ia30d760b1a029197d470818c73bfd2c00514652d
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15 06:10:44 +00:00
Jan Dabros 9e16ca9dec tests: Add lib/memrange-test test case
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: If30a238d32326ffd1d6719470deedc77f176ac72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-03-15 06:10:24 +00:00
hao_chou a776ebb801 mb/google/volteer/variants/copano: Add gpio-keys ACPI node for PENH
Use gpio_keys driver to add ACPI node for pen eject event.
Also setting gpio wake pin for wake events.

BUG=b:175519097
BRANCH=firmware-volteer-13672.B
TEST=build and verify on a Copano

Change-Id: Id0a132aa398abde4983af123d00e355ac61839a8
Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51249
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:09:51 +00:00
Aamir Bohra 7f61e5703b mb/intel/shadowmountain: Add ACPI entry for BT reset GPIO
Change-Id: Ia9e57f34eceaf1925dc5e3ffa6370ba0241447a4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-03-15 06:09:27 +00:00
Kevin Chang d2c4797891 mb/google/volteer: Add WiFi SAR table support for Lindar/Lillipup
Lindar/Lillipup uses the WIFI_SAR_ID field in FW_CONFIG to pick which
SAR table to load.

BUG=b:178302811
BRANCH=volteer
TEST=build and test no lindar/lillipup

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ibe829062033ba8246b9d9550cdcdc360f5f67dd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
2021-03-15 06:08:33 +00:00
Kevin Chang 1c02f6f088 mb/google/volteer/var/lindar: Add FW_CONFIG WIFI_SAR_ID fields in devicetree
Add FW_CONFIG WIFI_SAR_ID fields in devicetree.

BUG=b:178302811
BRANCH=volteer
TEST=build and test on lindar/lillipup

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I7ec37b80ffca6924f1f0952dcfbc43c378a70923
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51386
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:08:19 +00:00
Eric Lai 1d6a13c7ee mb/google/octopus/var/fleex: Add RTL5682 support
Fleex will use SSFC to support RTL5682.

BUG=b:178653122
TEST=abuild

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Icb06eabe297c5562bd2171b52cc9671c342e6dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
2021-03-15 06:06:21 +00:00
Seunghwan Kim e990f345c4 mb/google/dedede/var/sasuke: Update LTE GPIO configuration
Update GPP_A10 and GPP_H17 configuration to meet LTE power sequence
specification.
- FCPO (GPP_A10) should not turned off during warm reset.

BUG=b:177177967
BRANCH=dedede
TEST=Verified LTE power signal waveforms during powering on and off

Change-Id: I469f9c94ebd6bf2b68a0edc74f229158d82d0ef8
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-15 06:05:18 +00:00
Nico Huber 968ef75988 pciexp_device: Rewrite LTR configuration
I was bugged by spurious "Failed to enable LTR" messages for years.
Looking at the the current algorithm, it is flawed in multiple ways:

* It looks like the author didn't know they implemented a
  recursive algorithm (pciexp_enable_ltr()) inside another
  recursive algorithm (pciexp_scan_bridge()). Thus, at every
  tree level, everything is run again for the whole sub-
  tree.

* LTR is enabled no matter if `.set_ltr_max_latencies` is
  implemented or not. Leaving the endpoints' LTR settings
  at 0: They are told to always report zero tolerance.
  In theory, depending on the root-complex implementation,
  this may result in higher power consumption than without
  LTR messages.

* `.set_ltr_max_latencies` is only considered for the direct
  parent of a device. Thus, even with it implemented, an
  endpoint below a (non-root) bridge may suffer from the 0
  settings as described above.

* Due to the double-recursive nature, LTR is enabled starting
  with the endpoints, then moving up the tree, while the PCIe
  spec tells us to do it in the exact opposite order.

With the current implementation of pciexp_scan_bridge(), it is
hard to hook anything in that runs for each device from top to
bottom. So the proposed solution still adds some redundancy:

First, for every device that uses pciexp_scan_bus(), we enable
LTR if possible (see below). Then, when returning from the bus-
scanning recursion, we enable LTR for every device and configure
the maximum latencies (if supported). The latter runs again on
all bridges, because it's hard to know if pciexp_scan_bus() was
used for them.

When to enable LTR:

* For all devices that implement `.set_ltr_max_latencies`.
* For all devices below a bridge that has it enabled already.

Change-Id: I2c5b8658f1fc8cec15e8b0824464c6fc9bee7e0e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51328
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:04:38 +00:00
Felix Held ec2cbecf93 mb/google/kahlee: remove get_gpe_table
Since no board overrides the weak get_gpe_table function,
gpe_configure_sci wasn't called for any variant, so drop the function.

TEST=none

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3de204cc808449b625e1fa1e79fe653608e4b88a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-15 06:04:31 +00:00
Tim Wawrzynczak 8996b277ab mb/intel/adlrvp: Select ADL_ENABLE_USB4_PCIE_RESOURCES
This change select the Kconfig to pre-allocate the Intel-recommended bus
and memory resources per-PCIe TBT root port for the adlrvp mainboard.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic56ebab02e50a466662a07d122d8f40eaf16b54b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51461
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:03:55 +00:00
Tim Wawrzynczak 7b97289d56 mb/google/brya: Select ADL_ENABLE_USB4_PCIE_RESOURCES for brya0
This change select the Kconfig to pre-allocate the Intel-recommended bus
and memory resources per-PCIe TBT root port for the brya0 mainboard.

TEST=snippet from dmesg logs shows the correct resources being allocated:
   PCI: 00:07.0 resource base 27fc00000 size 1c000000 align 20 gran 20 limit 29bbfffff flags 60181202 index 24
   PCI: 00:07.0 resource base 83000000 size c200000 align 20 gran 20 limit 8f1fffff flags 60080202 index 20
   PCI: 00:07.1 resource base 29bc00000 size 1c000000 align 20 gran 20 limit 2b7bfffff flags 60181202 index 24
   PCI: 00:07.1 resource base a0000000 size c200000 align 20 gran 20 limit ac1fffff flags 60080202 index 20
   PCI: 00:07.2 resource base 2b7c00000 size 1c000000 align 20 gran 20 limit 2d3bfffff flags 60181202 index 24
   PCI: 00:07.2 resource base ac200000 size c200000 align 20 gran 20 limit b83fffff flags 60080202 index 20

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6b520ae50f19a730263de7918594718f3b4b1c1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51455
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:03:45 +00:00