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7 commits

Author SHA1 Message Date
Curtis Chen
1f8563ec0e soc/intel/alderlake: Add ADL-P 6+8+2 (28W) VR config 
We only have ADL-P 6+8+2 (45W) VR configuration now. Based on the
power map, fill in correct ADL-P 6+8+2 (28W) VR configuration.

BUG=b:202486131
TEST=Build and check fsp log to confirm the settings are set properly.

Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: Ie8dbd95b2d8e49b5898b2a97aff72e0e64868c8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-12-06 16:39:57 +00:00
Curtis Chen
ea1bb5f7de soc/intel/alderlake: Add TDP to give correct VR configuration 
The VR configuration should be based on the different Soc SKU type. And
we also have different SKU in the same SA PCI ID.

Therefore, add TDP to recognize the correct SKU and give the correct
power setting.

BUG=b:202486131
TEST=Build and check fsp log to confirm the settings are set properly.

Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: I4d31e7afc76d9a8c772781671f92ec08f9d8713f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-12-03 15:37:44 +00:00
Curtis Chen
0c54461cf9 soc/intel/alderlake: Add ADLP 4+4+2 power configurations 
Map existing PCI_DEVICE_ID_INTEL_ADL_P_ID_1 to ADLP 4+4+2 45W SKU power
related settings.
Per doc#626774 ADL_MOW_WW46_2021, update PD optimization relaxation for
ADL-P 482(28W) and 442(45W).

BUG=b:193864533
TEST=Build and check fsp log to confirm the settings are set properly.

Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-11-25 19:43:00 +00:00
Bora Guvendik
f6f1258673 soc/intel/alderlake: Allow devicetree override to leave some VR settings as default 
Allow devicetree override to leave ac_loadline, dc_loadline and icc_max as default.

Test=Boot to OS

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I715345d5ea83aed9ee929b2a4e13921c9d8895b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-11-03 09:33:12 +00:00
Tracy Wu
697d6a81c2 soc/intel/alderlake: Add ADLP 242 power configurations 
Add ADLP 242 sku power related settings, which follow the settings of
ADLP 282 sku (both are 15w).

BUG=b:201253904
TEST=Build and check fsp log to confirm the settings are set properly.

Change-Id: I829dd690c22d167a507b1910106da06b275cec09
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2021-09-29 10:07:00 +00:00
Ronak Kanabar
1f88a71aa8 soc/intel/alderlake: Enable Irms UPD for ADL 
This change sets Irms config in FSP if TdcTimeWindow and TdcCurrentLimit
is set to non zero. It results VR TDC Input current to be treated as it
is root mean square.

This change also optimizes the check of TdcTimeWindow and TdcCurrentLimit
for TdcEnable UPD.

BRANCH=None
TEST=Build and boot brya with debug FSP and verify Irms UPD value
from logs

Change-Id: Ice5c775ef9560503109957a1ed994af1d287aafc
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
 2021-09-09 14:41:52 +00:00
V Sowmya
c6d7166942 soc/intel/alderlake: Configure the SKU specific parameters for VR domains 
This patch configures the SKU specific power delivery parameters for the
VR domains.
+--------------+-------+-------+-------+-------+-----------+--------+
|      SKU     |Setting| AC LL | DC LL |ICC MAX|TDC Current|TDC Time|
|              |       |(mOhms)|(mOhms)|  (A)  |     (A)   |  (msec)|
+--------------+-------+-------+-------+-------+-----------+--------+
|ADL-P 682(45W)|   IA  |  2.3  |  2.3  |  160  |     57    | 28000  |
+              +-------+-------+-------+-------+-----------+--------+
|              |   GT  |  3.2  |  3.2  |   50  |     57    | 28000  |
+--------------+-------+-------+-------+-------+-----------+--------+
|ADL-P 482(28W)|   IA  |  2.3  |  2.3  |  109  |     40    | 28000  |
+              +-------+-------+-------+-------+-----------+--------+
|              |   GT  |  3.2  |  3.2  |   50  |     40    | 28000  |
+--------------+-------+-------+-------+-------+-----------+--------+
|ADL-P 282(15W)|   IA  |  2.8  |  2.8  |   80  |     20    | 28000  |
+              +-------+-------+-------+-------+-----------+--------+
|              |   GT  |  3.2  |  3.2  |   40  |     20    | 28000  |
+--------------+-------+-------+-------+-------+-----------+--------+

These config values are generated iPDG application with ADL-P platform
package tool and supports 15W/28W/45W SKU's.
RDC Kit ID for the iPDG tools,
* Intel(R) Platform Design Studio Installer: 610905.
* Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345.
* Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261.

BUG=b:195033556

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56325
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-08-12 19:32:34 +00:00