enable that area once the register is set so print a warning.
Signed-off-by: Marc Jones <marcj.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This is useless, as it changes with each access; it doesn't convey any
useful information at all.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The ICH9 and ICH10 data sheets are identical regarding FWH/SPI flash
interfaces, so this just adds the required PCI IDs.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested on actual hardware, the MSI K9AG Neo2-Digital (MS-7368).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Probing, reading, and erasing use the Jedec-routines,
whereas writing resort to the recent write_en29f002a(),
since also these chips use a byte wise algorithm.
Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It replaces the write function to one based on write_byte_program_jedec()
instead of write_page_write_jedec(), as this part does not support page
programming.
I have verified the NT variant to fully work now, and adjusted the test
status accordingly. The N variant *should* also work with this patch, but
remains untested.
Signed-off-by: Tim ter Laak <timl@scintilla.utwente.nl>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Per report from Daniel Lindenaar. Thanks!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
All operations tested by me on hardware.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
To add a string to your cmos.layout, you need to specify type 's':
#start len type unused name
416 512 s 0 boot_devices
With this patch you can do
$ nvramtool -w boot_devices="(hd0,0);(hd2,1);(hd3)"
And FILO will attempt to load a menu.lst from any of these devices in that
order.
The patch is not exactly pretty, but a cleaner solution might have resulted in
a complete rewrite of the tool, which I did not want.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Fully tested for Probe/Read/Erase/Write on EN29F002NT.
Jedec subroutines 'probe_jedec()' and 'erase_chip_jedec()'
are still in use, but a tailored 'write_en29f002a()' is
needed due to a byte wise writing mechanism for this chip.
Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Per report from Kevin O'Connor. Thanks Kevin!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
targets/*/*/Makefile
targets/*/*/normal/Makefile
targets/*/*/fallback/Makefile
to use a common copy of romcc, and to leave this compiler untouched by
'make clean' in targets/*/*/fallback/ and targets/*/*/normal/ .
'make clean' in targets/*/*/ will clean romcc.
Thanks to Mats for the initial idea and implementation of a tool to do
this. This patch has almost the same behaviour as the original tool
without having to run the tool each time.
Tested for abuild-friendliness.
The patch saves ~10-12 seconds for every target using romcc. For a full
abuild run, this is ~20% time saved.
For the first 38 abuild targets, total build time is down to 13m24s
instead of 16m22s on my machine.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This removes the false positive matches we've been seeing, and also removes
the true positive match in case there is more than one flash chip and the 2nd
or 3rd are unknown - but I think that case is uncommon enough to warrant the
improvement in the common case. Use flashrom -frc forced read if you have the
uncommon case, and/or please add the flash chip to the flashchips array.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Per test report from Bari Ari. Thanks!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Per test report from Ward.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
immensly when they know more systems / cpus / chipsets
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the KT3 Ultra 2 with "-m msi:kt4v" (but is not autodetected, yet).
Signed-off-by: Sean Nelson <snelson@nmt.edu>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Don't calculate "flash_baseaddr" until the final value of "size"
is known, otherwise we end up trying to map a page right after
the end of memory.
Fixes#112.
Signed-off-by: Segher Boessenkool <segher@kernel.crashing.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3502 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Per test report from Marcel Konrad. Thanks!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
packages/mkelfimage/mkelfimage-autoconf.patch
packages/mkelfimage/mkelfImage-2.7-x86_64.patch
to our svn copy of mkelfimage.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
These are the original commit messages from the buildrom svn tree:
-----------------------------------------------------------------------
r61 | jcrouse | 2007-11-28 13:06:23 -0500 (Wed, 28 Nov 2007) | 9 lines
[BUILDROM] Fixup mkelfimage
My patch makes it so all targets use vmlinux and 2.7. Including
the mkelfimage patch from Yhinghai Lu.
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
------------------------------------------------------------------------
r80 | jcrouse | 2007-12-10 13:56:40 -0500 (Mon, 10 Dec 2007) | 8 lines
[BUILDROM] Fix breakage in the new mkelfimage autoconf scripts
Whack the autoconf scripts in mkelfimage to allow us to pass our
stack protection flags in.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
------------------------------------------------------------------------
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(doesn't make sense in v2). For silent build, use make -s
(trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
W39V040C does standard JEDEC commands except chip erase so add a small driver.
probe_w39v040c() prints the block lock pin status when a chip is found.
The Neo2 board enable matches on 8237-internal IDE and onboard NIC PCI IDs.
Many thanks to Daniel McLellan for testing all of this on hardware!
Build tested by Uwe.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
and scattered within the datasheets. (trivial patch)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3428 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
While writing a new SPI driver I fixed some things in the SPI code:
All calls to spi_command() had unneccessary #define duplications, and in some
cases the read count define could theoretically become harmful because NULL was
passed for the read buffer. Avoid a crash, should someone change the #defines.
I also noticed that the only caller of spi_page_program() was the it87 driver,
and spi_page_program() could only call back into the it87 driver. Removed the
function for easier-to-follow code and made it8716f_spi_page_program() static.
The ichspi driver's static page functions are already static.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
flash.h is a database of known IDs, whereas flashchips.c is a database
of chips for which support has been implemented. Keep it that way.
Trivial.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3416 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This patch adds support to the AMIC A29002 chip in its top and bottom
configuration to flashrom. Additionally, the alphabetic order of the
AMIC chips was fixed.
The datasheet is at <http://www.amictechnology.com/pdf/A29002.pdf>.
A29002T PREW functionality was tested and works.
This flash chip has asymmetric sector layout so it is important to use the
mx29f002 driver, which does chip erase before writing, rather than am29f040b,
which uses sector erase.
Signed-off-by: Andreas Thienemann <andreas@bawue.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Uses the 0.0 Host bridge CN700/VN800/P4M800CE/Pro and 11.0 ISA bridge devices
with their 1106:aa08 subsystem id:s for autodetection.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Thanks to Paul Seidler and Ward Vandewege for testing.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Per test report from Björn Gerhart. Thanks!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
absolutely perfect, but the likelihood of this check to fail is
0.000000000000000000000000013 (1.3*10^-26) which is good enough for me.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3408 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Marc Jones